1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include <stdio.h>
29
30 #include "CUnit/Basic.h"
31
32 #include "util_math.h"
33
34 #include "amdgpu_test.h"
35 #include "uvd_messages.h"
36 #include "amdgpu_drm.h"
37 #include "amdgpu_internal.h"
38
39 #define IB_SIZE 4096
40 #define MAX_RESOURCES 16
41
42 static amdgpu_device_handle device_handle;
43 static uint32_t major_version;
44 static uint32_t minor_version;
45 static uint32_t family_id;
46 static uint32_t chip_rev;
47 static uint32_t chip_id;
48
49 static amdgpu_context_handle context_handle;
50 static amdgpu_bo_handle ib_handle;
51 static uint64_t ib_mc_address;
52 static uint32_t *ib_cpu;
53 static amdgpu_va_handle ib_va_handle;
54
55 static amdgpu_bo_handle resources[MAX_RESOURCES];
56 static unsigned num_resources;
57
58 static void amdgpu_cs_uvd_create(void);
59 static void amdgpu_cs_uvd_decode(void);
60 static void amdgpu_cs_uvd_destroy(void);
61
62 CU_TestInfo cs_tests[] = {
63 { "UVD create", amdgpu_cs_uvd_create },
64 { "UVD decode", amdgpu_cs_uvd_decode },
65 { "UVD destroy", amdgpu_cs_uvd_destroy },
66 CU_TEST_INFO_NULL,
67 };
68
suite_cs_tests_init(void)69 int suite_cs_tests_init(void)
70 {
71 amdgpu_bo_handle ib_result_handle;
72 void *ib_result_cpu;
73 uint64_t ib_result_mc_address;
74 amdgpu_va_handle ib_result_va_handle;
75 int r;
76
77 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
78 &minor_version, &device_handle);
79 if (r) {
80 if ((r == -EACCES) && (errno == EACCES))
81 printf("\n\nError:%s. "
82 "Hint:Try to run this test program as root.",
83 strerror(errno));
84
85 return CUE_SINIT_FAILED;
86 }
87
88 family_id = device_handle->info.family_id;
89 /* VI asic POLARIS10/11 have specific external_rev_id */
90 chip_rev = device_handle->info.chip_rev;
91 chip_id = device_handle->info.chip_external_rev;
92
93 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
94 if (r)
95 return CUE_SINIT_FAILED;
96
97 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
98 AMDGPU_GEM_DOMAIN_GTT, 0,
99 &ib_result_handle, &ib_result_cpu,
100 &ib_result_mc_address,
101 &ib_result_va_handle);
102 if (r)
103 return CUE_SINIT_FAILED;
104
105 ib_handle = ib_result_handle;
106 ib_mc_address = ib_result_mc_address;
107 ib_cpu = ib_result_cpu;
108 ib_va_handle = ib_result_va_handle;
109
110 return CUE_SUCCESS;
111 }
112
suite_cs_tests_clean(void)113 int suite_cs_tests_clean(void)
114 {
115 int r;
116
117 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
118 ib_mc_address, IB_SIZE);
119 if (r)
120 return CUE_SCLEAN_FAILED;
121
122 r = amdgpu_cs_ctx_free(context_handle);
123 if (r)
124 return CUE_SCLEAN_FAILED;
125
126 r = amdgpu_device_deinitialize(device_handle);
127 if (r)
128 return CUE_SCLEAN_FAILED;
129
130 return CUE_SUCCESS;
131 }
132
submit(unsigned ndw,unsigned ip)133 static int submit(unsigned ndw, unsigned ip)
134 {
135 struct amdgpu_cs_request ibs_request = {0};
136 struct amdgpu_cs_ib_info ib_info = {0};
137 struct amdgpu_cs_fence fence_status = {0};
138 uint32_t expired;
139 int r;
140
141 ib_info.ib_mc_address = ib_mc_address;
142 ib_info.size = ndw;
143
144 ibs_request.ip_type = ip;
145
146 r = amdgpu_bo_list_create(device_handle, num_resources, resources,
147 NULL, &ibs_request.resources);
148 if (r)
149 return r;
150
151 ibs_request.number_of_ibs = 1;
152 ibs_request.ibs = &ib_info;
153 ibs_request.fence_info.handle = NULL;
154
155 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
156 if (r)
157 return r;
158
159 r = amdgpu_bo_list_destroy(ibs_request.resources);
160 if (r)
161 return r;
162
163 fence_status.context = context_handle;
164 fence_status.ip_type = ip;
165 fence_status.fence = ibs_request.seq_no;
166
167 r = amdgpu_cs_query_fence_status(&fence_status,
168 AMDGPU_TIMEOUT_INFINITE,
169 0, &expired);
170 if (r)
171 return r;
172
173 return 0;
174 }
175
uvd_cmd(uint64_t addr,unsigned cmd,int * idx)176 static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
177 {
178 ib_cpu[(*idx)++] = 0x3BC4;
179 ib_cpu[(*idx)++] = addr;
180 ib_cpu[(*idx)++] = 0x3BC5;
181 ib_cpu[(*idx)++] = addr >> 32;
182 ib_cpu[(*idx)++] = 0x3BC3;
183 ib_cpu[(*idx)++] = cmd << 1;
184 }
185
amdgpu_cs_uvd_create(void)186 static void amdgpu_cs_uvd_create(void)
187 {
188 struct amdgpu_bo_alloc_request req = {0};
189 amdgpu_bo_handle buf_handle;
190 uint64_t va = 0;
191 amdgpu_va_handle va_handle;
192 void *msg;
193 int i, r;
194
195 req.alloc_size = 4*1024;
196 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
197
198 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
199 CU_ASSERT_EQUAL(r, 0);
200
201 r = amdgpu_va_range_alloc(device_handle,
202 amdgpu_gpu_va_range_general,
203 4096, 1, 0, &va,
204 &va_handle, 0);
205 CU_ASSERT_EQUAL(r, 0);
206
207 r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
208 CU_ASSERT_EQUAL(r, 0);
209
210 r = amdgpu_bo_cpu_map(buf_handle, &msg);
211 CU_ASSERT_EQUAL(r, 0);
212
213 memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
214 if (family_id >= AMDGPU_FAMILY_VI) {
215 ((uint8_t*)msg)[0x10] = 7;
216 /* chip polaris 10/11 */
217 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
218 /* dpb size */
219 ((uint8_t*)msg)[0x28] = 0x00;
220 ((uint8_t*)msg)[0x29] = 0x94;
221 ((uint8_t*)msg)[0x2A] = 0x6B;
222 ((uint8_t*)msg)[0x2B] = 0x00;
223 }
224 }
225
226 r = amdgpu_bo_cpu_unmap(buf_handle);
227 CU_ASSERT_EQUAL(r, 0);
228
229 num_resources = 0;
230 resources[num_resources++] = buf_handle;
231 resources[num_resources++] = ib_handle;
232
233 i = 0;
234 uvd_cmd(va, 0x0, &i);
235 for (; i % 16; ++i)
236 ib_cpu[i] = 0x80000000;
237
238 r = submit(i, AMDGPU_HW_IP_UVD);
239 CU_ASSERT_EQUAL(r, 0);
240
241 r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP);
242 CU_ASSERT_EQUAL(r, 0);
243
244 r = amdgpu_va_range_free(va_handle);
245 CU_ASSERT_EQUAL(r, 0);
246
247 r = amdgpu_bo_free(buf_handle);
248 CU_ASSERT_EQUAL(r, 0);
249 }
250
amdgpu_cs_uvd_decode(void)251 static void amdgpu_cs_uvd_decode(void)
252 {
253 const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
254 uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
255 struct amdgpu_bo_alloc_request req = {0};
256 amdgpu_bo_handle buf_handle;
257 amdgpu_va_handle va_handle;
258 uint64_t va = 0;
259 uint64_t sum;
260 uint8_t *ptr;
261 int i, r;
262
263 req.alloc_size = 4*1024; /* msg */
264 req.alloc_size += 4*1024; /* fb */
265 if (family_id >= AMDGPU_FAMILY_VI)
266 req.alloc_size += 4096; /*it_scaling_table*/
267 req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
268 req.alloc_size += ALIGN(dpb_size, 4*1024);
269 req.alloc_size += ALIGN(dt_size, 4*1024);
270
271 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
272
273 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
274 CU_ASSERT_EQUAL(r, 0);
275
276 r = amdgpu_va_range_alloc(device_handle,
277 amdgpu_gpu_va_range_general,
278 req.alloc_size, 1, 0, &va,
279 &va_handle, 0);
280 CU_ASSERT_EQUAL(r, 0);
281
282 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
283 AMDGPU_VA_OP_MAP);
284 CU_ASSERT_EQUAL(r, 0);
285
286 r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
287 CU_ASSERT_EQUAL(r, 0);
288
289 memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
290 if (family_id >= AMDGPU_FAMILY_VI) {
291 ptr[0x10] = 7;
292 ptr[0x98] = 0x00;
293 ptr[0x99] = 0x02;
294 /* chip polaris10/11 */
295 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
296 /*dpb size */
297 ptr[0x24] = 0x00;
298 ptr[0x25] = 0x94;
299 ptr[0x26] = 0x6B;
300 ptr[0x27] = 0x00;
301 /*ctx size */
302 ptr[0x2C] = 0x00;
303 ptr[0x2D] = 0xAF;
304 ptr[0x2E] = 0x50;
305 ptr[0x2F] = 0x00;
306 }
307 }
308
309 ptr += 4*1024;
310 memset(ptr, 0, 4*1024);
311 if (family_id >= AMDGPU_FAMILY_VI) {
312 ptr += 4*1024;
313 memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
314 }
315
316 ptr += 4*1024;
317 memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
318
319 ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
320 memset(ptr, 0, dpb_size);
321
322 ptr += ALIGN(dpb_size, 4*1024);
323 memset(ptr, 0, dt_size);
324
325 num_resources = 0;
326 resources[num_resources++] = buf_handle;
327 resources[num_resources++] = ib_handle;
328
329 msg_addr = va;
330 fb_addr = msg_addr + 4*1024;
331 if (family_id >= AMDGPU_FAMILY_VI) {
332 it_addr = fb_addr + 4*1024;
333 bs_addr = it_addr + 4*1024;
334 } else
335 bs_addr = fb_addr + 4*1024;
336 dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
337
338 if ((family_id >= AMDGPU_FAMILY_VI) &&
339 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
340 ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
341 }
342
343 dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
344
345 i = 0;
346 uvd_cmd(msg_addr, 0x0, &i);
347 uvd_cmd(dpb_addr, 0x1, &i);
348 uvd_cmd(dt_addr, 0x2, &i);
349 uvd_cmd(fb_addr, 0x3, &i);
350 uvd_cmd(bs_addr, 0x100, &i);
351 if (family_id >= AMDGPU_FAMILY_VI) {
352 uvd_cmd(it_addr, 0x204, &i);
353 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)
354 uvd_cmd(ctx_addr, 0x206, &i);
355 }
356 ib_cpu[i++] = 0x3BC6;
357 ib_cpu[i++] = 0x1;
358 for (; i % 16; ++i)
359 ib_cpu[i] = 0x80000000;
360
361 r = submit(i, AMDGPU_HW_IP_UVD);
362 CU_ASSERT_EQUAL(r, 0);
363
364 /* TODO: use a real CRC32 */
365 for (i = 0, sum = 0; i < dt_size; ++i)
366 sum += ptr[i];
367 CU_ASSERT_EQUAL(sum, 0x20345d8);
368
369 r = amdgpu_bo_cpu_unmap(buf_handle);
370 CU_ASSERT_EQUAL(r, 0);
371
372 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
373 CU_ASSERT_EQUAL(r, 0);
374
375 r = amdgpu_va_range_free(va_handle);
376 CU_ASSERT_EQUAL(r, 0);
377
378 r = amdgpu_bo_free(buf_handle);
379 CU_ASSERT_EQUAL(r, 0);
380 }
381
amdgpu_cs_uvd_destroy(void)382 static void amdgpu_cs_uvd_destroy(void)
383 {
384 struct amdgpu_bo_alloc_request req = {0};
385 amdgpu_bo_handle buf_handle;
386 amdgpu_va_handle va_handle;
387 uint64_t va = 0;
388 void *msg;
389 int i, r;
390
391 req.alloc_size = 4*1024;
392 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
393
394 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
395 CU_ASSERT_EQUAL(r, 0);
396
397 r = amdgpu_va_range_alloc(device_handle,
398 amdgpu_gpu_va_range_general,
399 req.alloc_size, 1, 0, &va,
400 &va_handle, 0);
401 CU_ASSERT_EQUAL(r, 0);
402
403 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
404 AMDGPU_VA_OP_MAP);
405 CU_ASSERT_EQUAL(r, 0);
406
407 r = amdgpu_bo_cpu_map(buf_handle, &msg);
408 CU_ASSERT_EQUAL(r, 0);
409
410 memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg));
411 if (family_id >= AMDGPU_FAMILY_VI)
412 ((uint8_t*)msg)[0x10] = 7;
413
414 r = amdgpu_bo_cpu_unmap(buf_handle);
415 CU_ASSERT_EQUAL(r, 0);
416
417 num_resources = 0;
418 resources[num_resources++] = buf_handle;
419 resources[num_resources++] = ib_handle;
420
421 i = 0;
422 uvd_cmd(va, 0x0, &i);
423 for (; i % 16; ++i)
424 ib_cpu[i] = 0x80000000;
425
426 r = submit(i, AMDGPU_HW_IP_UVD);
427 CU_ASSERT_EQUAL(r, 0);
428
429 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
430 CU_ASSERT_EQUAL(r, 0);
431
432 r = amdgpu_va_range_free(va_handle);
433 CU_ASSERT_EQUAL(r, 0);
434
435 r = amdgpu_bo_free(buf_handle);
436 CU_ASSERT_EQUAL(r, 0);
437 }
438