1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 #include "util/u_format.h"
27 #include "util/u_memory.h"
28 #include "util/u_inlines.h"
29 #include "util/u_string.h"
30 #include "util/u_math.h"
31
32 #include "svga_winsys.h"
33 #include "svga_public.h"
34 #include "svga_context.h"
35 #include "svga_format.h"
36 #include "svga_screen.h"
37 #include "svga_tgsi.h"
38 #include "svga_resource_texture.h"
39 #include "svga_resource.h"
40 #include "svga_debug.h"
41
42 #include "svga3d_shaderdefs.h"
43 #include "VGPU10ShaderTokens.h"
44
45 /* NOTE: this constant may get moved into a svga3d*.h header file */
46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
47
48 #ifdef DEBUG
49 int SVGA_DEBUG = 0;
50
51 static const struct debug_named_value svga_debug_flags[] = {
52 { "dma", DEBUG_DMA, NULL },
53 { "tgsi", DEBUG_TGSI, NULL },
54 { "pipe", DEBUG_PIPE, NULL },
55 { "state", DEBUG_STATE, NULL },
56 { "screen", DEBUG_SCREEN, NULL },
57 { "tex", DEBUG_TEX, NULL },
58 { "swtnl", DEBUG_SWTNL, NULL },
59 { "const", DEBUG_CONSTS, NULL },
60 { "viewport", DEBUG_VIEWPORT, NULL },
61 { "views", DEBUG_VIEWS, NULL },
62 { "perf", DEBUG_PERF, NULL },
63 { "flush", DEBUG_FLUSH, NULL },
64 { "sync", DEBUG_SYNC, NULL },
65 { "cache", DEBUG_CACHE, NULL },
66 { "streamout", DEBUG_STREAMOUT, NULL },
67 { "query", DEBUG_QUERY, NULL },
68 DEBUG_NAMED_VALUE_END
69 };
70 #endif
71
72 static const char *
svga_get_vendor(struct pipe_screen * pscreen)73 svga_get_vendor( struct pipe_screen *pscreen )
74 {
75 return "VMware, Inc.";
76 }
77
78
79 static const char *
svga_get_name(struct pipe_screen * pscreen)80 svga_get_name( struct pipe_screen *pscreen )
81 {
82 const char *build = "", *llvm = "", *mutex = "";
83 static char name[100];
84 #ifdef DEBUG
85 /* Only return internal details in the DEBUG version:
86 */
87 build = "build: DEBUG;";
88 mutex = "mutex: " PIPE_ATOMIC ";";
89 #elif defined(VMX86_STATS)
90 build = "build: OPT;";
91 #else
92 build = "build: RELEASE;";
93 #endif
94 #ifdef HAVE_LLVM
95 llvm = "LLVM;";
96 #endif
97
98 util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
99 return name;
100 }
101
102
103 /** Helper for querying float-valued device cap */
104 static float
get_float_cap(struct svga_winsys_screen * sws,unsigned cap,float defaultVal)105 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
106 {
107 SVGA3dDevCapResult result;
108 if (sws->get_cap(sws, cap, &result))
109 return result.f;
110 else
111 return defaultVal;
112 }
113
114
115 /** Helper for querying uint-valued device cap */
116 static unsigned
get_uint_cap(struct svga_winsys_screen * sws,unsigned cap,unsigned defaultVal)117 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
118 {
119 SVGA3dDevCapResult result;
120 if (sws->get_cap(sws, cap, &result))
121 return result.u;
122 else
123 return defaultVal;
124 }
125
126
127 /** Helper for querying boolean-valued device cap */
128 static boolean
get_bool_cap(struct svga_winsys_screen * sws,unsigned cap,boolean defaultVal)129 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
130 {
131 SVGA3dDevCapResult result;
132 if (sws->get_cap(sws, cap, &result))
133 return result.b;
134 else
135 return defaultVal;
136 }
137
138
139 static float
svga_get_paramf(struct pipe_screen * screen,enum pipe_capf param)140 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
141 {
142 struct svga_screen *svgascreen = svga_screen(screen);
143 struct svga_winsys_screen *sws = svgascreen->sws;
144
145 switch (param) {
146 case PIPE_CAPF_MAX_LINE_WIDTH:
147 return svgascreen->maxLineWidth;
148 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
149 return svgascreen->maxLineWidthAA;
150
151 case PIPE_CAPF_MAX_POINT_WIDTH:
152 /* fall-through */
153 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
154 return svgascreen->maxPointSize;
155
156 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
157 return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
158
159 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
160 return 15.0;
161
162 case PIPE_CAPF_GUARD_BAND_LEFT:
163 case PIPE_CAPF_GUARD_BAND_TOP:
164 case PIPE_CAPF_GUARD_BAND_RIGHT:
165 case PIPE_CAPF_GUARD_BAND_BOTTOM:
166 return 0.0;
167 }
168
169 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
170 return 0;
171 }
172
173
174 static int
svga_get_param(struct pipe_screen * screen,enum pipe_cap param)175 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
176 {
177 struct svga_screen *svgascreen = svga_screen(screen);
178 struct svga_winsys_screen *sws = svgascreen->sws;
179 SVGA3dDevCapResult result;
180
181 switch (param) {
182 case PIPE_CAP_NPOT_TEXTURES:
183 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
184 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
185 return 1;
186 case PIPE_CAP_TWO_SIDED_STENCIL:
187 return 1;
188 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
189 /*
190 * "In virtually every OpenGL implementation and hardware,
191 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
192 * http://www.opengl.org/wiki/Blending
193 */
194 return sws->have_vgpu10 ? 1 : 0;
195 case PIPE_CAP_ANISOTROPIC_FILTER:
196 return 1;
197 case PIPE_CAP_POINT_SPRITE:
198 return 1;
199 case PIPE_CAP_TGSI_TEXCOORD:
200 return 0;
201 case PIPE_CAP_MAX_RENDER_TARGETS:
202 return svgascreen->max_color_buffers;
203 case PIPE_CAP_OCCLUSION_QUERY:
204 return 1;
205 case PIPE_CAP_QUERY_TIME_ELAPSED:
206 return 0;
207 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
208 return sws->have_vgpu10;
209 case PIPE_CAP_TEXTURE_SHADOW_MAP:
210 return 1;
211 case PIPE_CAP_TEXTURE_SWIZZLE:
212 return 1;
213 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
214 return 0;
215 case PIPE_CAP_USER_VERTEX_BUFFERS:
216 case PIPE_CAP_USER_INDEX_BUFFERS:
217 return 0;
218 case PIPE_CAP_USER_CONSTANT_BUFFERS:
219 return 1;
220 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
221 return 256;
222
223 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
224 {
225 unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
226 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
227 levels = MIN2(util_logbase2(result.u) + 1, levels);
228 else
229 levels = 12 /* 2048x2048 */;
230 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
231 levels = MIN2(util_logbase2(result.u) + 1, levels);
232 else
233 levels = 12 /* 2048x2048 */;
234 return levels;
235 }
236
237 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
238 if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
239 return 8; /* max 128x128x128 */
240 return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
241
242 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
243 /*
244 * No mechanism to query the host, and at least limited to 2048x2048 on
245 * certain hardware.
246 */
247 return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
248 12 /* 2048x2048 */);
249
250 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
251 return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
252
253 case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
254 return 1;
255
256 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
257 return 1;
258 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
259 return sws->have_vgpu10;
260 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
261 return 0;
262 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
263 return !sws->have_vgpu10;
264
265 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
266 return 1; /* The color outputs of vertex shaders are not clamped */
267 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
268 return 0; /* The driver can't clamp vertex colors */
269 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
270 return 0; /* The driver can't clamp fragment colors */
271
272 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
273 return 1; /* expected for GL_ARB_framebuffer_object */
274
275 case PIPE_CAP_GLSL_FEATURE_LEVEL:
276 return sws->have_vgpu10 ? 330 : 120;
277
278 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
279 return 0;
280
281 case PIPE_CAP_SM3:
282 return 1;
283
284 case PIPE_CAP_DEPTH_CLIP_DISABLE:
285 case PIPE_CAP_INDEP_BLEND_ENABLE:
286 case PIPE_CAP_CONDITIONAL_RENDER:
287 case PIPE_CAP_QUERY_TIMESTAMP:
288 case PIPE_CAP_TGSI_INSTANCEID:
289 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
290 case PIPE_CAP_SEAMLESS_CUBE_MAP:
291 case PIPE_CAP_FAKE_SW_MSAA:
292 return sws->have_vgpu10;
293
294 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
295 return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
296 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
297 return sws->have_vgpu10 ? 4 : 0;
298 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
299 return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
300 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
301 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
302 return 0;
303 case PIPE_CAP_TEXTURE_MULTISAMPLE:
304 return svgascreen->ms_samples ? 1 : 0;
305
306 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
307 return SVGA3D_DX_MAX_RESOURCE_SIZE;
308
309 case PIPE_CAP_MIN_TEXEL_OFFSET:
310 return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
311 case PIPE_CAP_MAX_TEXEL_OFFSET:
312 return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
313
314 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
315 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
316 return 0;
317
318 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
319 return sws->have_vgpu10 ? 256 : 0;
320 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
321 return sws->have_vgpu10 ? 1024 : 0;
322
323 case PIPE_CAP_PRIMITIVE_RESTART:
324 return 1; /* may be a sw fallback, depending on restart index */
325
326 case PIPE_CAP_GENERATE_MIPMAP:
327 return sws->have_generate_mipmap_cmd;
328
329 /* Unsupported features */
330 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
331 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
332 case PIPE_CAP_SHADER_STENCIL_EXPORT:
333 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
334 case PIPE_CAP_INDEP_BLEND_FUNC:
335 case PIPE_CAP_TEXTURE_BARRIER:
336 case PIPE_CAP_MAX_VERTEX_STREAMS:
337 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
338 case PIPE_CAP_COMPUTE:
339 case PIPE_CAP_START_INSTANCE:
340 case PIPE_CAP_CUBE_MAP_ARRAY:
341 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
342 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
343 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
344 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
345 case PIPE_CAP_TEXTURE_GATHER_SM5:
346 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
347 case PIPE_CAP_TEXTURE_QUERY_LOD:
348 case PIPE_CAP_SAMPLE_SHADING:
349 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
350 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
351 case PIPE_CAP_DRAW_INDIRECT:
352 case PIPE_CAP_MULTI_DRAW_INDIRECT:
353 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
354 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
355 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
356 case PIPE_CAP_SAMPLER_VIEW_TARGET:
357 case PIPE_CAP_CLIP_HALFZ:
358 case PIPE_CAP_VERTEXID_NOBASE:
359 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
360 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
361 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
362 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
363 case PIPE_CAP_INVALIDATE_BUFFER:
364 case PIPE_CAP_STRING_MARKER:
365 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
366 case PIPE_CAP_QUERY_MEMORY_INFO:
367 case PIPE_CAP_PCI_GROUP:
368 case PIPE_CAP_PCI_BUS:
369 case PIPE_CAP_PCI_DEVICE:
370 case PIPE_CAP_PCI_FUNCTION:
371 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
372 case PIPE_CAP_NATIVE_FENCE_FD:
373 return 0;
374 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
375 return 64;
376 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
377 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
378 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
379 return 1; /* need 4-byte alignment for all offsets and strides */
380 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
381 return 2048;
382 case PIPE_CAP_MAX_VIEWPORTS:
383 return 1;
384 case PIPE_CAP_ENDIANNESS:
385 return PIPE_ENDIAN_LITTLE;
386
387 case PIPE_CAP_VENDOR_ID:
388 return 0x15ad; /* VMware Inc. */
389 case PIPE_CAP_DEVICE_ID:
390 return 0x0405; /* assume SVGA II */
391 case PIPE_CAP_ACCELERATED:
392 return 0; /* XXX: */
393 case PIPE_CAP_VIDEO_MEMORY:
394 /* XXX: Query the host ? */
395 return 1;
396 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
397 return sws->have_vgpu10;
398 case PIPE_CAP_CLEAR_TEXTURE:
399 return sws->have_vgpu10;
400 case PIPE_CAP_UMA:
401 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
402 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
403 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
404 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
405 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
406 case PIPE_CAP_DEPTH_BOUNDS_TEST:
407 case PIPE_CAP_TGSI_TXQS:
408 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
409 case PIPE_CAP_SHAREABLE_SHADERS:
410 case PIPE_CAP_DRAW_PARAMETERS:
411 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
412 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
413 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
414 case PIPE_CAP_QUERY_BUFFER_OBJECT:
415 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
416 case PIPE_CAP_CULL_DISTANCE:
417 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
418 case PIPE_CAP_TGSI_VOTE:
419 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
420 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
421 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
422 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
423 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
424 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
425 case PIPE_CAP_TGSI_FS_FBFETCH:
426 return 0;
427 }
428
429 debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
430 return 0;
431 }
432
433
434 static int
vgpu9_get_shader_param(struct pipe_screen * screen,unsigned shader,enum pipe_shader_cap param)435 vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
436 enum pipe_shader_cap param)
437 {
438 struct svga_screen *svgascreen = svga_screen(screen);
439 struct svga_winsys_screen *sws = svgascreen->sws;
440 unsigned val;
441
442 assert(!sws->have_vgpu10);
443
444 switch (shader)
445 {
446 case PIPE_SHADER_FRAGMENT:
447 switch (param)
448 {
449 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
450 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
451 return get_uint_cap(sws,
452 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
453 512);
454 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
455 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
456 return 512;
457 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
458 return SVGA3D_MAX_NESTING_LEVEL;
459 case PIPE_SHADER_CAP_MAX_INPUTS:
460 return 10;
461 case PIPE_SHADER_CAP_MAX_OUTPUTS:
462 return svgascreen->max_color_buffers;
463 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
464 return 224 * sizeof(float[4]);
465 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
466 return 1;
467 case PIPE_SHADER_CAP_MAX_TEMPS:
468 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
469 return MIN2(val, SVGA3D_TEMPREG_MAX);
470 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
471 /*
472 * Although PS 3.0 has some addressing abilities it can only represent
473 * loops that can be statically determined and unrolled. Given we can
474 * only handle a subset of the cases that the state tracker already
475 * does it is better to defer loop unrolling to the state tracker.
476 */
477 return 0;
478 case PIPE_SHADER_CAP_MAX_PREDS:
479 return 1;
480 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
481 return 0;
482 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
483 return 0;
484 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
485 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
486 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
487 return 0;
488 case PIPE_SHADER_CAP_SUBROUTINES:
489 return 0;
490 case PIPE_SHADER_CAP_INTEGERS:
491 return 0;
492 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
493 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
494 return 16;
495 case PIPE_SHADER_CAP_PREFERRED_IR:
496 return PIPE_SHADER_IR_TGSI;
497 case PIPE_SHADER_CAP_SUPPORTED_IRS:
498 return 0;
499 case PIPE_SHADER_CAP_DOUBLES:
500 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
501 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
502 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
503 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
504 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
505 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
506 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
507 return 0;
508 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
509 return 32;
510 }
511 /* If we get here, we failed to handle a cap above */
512 debug_printf("Unexpected fragment shader query %u\n", param);
513 return 0;
514 case PIPE_SHADER_VERTEX:
515 switch (param)
516 {
517 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
518 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
519 return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
520 512);
521 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
522 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
523 /* XXX: until we have vertex texture support */
524 return 0;
525 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
526 return SVGA3D_MAX_NESTING_LEVEL;
527 case PIPE_SHADER_CAP_MAX_INPUTS:
528 return 16;
529 case PIPE_SHADER_CAP_MAX_OUTPUTS:
530 return 10;
531 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
532 return 256 * sizeof(float[4]);
533 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
534 return 1;
535 case PIPE_SHADER_CAP_MAX_TEMPS:
536 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
537 return MIN2(val, SVGA3D_TEMPREG_MAX);
538 case PIPE_SHADER_CAP_MAX_PREDS:
539 return 1;
540 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
541 return 0;
542 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
543 return 0;
544 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
545 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
546 return 1;
547 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
548 return 0;
549 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
550 return 1;
551 case PIPE_SHADER_CAP_SUBROUTINES:
552 return 0;
553 case PIPE_SHADER_CAP_INTEGERS:
554 return 0;
555 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
556 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
557 return 0;
558 case PIPE_SHADER_CAP_PREFERRED_IR:
559 return PIPE_SHADER_IR_TGSI;
560 case PIPE_SHADER_CAP_SUPPORTED_IRS:
561 return 0;
562 case PIPE_SHADER_CAP_DOUBLES:
563 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
564 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
565 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
566 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
567 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
568 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
569 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
570 return 0;
571 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
572 return 32;
573 }
574 /* If we get here, we failed to handle a cap above */
575 debug_printf("Unexpected vertex shader query %u\n", param);
576 return 0;
577 case PIPE_SHADER_GEOMETRY:
578 case PIPE_SHADER_COMPUTE:
579 case PIPE_SHADER_TESS_CTRL:
580 case PIPE_SHADER_TESS_EVAL:
581 /* no support for geometry, tess or compute shaders at this time */
582 return 0;
583 default:
584 debug_printf("Unexpected shader type (%u) query\n", shader);
585 return 0;
586 }
587 return 0;
588 }
589
590
591 static int
vgpu10_get_shader_param(struct pipe_screen * screen,unsigned shader,enum pipe_shader_cap param)592 vgpu10_get_shader_param(struct pipe_screen *screen, unsigned shader,
593 enum pipe_shader_cap param)
594 {
595 struct svga_screen *svgascreen = svga_screen(screen);
596 struct svga_winsys_screen *sws = svgascreen->sws;
597
598 assert(sws->have_vgpu10);
599 (void) sws; /* silence unused var warnings in non-debug builds */
600
601 /* Only VS, GS, FS supported */
602 if (shader != PIPE_SHADER_VERTEX &&
603 shader != PIPE_SHADER_GEOMETRY &&
604 shader != PIPE_SHADER_FRAGMENT) {
605 return 0;
606 }
607
608 /* NOTE: we do not query the device for any caps/limits at this time */
609
610 /* Generally the same limits for vertex, geometry and fragment shaders */
611 switch (param) {
612 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
613 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
614 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
615 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
616 return 64 * 1024;
617 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
618 return 64;
619 case PIPE_SHADER_CAP_MAX_INPUTS:
620 if (shader == PIPE_SHADER_FRAGMENT)
621 return VGPU10_MAX_FS_INPUTS;
622 else if (shader == PIPE_SHADER_GEOMETRY)
623 return VGPU10_MAX_GS_INPUTS;
624 else
625 return VGPU10_MAX_VS_INPUTS;
626 case PIPE_SHADER_CAP_MAX_OUTPUTS:
627 if (shader == PIPE_SHADER_FRAGMENT)
628 return VGPU10_MAX_FS_OUTPUTS;
629 else if (shader == PIPE_SHADER_GEOMETRY)
630 return VGPU10_MAX_GS_OUTPUTS;
631 else
632 return VGPU10_MAX_VS_OUTPUTS;
633 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
634 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
635 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
636 return svgascreen->max_const_buffers;
637 case PIPE_SHADER_CAP_MAX_TEMPS:
638 return VGPU10_MAX_TEMPS;
639 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
640 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
641 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
642 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
643 return TRUE; /* XXX verify */
644 case PIPE_SHADER_CAP_MAX_PREDS:
645 return 0;
646 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
647 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
648 case PIPE_SHADER_CAP_SUBROUTINES:
649 case PIPE_SHADER_CAP_INTEGERS:
650 return TRUE;
651 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
652 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
653 return SVGA3D_DX_MAX_SAMPLERS;
654 case PIPE_SHADER_CAP_PREFERRED_IR:
655 return PIPE_SHADER_IR_TGSI;
656 case PIPE_SHADER_CAP_SUPPORTED_IRS:
657 return 0;
658 case PIPE_SHADER_CAP_DOUBLES:
659 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
660 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
661 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
662 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
663 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
664 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
665 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
666 return 0;
667 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
668 return 32;
669 default:
670 debug_printf("Unexpected vgpu10 shader query %u\n", param);
671 return 0;
672 }
673 return 0;
674 }
675
676
677 static int
svga_get_shader_param(struct pipe_screen * screen,unsigned shader,enum pipe_shader_cap param)678 svga_get_shader_param(struct pipe_screen *screen, unsigned shader,
679 enum pipe_shader_cap param)
680 {
681 struct svga_screen *svgascreen = svga_screen(screen);
682 struct svga_winsys_screen *sws = svgascreen->sws;
683 if (sws->have_vgpu10) {
684 return vgpu10_get_shader_param(screen, shader, param);
685 }
686 else {
687 return vgpu9_get_shader_param(screen, shader, param);
688 }
689 }
690
691
692 /**
693 * Implement pipe_screen::is_format_supported().
694 * \param bindings bitmask of PIPE_BIND_x flags
695 */
696 static boolean
svga_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned bindings)697 svga_is_format_supported( struct pipe_screen *screen,
698 enum pipe_format format,
699 enum pipe_texture_target target,
700 unsigned sample_count,
701 unsigned bindings)
702 {
703 struct svga_screen *ss = svga_screen(screen);
704 SVGA3dSurfaceFormat svga_format;
705 SVGA3dSurfaceFormatCaps caps;
706 SVGA3dSurfaceFormatCaps mask;
707
708 assert(bindings);
709
710 if (sample_count > 1) {
711 /* In ms_samples, if bit N is set it means that we support
712 * multisample with N+1 samples per pixel.
713 */
714 if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
715 return FALSE;
716 }
717 }
718
719 svga_format = svga_translate_format(ss, format, bindings);
720 if (svga_format == SVGA3D_FORMAT_INVALID) {
721 return FALSE;
722 }
723
724 /* we don't support sRGB rendering into display targets */
725 if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
726 return FALSE;
727 }
728
729 /*
730 * For VGPU10 vertex formats, skip querying host capabilities
731 */
732
733 if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
734 SVGA3dSurfaceFormat svga_format;
735 unsigned flags;
736 svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
737 return svga_format != SVGA3D_FORMAT_INVALID;
738 }
739
740 /*
741 * Override host capabilities, so that we end up with the same
742 * visuals for all virtual hardware implementations.
743 */
744
745 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
746 switch (svga_format) {
747 case SVGA3D_A8R8G8B8:
748 case SVGA3D_X8R8G8B8:
749 case SVGA3D_R5G6B5:
750 break;
751
752 /* VGPU10 formats */
753 case SVGA3D_B8G8R8A8_UNORM:
754 case SVGA3D_B8G8R8X8_UNORM:
755 case SVGA3D_B5G6R5_UNORM:
756 break;
757
758 /* Often unsupported/problematic. This means we end up with the same
759 * visuals for all virtual hardware implementations.
760 */
761 case SVGA3D_A4R4G4B4:
762 case SVGA3D_A1R5G5B5:
763 return FALSE;
764
765 default:
766 return FALSE;
767 }
768 }
769
770 /*
771 * Query the host capabilities.
772 */
773
774 svga_get_format_cap(ss, svga_format, &caps);
775
776 if (bindings & PIPE_BIND_RENDER_TARGET) {
777 /* Check that the color surface is blendable, unless it's an
778 * integer format.
779 */
780 if (!svga_format_is_integer(svga_format) &&
781 (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
782 return FALSE;
783 }
784 }
785
786 mask.value = 0;
787 if (bindings & PIPE_BIND_RENDER_TARGET) {
788 mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
789 }
790 if (bindings & PIPE_BIND_DEPTH_STENCIL) {
791 mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
792 }
793 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
794 mask.value |= SVGA3DFORMAT_OP_TEXTURE;
795 }
796
797 if (target == PIPE_TEXTURE_CUBE) {
798 mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
799 }
800 else if (target == PIPE_TEXTURE_3D) {
801 mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
802 }
803
804 return (caps.value & mask.value) == mask.value;
805 }
806
807
808 static void
svga_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)809 svga_fence_reference(struct pipe_screen *screen,
810 struct pipe_fence_handle **ptr,
811 struct pipe_fence_handle *fence)
812 {
813 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
814 sws->fence_reference(sws, ptr, fence);
815 }
816
817
818 static boolean
svga_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)819 svga_fence_finish(struct pipe_screen *screen,
820 struct pipe_context *ctx,
821 struct pipe_fence_handle *fence,
822 uint64_t timeout)
823 {
824 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
825 boolean retVal;
826
827 SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
828
829 if (!timeout) {
830 retVal = sws->fence_signalled(sws, fence, 0) == 0;
831 }
832 else {
833 SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
834 __FUNCTION__, fence);
835
836 retVal = sws->fence_finish(sws, fence, 0) == 0;
837 }
838
839 SVGA_STATS_TIME_POP(sws);
840
841 return retVal;
842 }
843
844
845 static int
svga_get_driver_query_info(struct pipe_screen * screen,unsigned index,struct pipe_driver_query_info * info)846 svga_get_driver_query_info(struct pipe_screen *screen,
847 unsigned index,
848 struct pipe_driver_query_info *info)
849 {
850 #define QUERY(NAME, ENUM, UNITS) \
851 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
852
853 static const struct pipe_driver_query_info queries[] = {
854 /* per-frame counters */
855 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
856 PIPE_DRIVER_QUERY_TYPE_UINT64),
857 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
858 PIPE_DRIVER_QUERY_TYPE_UINT64),
859 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
860 PIPE_DRIVER_QUERY_TYPE_UINT64),
861 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
862 PIPE_DRIVER_QUERY_TYPE_UINT64),
863 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
864 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
865 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
866 PIPE_DRIVER_QUERY_TYPE_UINT64),
867 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
868 PIPE_DRIVER_QUERY_TYPE_UINT64),
869 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
870 PIPE_DRIVER_QUERY_TYPE_BYTES),
871 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
872 PIPE_DRIVER_QUERY_TYPE_BYTES),
873 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
874 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
875 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
876 PIPE_DRIVER_QUERY_TYPE_UINT64),
877 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
878 PIPE_DRIVER_QUERY_TYPE_UINT64),
879 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
880 PIPE_DRIVER_QUERY_TYPE_UINT64),
881 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
882 PIPE_DRIVER_QUERY_TYPE_UINT64),
883 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
884 PIPE_DRIVER_QUERY_TYPE_UINT64),
885 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
886 PIPE_DRIVER_QUERY_TYPE_UINT64),
887
888 /* running total counters */
889 QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
890 PIPE_DRIVER_QUERY_TYPE_BYTES),
891 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
892 PIPE_DRIVER_QUERY_TYPE_UINT64),
893 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
894 PIPE_DRIVER_QUERY_TYPE_UINT64),
895 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
896 PIPE_DRIVER_QUERY_TYPE_UINT64),
897 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
898 PIPE_DRIVER_QUERY_TYPE_UINT64),
899 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
900 PIPE_DRIVER_QUERY_TYPE_UINT64),
901 };
902 #undef QUERY
903
904 if (!info)
905 return ARRAY_SIZE(queries);
906
907 if (index >= ARRAY_SIZE(queries))
908 return 0;
909
910 *info = queries[index];
911 return 1;
912 }
913
914
915 static void
svga_destroy_screen(struct pipe_screen * screen)916 svga_destroy_screen( struct pipe_screen *screen )
917 {
918 struct svga_screen *svgascreen = svga_screen(screen);
919
920 svga_screen_cache_cleanup(svgascreen);
921
922 pipe_mutex_destroy(svgascreen->swc_mutex);
923 pipe_mutex_destroy(svgascreen->tex_mutex);
924
925 svgascreen->sws->destroy(svgascreen->sws);
926
927 FREE(svgascreen);
928 }
929
930
931 /**
932 * Create a new svga_screen object
933 */
934 struct pipe_screen *
svga_screen_create(struct svga_winsys_screen * sws)935 svga_screen_create(struct svga_winsys_screen *sws)
936 {
937 struct svga_screen *svgascreen;
938 struct pipe_screen *screen;
939
940 #ifdef DEBUG
941 SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
942 #endif
943
944 svgascreen = CALLOC_STRUCT(svga_screen);
945 if (!svgascreen)
946 goto error1;
947
948 svgascreen->debug.force_level_surface_view =
949 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
950 svgascreen->debug.force_surface_view =
951 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
952 svgascreen->debug.force_sampler_view =
953 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
954 svgascreen->debug.no_surface_view =
955 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
956 svgascreen->debug.no_sampler_view =
957 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
958 svgascreen->debug.no_cache_index_buffers =
959 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
960
961 screen = &svgascreen->screen;
962
963 screen->destroy = svga_destroy_screen;
964 screen->get_name = svga_get_name;
965 screen->get_vendor = svga_get_vendor;
966 screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
967 screen->get_param = svga_get_param;
968 screen->get_shader_param = svga_get_shader_param;
969 screen->get_paramf = svga_get_paramf;
970 screen->get_timestamp = NULL;
971 screen->is_format_supported = svga_is_format_supported;
972 screen->context_create = svga_context_create;
973 screen->fence_reference = svga_fence_reference;
974 screen->fence_finish = svga_fence_finish;
975 screen->get_driver_query_info = svga_get_driver_query_info;
976 svgascreen->sws = sws;
977
978 svga_init_screen_resource_functions(svgascreen);
979
980 if (sws->get_hw_version) {
981 svgascreen->hw_version = sws->get_hw_version(sws);
982 } else {
983 svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
984 }
985
986 /*
987 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
988 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
989 * we prefer the later when available.
990 *
991 * This mimics hardware vendors extensions for D3D depth sampling. See also
992 * http://aras-p.info/texts/D3D9GPUHacks.html
993 */
994
995 {
996 boolean has_df16, has_df24, has_d24s8_int;
997 SVGA3dSurfaceFormatCaps caps;
998 SVGA3dSurfaceFormatCaps mask;
999 mask.value = 0;
1000 mask.zStencil = 1;
1001 mask.texture = 1;
1002
1003 svgascreen->depth.z16 = SVGA3D_Z_D16;
1004 svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1005 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1006
1007 svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1008 has_df16 = (caps.value & mask.value) == mask.value;
1009
1010 svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1011 has_df24 = (caps.value & mask.value) == mask.value;
1012
1013 svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1014 has_d24s8_int = (caps.value & mask.value) == mask.value;
1015
1016 /* XXX: We might want some other logic here.
1017 * Like if we only have d24s8_int we should
1018 * emulate the other formats with that.
1019 */
1020 if (has_df16) {
1021 svgascreen->depth.z16 = SVGA3D_Z_DF16;
1022 }
1023 if (has_df24) {
1024 svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1025 }
1026 if (has_d24s8_int) {
1027 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1028 }
1029 }
1030
1031 /* Query device caps
1032 */
1033 if (sws->have_vgpu10) {
1034 svgascreen->haveProvokingVertex
1035 = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1036 svgascreen->haveLineSmooth = TRUE;
1037 svgascreen->maxPointSize = 80.0F;
1038 svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1039
1040 /* Multisample samples per pixel */
1041 if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1042 svgascreen->ms_samples =
1043 get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1044 }
1045
1046 /* Maximum number of constant buffers */
1047 svgascreen->max_const_buffers =
1048 get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1049 assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1050 }
1051 else {
1052 /* VGPU9 */
1053 unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1054 SVGA3DVSVERSION_NONE);
1055 unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1056 SVGA3DPSVERSION_NONE);
1057
1058 /* we require Shader model 3.0 or later */
1059 if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1060 goto error2;
1061 }
1062
1063 svgascreen->haveProvokingVertex = FALSE;
1064
1065 svgascreen->haveLineSmooth =
1066 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1067
1068 svgascreen->maxPointSize =
1069 get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1070 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1071 svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1072
1073 /* The SVGA3D device always supports 4 targets at this time, regardless
1074 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1075 */
1076 svgascreen->max_color_buffers = 4;
1077
1078 /* Only support one constant buffer
1079 */
1080 svgascreen->max_const_buffers = 1;
1081
1082 /* No multisampling */
1083 svgascreen->ms_samples = 0;
1084 }
1085
1086 /* common VGPU9 / VGPU10 caps */
1087 svgascreen->haveLineStipple =
1088 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1089
1090 svgascreen->maxLineWidth =
1091 get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1092
1093 svgascreen->maxLineWidthAA =
1094 get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1095
1096 if (0) {
1097 debug_printf("svga: haveProvokingVertex %u\n",
1098 svgascreen->haveProvokingVertex);
1099 debug_printf("svga: haveLineStip %u "
1100 "haveLineSmooth %u maxLineWidth %f\n",
1101 svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1102 svgascreen->maxLineWidth);
1103 debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1104 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1105 }
1106
1107 pipe_mutex_init(svgascreen->tex_mutex);
1108 pipe_mutex_init(svgascreen->swc_mutex);
1109
1110 svga_screen_cache_init(svgascreen);
1111
1112 return screen;
1113 error2:
1114 FREE(svgascreen);
1115 error1:
1116 return NULL;
1117 }
1118
1119 struct svga_winsys_screen *
svga_winsys_screen(struct pipe_screen * screen)1120 svga_winsys_screen(struct pipe_screen *screen)
1121 {
1122 return svga_screen(screen)->sws;
1123 }
1124
1125 #ifdef DEBUG
1126 struct svga_screen *
svga_screen(struct pipe_screen * screen)1127 svga_screen(struct pipe_screen *screen)
1128 {
1129 assert(screen);
1130 assert(screen->destroy == svga_destroy_screen);
1131 return (struct svga_screen *)screen;
1132 }
1133 #endif
1134