| /external/llvm/test/ObjectYAML/MachO/ |
| D | lazy_bind_opcode.yaml | 66 Imm: 2
70 Imm: 1
72 Imm: 0
75 Imm: 0
77 Imm: 0
79 Imm: 2
83 Imm: 1
85 Imm: 0
88 Imm: 0
90 Imm: 0
[all …]
|
| D | bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | weak_bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | out_of_order_linkedit.yaml | 144 Imm: 1
146 Imm: 2
150 Imm: 0
154 Imm: 0
157 Imm: 1
160 Imm: 0
163 Imm: 1
166 Imm: 2
171 Imm: 0
174 Imm: 0
[all …]
|
| /external/valgrind/none/tests/mips64/ |
| D | shift_instructions.stdout.exp-mips64 | 1 dsll $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
2 dsll $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
3 dsll $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
4 dsll $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
5 dsll $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
6 dsll $t2, $t3, 0x1f :: rt 0x95eb5500000000, rs 0x12bd6aa, imm 0x001f
7 dsll $a0, $a1, 0x0f :: rt 0x95eb550000, rs 0x12bd6aa, imm 0x000f
8 dsll $s0, $s1, 0x03 :: rt 0x95eb550, rs 0x12bd6aa, imm 0x0003
9 dsll $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
10 dsll $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
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| D | shift_instructions.stdout.exp-mips64r2 | 1 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
2 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
3 drotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
4 drotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
5 drotr $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
6 drotr $t2, $t3, 0x1f :: rt 0x257ad5400000000, rs 0x12bd6aa, imm 0x001f
7 drotr $a0, $a1, 0x0f :: rt 0xad54000000000257, rs 0x12bd6aa, imm 0x000f
8 drotr $s0, $s1, 0x03 :: rt 0x4000000000257ad5, rs 0x12bd6aa, imm 0x0003
9 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
10 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
|
| D | logical_instructions.stdout.exp | 513 andi $t0, $t1, 0xff :: rt 0x0, rs 0x0, imm 0x00ff
514 andi $t2, $t3, 0xffff :: rt 0x0, rs 0x0, imm 0xffff
515 andi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000
516 andi $s0, $s1, 0x23 :: rt 0x0, rs 0x0, imm 0x0023
517 andi $t0, $t1, 0xff :: rt 0xaa, rs 0x12bd6aa, imm 0x00ff
518 andi $t2, $t3, 0xffff :: rt 0xd6aa, rs 0x12bd6aa, imm 0xffff
519 andi $a0, $a1, 0x0 :: rt 0x0, rs 0x12bd6aa, imm 0x0000
520 andi $s0, $s1, 0x23 :: rt 0x22, rs 0x12bd6aa, imm 0x0023
521 andi $t0, $t1, 0xff :: rt 0x0, rs 0x0, imm 0x00ff
522 andi $t2, $t3, 0xffff :: rt 0x0, rs 0x0, imm 0xffff
[all …]
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| D | arithmetic_instruction.stdout.exp-mips64 | 257 addi $t0, $t1, 0xff :: rt 0xff, rs 0x0, imm 0x00ff
258 addi $t2, $t3, 0xffff :: rt 0xffffffffffffffff, rs 0x0, imm 0xffff
259 addi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000
260 addi $s0, $s1, 0x23 :: rt 0x23, rs 0x0, imm 0x0023
261 addi $t0, $t1, 0xff :: rt 0xff, rs 0x0, imm 0x00ff
262 addi $t2, $t3, 0xffff :: rt 0xffffffffffffffff, rs 0x0, imm 0xffff
263 addi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000
264 addi $s0, $s1, 0x23 :: rt 0x23, rs 0x0, imm 0x0023
265 addi $t0, $t1, 0xff :: rt 0x9823c6d, rs 0x9823b6e, imm 0x00ff
266 addi $t2, $t3, 0xffff :: rt 0x9823b6d, rs 0x9823b6e, imm 0xffff
[all …]
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| D | arithmetic_instruction.stdout.exp-mips64r2 | 257 addi $t0, $t1, 0xff :: rt 0xff, rs 0x0, imm 0x00ff
258 addi $t2, $t3, 0xffff :: rt 0xffffffffffffffff, rs 0x0, imm 0xffff
259 addi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000
260 addi $s0, $s1, 0x23 :: rt 0x23, rs 0x0, imm 0x0023
261 addi $t0, $t1, 0xff :: rt 0xff, rs 0x0, imm 0x00ff
262 addi $t2, $t3, 0xffff :: rt 0xffffffffffffffff, rs 0x0, imm 0xffff
263 addi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000
264 addi $s0, $s1, 0x23 :: rt 0x23, rs 0x0, imm 0x0023
265 addi $t0, $t1, 0xff :: rt 0x9823c6d, rs 0x9823b6e, imm 0x00ff
266 addi $t2, $t3, 0xffff :: rt 0x9823b6d, rs 0x9823b6e, imm 0xffff
[all …]
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_fs_combine_constants.cpp | 101 struct imm { struct
142 struct imm *imm; argument
147 static struct imm *
151 if (table->imm[i].val == val) { in find_imm()
152 return &table->imm[i]; in find_imm()
158 static struct imm *
163 table->imm = reralloc(mem_ctx, table->imm, struct imm, table->size); in new_imm()
165 return &table->imm[table->len++]; in new_imm()
169 * Comparator used for sorting an array of imm structures.
179 const struct imm *a = (const struct imm *)_a, in compare()
[all …]
|
| /external/clang/lib/Headers/ |
| D | avx512bwintrin.h | 1632 #define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \ argument
1636 4 + (((imm) >> 0) & 0x3), \
1637 4 + (((imm) >> 2) & 0x3), \
1638 4 + (((imm) >> 4) & 0x3), \
1639 4 + (((imm) >> 6) & 0x3), \
1641 12 + (((imm) >> 0) & 0x3), \
1642 12 + (((imm) >> 2) & 0x3), \
1643 12 + (((imm) >> 4) & 0x3), \
1644 12 + (((imm) >> 6) & 0x3), \
1646 20 + (((imm) >> 0) & 0x3), \
[all …]
|
| D | avx2intrin.h | 498 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \ argument
501 0 + (((imm) >> 0) & 0x3), \
502 0 + (((imm) >> 2) & 0x3), \
503 0 + (((imm) >> 4) & 0x3), \
504 0 + (((imm) >> 6) & 0x3), \
505 4 + (((imm) >> 0) & 0x3), \
506 4 + (((imm) >> 2) & 0x3), \
507 4 + (((imm) >> 4) & 0x3), \
508 4 + (((imm) >> 6) & 0x3)); })
510 #define _mm256_shufflehi_epi16(a, imm) __extension__ ({ \ argument
[all …]
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_64.c | 44 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in load_immediate() argument
51 if (imm <= SIMM_MAX && imm >= SIMM_MIN) in load_immediate()
52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
54 if (!(imm & ~0xffff)) in load_immediate()
55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
57 if (imm <= 0x7fffffffl && imm >= -0x80000000l) { in load_immediate()
58 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
63 tmp = (imm >= 0) ? imm : ~imm; in load_immediate()
67 tmp = (imm << shift); in load_immediate()
[all …]
|
| D | sljitNativePPC_32.c | 29 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in load_immediate() argument
31 if (imm <= SIMM_MAX && imm >= SIMM_MIN) in load_immediate()
32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
34 if (!(imm & ~0xffff)) in load_immediate()
35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
37 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
101 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); in emit_single_op()
106 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); in emit_single_op()
110 return push_inst(compiler, ADDIC | D(dst) | A(src1) | compiler->imm); in emit_single_op()
[all …]
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrMemory.td | 83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
84 (LOAD_I32 imm:$off, $addr, 0)>;
85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
86 (LOAD_I64 imm:$off, $addr, 0)>;
87 def : Pat<(f32 (load (regPlusImm I32:$addr, imm:$off))),
88 (LOAD_F32 imm:$off, $addr, 0)>;
89 def : Pat<(f64 (load (regPlusImm I32:$addr, imm:$off))),
90 (LOAD_F64 imm:$off, $addr, 0)>;
91 def : Pat<(i32 (load (or_is_add I32:$addr, imm:$off))),
92 (LOAD_I32 imm:$off, $addr, 0)>;
[all …]
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| /external/mesa3d/src/gallium/auxiliary/postprocess/ |
| D | pp_mlaa.h | 55 "IMM FLT32 { 0.0030, 0.0000, 1.0000, 0.0000}\n"
67 " 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx\n"
68 " 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz\n"
69 " 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy\n"
86 "IMM FLT32 { 0.2126, 0.7152, 0.0722, 0.1000}\n"
87 "IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000}\n"
89 " 1: DP3 TEMP[0].x, TEMP[1].xyzz, IMM[0]\n"
91 " 3: DP3 TEMP[0].y, TEMP[1].xyzz, IMM[0].xyzz\n"
93 " 5: DP3 TEMP[0].z, TEMP[1].xyzz, IMM[0].xyzz\n"
95 " 7: DP3 TEMP[0].w, TEMP[1].xyzz, IMM[0].xyzz\n"
[all …]
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 66 // b<cond> $imm
67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68 (BCOND brtarget:$imm, condVal)>;
70 // b<cond>,a $imm
71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72 (BCONDA brtarget:$imm, condVal)>;
74 // b<cond> %icc, $imm
75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 // b<cond>,pt %icc, $imm
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIIntrinsics.td | 26 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
29 llvm_i32_ty, // inst_offset(imm)
30 llvm_i32_ty, // dfmt(imm)
31 llvm_i32_ty, // nfmt(imm)
32 llvm_i32_ty, // offen(imm)
33 llvm_i32_ty, // idxen(imm)
34 llvm_i32_ty, // glc(imm)
35 llvm_i32_ty, // slc(imm)
36 llvm_i32_ty], // tfe(imm)
45 llvm_i32_ty, // inst_offset(imm)
[all …]
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| /external/llvm/test/MC/Lanai/ |
| D | memory.s | 12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
28 ! CHECK-NEXT: <MCOperand Imm:0>
29 ! CHECK-NEXT: <MCOperand Imm:0>
36 ! CHECK-NEXT: <MCOperand Imm:291>
37 ! CHECK-NEXT: <MCOperand Imm:128>
44 ! CHECK-NEXT: <MCOperand Imm:-4>
45 ! CHECK-NEXT: <MCOperand Imm:128>
[all …]
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZTargetTransformInfo.cpp | 34 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument
46 if (Imm == 0) in getIntImmCost()
49 if (Imm.getBitWidth() <= 64) { in getIntImmCost()
51 if (isInt<32>(Imm.getSExtValue())) in getIntImmCost()
54 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
57 if ((Imm.getZExtValue() & 0xffffffff) == 0) in getIntImmCost()
67 const APInt &Imm, Type *Ty) { in getIntImmCost() argument
90 if (Idx == 0 && Imm.getBitWidth() <= 64) { in getIntImmCost()
95 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
100 if (Idx == 1 && Imm.getBitWidth() <= 64) { in getIntImmCost()
[all …]
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| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 154 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument
155 if (!isUInt<N>(Imm)) in decodeUImmOperand()
157 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
162 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument
163 if (!isUInt<N>(Imm)) in decodeSImmOperand()
165 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
169 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, in decodeAccessRegOperand() argument
172 return decodeUImmOperand<4>(Inst, Imm); in decodeAccessRegOperand()
175 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU1ImmOperand() argument
177 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonOperands.td | 124 def s32ImmPred : PatLeaf<(i32 imm), [{
129 def s32_0ImmPred : PatLeaf<(i32 imm), [{
134 def s31_1ImmPred : PatLeaf<(i32 imm), [{
139 def s30_2ImmPred : PatLeaf<(i32 imm), [{
144 def s29_3ImmPred : PatLeaf<(i32 imm), [{
149 def s16ImmPred : PatLeaf<(i32 imm), [{
154 def s11_0ImmPred : PatLeaf<(i32 imm), [{
159 def s11_1ImmPred : PatLeaf<(i32 imm), [{
164 def s11_2ImmPred : PatLeaf<(i32 imm), [{
169 def s11_3ImmPred : PatLeaf<(i32 imm), [{
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu()
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi()
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument
43 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL()
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument
[all …]
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 606 ImmediateT32::ImmediateT32(uint32_t imm) { in ImmediateT32() argument
608 if ((imm & ~0xff) == 0) { in ImmediateT32()
609 SetEncodingValue(imm); in ImmediateT32()
612 if ((imm >> 16) == (imm & 0xffff)) { in ImmediateT32()
613 if ((imm & 0xff00) == 0) { in ImmediateT32()
615 SetEncodingValue((imm & 0xff) | (0x1 << 8)); in ImmediateT32()
618 if ((imm & 0xff) == 0) { in ImmediateT32()
620 SetEncodingValue(((imm >> 8) & 0xff) | (0x2 << 8)); in ImmediateT32()
623 if (((imm >> 8) & 0xff) == (imm & 0xff)) { in ImmediateT32()
625 SetEncodingValue((imm & 0xff) | (0x3 << 8)); in ImmediateT32()
[all …]
|