1#!/usr/bin/env python2.7 2 3# Copyright 2015, VIXL authors 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are met: 8# 9# * Redistributions of source code must retain the above copyright notice, 10# this list of conditions and the following disclaimer. 11# * Redistributions in binary form must reproduce the above copyright notice, 12# this list of conditions and the following disclaimer in the documentation 13# and/or other materials provided with the distribution. 14# * Neither the name of ARM Limited nor the names of its contributors may be 15# used to endorse or promote products derived from this software without 16# specific prior written permission. 17# 18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 19# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 22# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 29import os 30import sys 31import argparse 32import re 33import util 34 35copyright_header = """// Copyright 2015, VIXL authors 36// All rights reserved. 37// 38// Redistribution and use in source and binary forms, with or without 39// modification, are permitted provided that the following conditions are met: 40// 41// * Redistributions of source code must retain the above copyright notice, 42// this list of conditions and the following disclaimer. 43// * Redistributions in binary form must reproduce the above copyright notice, 44// this list of conditions and the following disclaimer in the documentation 45// and/or other materials provided with the distribution. 46// * Neither the name of ARM Limited nor the names of its contributors may be 47// used to endorse or promote products derived from this software without 48// specific prior written permission. 49// 50// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 51// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 52// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 53// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 54// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 55// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 56// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 57// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 58// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 59// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 61""" 62 63master_trace_header = """ 64// This file holds the expected results for the instructions tested by 65// test-simulator-aarch64. 66// 67// If you update input lists in test-simulator-inputs-aarch64.h, or add a new 68// test to test-simulator-aarch64.cc, please run 69// tools/generate_simulator_traces.py on a reference platform to regenerate 70// this file and trace files. 71// 72 73#ifndef VIXL_TEST_AARCH64_SIMULATOR_TRACES_AARCH64_H_ 74#define VIXL_TEST_AARCH64_SIMULATOR_TRACES_AARCH64_H_ 75 76extern "C" { 77#include <stdint.h> 78} 79 80// To add a new simulator test to test-simulator-aarch64.cc, add dummy array(s) 81// below to build test-simulator-aarch64 for reference platform. Then, run 82// tools/generate_simulator_traces.py on a reference platform to regenerate this 83// file and traces files. 84 85// --------------------------------------------------------------------- 86// ADD DUMMY ARRAYS FOR NEW SIMULATOR TEST HERE. 87// --------------------------------------------------------------------- 88const uint64_t kExpected_dummy_64[] = { 0 }; 89const size_t kExpectedCount_dummy_64 = 0; 90 91const uint32_t kExpected_dummy_32[] = { 0 }; 92const size_t kExpectedCount_dummy_32 = 0; 93 94// --------------------------------------------------------------------- 95// Simulator test trace output files. 96// --------------------------------------------------------------------- 97""" 98master_trace_footer = """ 99#endif // VIXL_TEST_AARCH64_SIMULATOR_TRACES_AARCH64_H_ 100""" 101 102trace_header = """ 103// --------------------------------------------------------------------- 104// This file is auto generated using tools/generate_simulator_traces.py. 105// 106// PLEASE DO NOT EDIT. 107// --------------------------------------------------------------------- 108""" 109 110def BuildOptions(root): 111 result = argparse.ArgumentParser(description = 'Simulator test generator.') 112 result.add_argument('--runner', action='store', 113 default=os.path.join(root, 'obj/latest/test/test-runner'), 114 help='The test executable to run.') 115 result.add_argument('--aarch32-only', action='store_true') 116 result.add_argument('--aarch64-only', action='store_true') 117 result.add_argument('--out', action='store', 118 default='test/aarch64/test-simulator-traces-aarch64.h') 119 return result.parse_args() 120 121def ShouldGenerateAArch32(args): 122 return (not args.aarch32_only and not args.aarch64_only) or args.aarch32_only 123 124def ShouldGenerateAArch64(args): 125 return (not args.aarch32_only and not args.aarch64_only) or args.aarch64_only 126 127if __name__ == '__main__': 128 # $ROOT/tools/generate_simulator_traces.py 129 root_dir = os.path.dirname(os.path.dirname(os.path.abspath(sys.argv[0]))) 130 os.chdir(root_dir) 131 132 args = BuildOptions(root_dir) 133 134 # List all tests. 135 status, test_list = util.getstatusoutput(args.runner + ' --list') 136 if status != 0: util.abort('Failed to list all tests') 137 138 if ShouldGenerateAArch64(args): 139 # Run each simulator test (AARCH64_SIM_*) with the --generate_test_trace 140 # option, and use the output to create the traces header (from --out). In 141 # addition, the test-simulator-traces-aarch64.h file, the master trace file, 142 # which includes all other trace files is generated. 143 144 # Create master trace file. 145 master_trace_f = open(args.out, 'w') 146 master_trace_f.write(copyright_header) 147 master_trace_f.write(master_trace_header) 148 master_trace_f.write('\n\n') 149 150 # Find the AArch64 simulator tests. 151 tests = sorted(filter(lambda t: 'AARCH64_SIM_' in t, test_list.split())) 152 153 for test in tests: 154 # Run each test. 155 print 'Generating trace for ' + test; 156 # Strip out 'AARCH64_' to get the name of the test. 157 test_name = test[len('AARCH64_'):] 158 cmd = ' '.join([args.runner, '--generate_test_trace', test]) 159 status, output = util.getstatusoutput(cmd) 160 if status != 0: util.abort('Failed to run ' + cmd + '.') 161 162 # Create a new trace header file. 163 trace_filename = test_name.lower().replace('_', '-') + "-trace-aarch64.h" 164 trace_f = open("test/aarch64/traces/" + trace_filename, 'w') 165 trace_f.write(copyright_header) 166 trace_f.write(trace_header) 167 trace_f.write('\n') 168 trace_f.write("#ifndef VIXL_" + test_name.upper() + "_TRACE_AARCH64_H_\n") 169 trace_f.write("#define VIXL_" + test_name.upper() + "_TRACE_AARCH64_H_\n") 170 trace_f.write('\n') 171 trace_f.write(output) 172 trace_f.write('\n') 173 trace_f.write('\n' + "#endif // VIXL_" 174 + test_name.upper() + "_TRACE_AARCH64_H_" + '\n') 175 trace_f.close() 176 177 # Update master trace file. 178 master_trace_f.write( 179 '#include \"aarch64/traces/' + trace_filename + '\"\n') 180 181 # Close master trace file. 182 master_trace_f.write(master_trace_footer) 183 master_trace_f.close() 184 185 if ShouldGenerateAArch32(args): 186 # Run each test (AARCH32_{SIMULATOR,ASSEMBLER}_*) with the 187 # --generate_test_trace option. 188 189 # Find the AArch32 tests. 190 tests = sorted(filter( 191 lambda t: 'AARCH32_SIMULATOR_' in t or 'AARCH32_ASSEMBLER_' in t, 192 test_list.split())) 193 194 for test in tests: 195 # Run each test. 196 print 'Generating trace for ' + test; 197 # Strip out 'AARCH32_' to get the name of the test. 198 test_name = test[len('AARCH32_'):] 199 200 # An "and" instruction will be called "and_" since we cannot clash with 201 # the C++ operator. Rename "and_" to "and" to keep sane filenames. 202 test_name = test_name.replace('and_', 'and') 203 204 cmd = ' '.join([args.runner, '--generate_test_trace', test]) 205 status, output = util.getstatusoutput(cmd) 206 if status != 0: util.abort('Failed to run ' + cmd + '.') 207 208 # Create a new trace header file. 209 trace_filename = test_name.lower().replace('_', '-') + ".h" 210 trace_f = open("test/aarch32/traces/" + trace_filename, 'w') 211 trace_f.write(copyright_header) 212 trace_f.write(trace_header) 213 trace_f.write('\n') 214 trace_f.write("#ifndef VIXL_" + test_name.upper() + "_H_\n") 215 trace_f.write("#define VIXL_" + test_name.upper() + "_H_\n") 216 trace_f.write('\n') 217 trace_f.write(output) 218 trace_f.write('\n') 219 trace_f.write( 220 '\n' + "#endif // VIXL_" + test_name.upper() + "_H_" + '\n') 221 trace_f.close() 222 223 print 'Trace generation COMPLETE' 224