1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 // This peephole pass optimizes in the following cases.
9 // 1. Optimizes redundant sign extends for the following case
10 // Transform the following pattern
11 // %vreg170<def> = SXTW %vreg166
12 // ...
13 // %vreg176<def> = COPY %vreg170:subreg_loreg
14 //
15 // Into
16 // %vreg176<def> = COPY vreg166
17 //
18 // 2. Optimizes redundant negation of predicates.
19 // %vreg15<def> = CMPGTrr %vreg6, %vreg2
20 // ...
21 // %vreg16<def> = NOT_p %vreg15<kill>
22 // ...
23 // JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
24 //
25 // Into
26 // %vreg15<def> = CMPGTrr %vreg6, %vreg2;
27 // ...
28 // JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
29 //
30 // Note: The peephole pass makes the instrucstions like
31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
32 // redundant and relies on some form of dead removal instructions, like
33 // DCE or DIE to actually eliminate them.
34
35
36 //===----------------------------------------------------------------------===//
37
38 #include "Hexagon.h"
39 #include "HexagonTargetMachine.h"
40 #include "llvm/ADT/DenseMap.h"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/MachineFunction.h"
43 #include "llvm/CodeGen/MachineFunctionPass.h"
44 #include "llvm/CodeGen/MachineInstrBuilder.h"
45 #include "llvm/CodeGen/MachineRegisterInfo.h"
46 #include "llvm/CodeGen/Passes.h"
47 #include "llvm/IR/Constants.h"
48 #include "llvm/PassSupport.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
55 #include <algorithm>
56
57 using namespace llvm;
58
59 #define DEBUG_TYPE "hexagon-peephole"
60
61 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
62 cl::Hidden, cl::ZeroOrMore, cl::init(false),
63 cl::desc("Disable Peephole Optimization"));
64
65 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
66 cl::Hidden, cl::ZeroOrMore, cl::init(false),
67 cl::desc("Disable Optimization of PNotP"));
68
69 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
70 cl::Hidden, cl::ZeroOrMore, cl::init(true),
71 cl::desc("Disable Optimization of Sign/Zero Extends"));
72
73 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
74 cl::Hidden, cl::ZeroOrMore, cl::init(true),
75 cl::desc("Disable Optimization of extensions to i64."));
76
77 namespace llvm {
78 FunctionPass *createHexagonPeephole();
79 void initializeHexagonPeepholePass(PassRegistry&);
80 }
81
82 namespace {
83 struct HexagonPeephole : public MachineFunctionPass {
84 const HexagonInstrInfo *QII;
85 const HexagonRegisterInfo *QRI;
86 const MachineRegisterInfo *MRI;
87
88 public:
89 static char ID;
HexagonPeephole__anon5185b8dc0111::HexagonPeephole90 HexagonPeephole() : MachineFunctionPass(ID) {
91 initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
92 }
93
94 bool runOnMachineFunction(MachineFunction &MF) override;
95
getPassName__anon5185b8dc0111::HexagonPeephole96 const char *getPassName() const override {
97 return "Hexagon optimize redundant zero and size extends";
98 }
99
getAnalysisUsage__anon5185b8dc0111::HexagonPeephole100 void getAnalysisUsage(AnalysisUsage &AU) const override {
101 MachineFunctionPass::getAnalysisUsage(AU);
102 }
103
104 private:
105 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
106 };
107 }
108
109 char HexagonPeephole::ID = 0;
110
111 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
112 false, false)
113
runOnMachineFunction(MachineFunction & MF)114 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
115 if (skipFunction(*MF.getFunction()))
116 return false;
117
118 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
119 QRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
120 MRI = &MF.getRegInfo();
121
122 DenseMap<unsigned, unsigned> PeepholeMap;
123 DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap;
124
125 if (DisableHexagonPeephole) return false;
126
127 // Loop over all of the basic blocks.
128 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
129 MBBb != MBBe; ++MBBb) {
130 MachineBasicBlock *MBB = &*MBBb;
131 PeepholeMap.clear();
132 PeepholeDoubleRegsMap.clear();
133
134 // Traverse the basic block.
135 for (MachineInstr &MI : *MBB) {
136 // Look for sign extends:
137 // %vreg170<def> = SXTW %vreg166
138 if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
139 assert(MI.getNumOperands() == 2);
140 MachineOperand &Dst = MI.getOperand(0);
141 MachineOperand &Src = MI.getOperand(1);
142 unsigned DstReg = Dst.getReg();
143 unsigned SrcReg = Src.getReg();
144 // Just handle virtual registers.
145 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
146 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
147 // Map the following:
148 // %vreg170<def> = SXTW %vreg166
149 // PeepholeMap[170] = vreg166
150 PeepholeMap[DstReg] = SrcReg;
151 }
152 }
153
154 // Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
155 // %vreg170:DoublRegs, %vreg169:IntRegs
156 if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) {
157 assert(MI.getNumOperands() == 3);
158 MachineOperand &Dst = MI.getOperand(0);
159 MachineOperand &Src1 = MI.getOperand(1);
160 MachineOperand &Src2 = MI.getOperand(2);
161 if (Src1.getImm() != 0)
162 continue;
163 unsigned DstReg = Dst.getReg();
164 unsigned SrcReg = Src2.getReg();
165 PeepholeMap[DstReg] = SrcReg;
166 }
167
168 // Look for this sequence below
169 // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
170 // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
171 // and convert into
172 // %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
173 if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {
174 assert(MI.getNumOperands() == 3);
175 MachineOperand &Dst = MI.getOperand(0);
176 MachineOperand &Src1 = MI.getOperand(1);
177 MachineOperand &Src2 = MI.getOperand(2);
178 if (Src2.getImm() != 32)
179 continue;
180 unsigned DstReg = Dst.getReg();
181 unsigned SrcReg = Src1.getReg();
182 PeepholeDoubleRegsMap[DstReg] =
183 std::make_pair(*&SrcReg, Hexagon::subreg_hireg);
184 }
185
186 // Look for P=NOT(P).
187 if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) {
188 assert(MI.getNumOperands() == 2);
189 MachineOperand &Dst = MI.getOperand(0);
190 MachineOperand &Src = MI.getOperand(1);
191 unsigned DstReg = Dst.getReg();
192 unsigned SrcReg = Src.getReg();
193 // Just handle virtual registers.
194 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
195 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
196 // Map the following:
197 // %vreg170<def> = NOT_xx %vreg166
198 // PeepholeMap[170] = vreg166
199 PeepholeMap[DstReg] = SrcReg;
200 }
201 }
202
203 // Look for copy:
204 // %vreg176<def> = COPY %vreg170:subreg_loreg
205 if (!DisableOptSZExt && MI.isCopy()) {
206 assert(MI.getNumOperands() == 2);
207 MachineOperand &Dst = MI.getOperand(0);
208 MachineOperand &Src = MI.getOperand(1);
209
210 // Make sure we are copying the lower 32 bits.
211 if (Src.getSubReg() != Hexagon::subreg_loreg)
212 continue;
213
214 unsigned DstReg = Dst.getReg();
215 unsigned SrcReg = Src.getReg();
216 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
217 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
218 // Try to find in the map.
219 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
220 // Change the 1st operand.
221 MI.RemoveOperand(1);
222 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
223 } else {
224 DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
225 PeepholeDoubleRegsMap.find(SrcReg);
226 if (DI != PeepholeDoubleRegsMap.end()) {
227 std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
228 MI.RemoveOperand(1);
229 MI.addOperand(MachineOperand::CreateReg(
230 PeepholeSrc.first, false /*isDef*/, false /*isImp*/,
231 false /*isKill*/, false /*isDead*/, false /*isUndef*/,
232 false /*isEarlyClobber*/, PeepholeSrc.second));
233 }
234 }
235 }
236 }
237
238 // Look for Predicated instructions.
239 if (!DisablePNotP) {
240 bool Done = false;
241 if (QII->isPredicated(MI)) {
242 MachineOperand &Op0 = MI.getOperand(0);
243 unsigned Reg0 = Op0.getReg();
244 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
245 if (RC0->getID() == Hexagon::PredRegsRegClassID) {
246 // Handle instructions that have a prediate register in op0
247 // (most cases of predicable instructions).
248 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
249 // Try to find in the map.
250 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
251 // Change the 1st operand and, flip the opcode.
252 MI.getOperand(0).setReg(PeepholeSrc);
253 int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());
254 MI.setDesc(QII->get(NewOp));
255 Done = true;
256 }
257 }
258 }
259 }
260
261 if (!Done) {
262 // Handle special instructions.
263 unsigned Op = MI.getOpcode();
264 unsigned NewOp = 0;
265 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
266
267 switch (Op) {
268 case Hexagon::C2_mux:
269 case Hexagon::C2_muxii:
270 NewOp = Op;
271 break;
272 case Hexagon::C2_muxri:
273 NewOp = Hexagon::C2_muxir;
274 break;
275 case Hexagon::C2_muxir:
276 NewOp = Hexagon::C2_muxri;
277 break;
278 }
279 if (NewOp) {
280 unsigned PSrc = MI.getOperand(PR).getReg();
281 if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
282 MI.getOperand(PR).setReg(POrig);
283 MI.setDesc(QII->get(NewOp));
284 // Swap operands S1 and S2.
285 MachineOperand Op1 = MI.getOperand(S1);
286 MachineOperand Op2 = MI.getOperand(S2);
287 ChangeOpInto(MI.getOperand(S1), Op2);
288 ChangeOpInto(MI.getOperand(S2), Op1);
289 }
290 } // if (NewOp)
291 } // if (!Done)
292
293 } // if (!DisablePNotP)
294
295 } // Instruction
296 } // Basic Block
297 return true;
298 }
299
ChangeOpInto(MachineOperand & Dst,MachineOperand & Src)300 void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
301 assert (&Dst != &Src && "Cannot duplicate into itself");
302 switch (Dst.getType()) {
303 case MachineOperand::MO_Register:
304 if (Src.isReg()) {
305 Dst.setReg(Src.getReg());
306 Dst.setSubReg(Src.getSubReg());
307 } else if (Src.isImm()) {
308 Dst.ChangeToImmediate(Src.getImm());
309 } else {
310 llvm_unreachable("Unexpected src operand type");
311 }
312 break;
313
314 case MachineOperand::MO_Immediate:
315 if (Src.isImm()) {
316 Dst.setImm(Src.getImm());
317 } else if (Src.isReg()) {
318 Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
319 Src.isKill(), Src.isDead(), Src.isUndef(),
320 Src.isDebug());
321 Dst.setSubReg(Src.getSubReg());
322 } else {
323 llvm_unreachable("Unexpected src operand type");
324 }
325 break;
326
327 default:
328 llvm_unreachable("Unexpected dst operand type");
329 break;
330 }
331 }
332
createHexagonPeephole()333 FunctionPass *llvm::createHexagonPeephole() {
334 return new HexagonPeephole();
335 }
336