1 //===--- HexagonSplitDouble.cpp -------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #define DEBUG_TYPE "hsdr"
11
12 #include "HexagonRegisterInfo.h"
13 #include "HexagonTargetMachine.h"
14
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineLoopInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Pass.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25
26 #include <map>
27 #include <set>
28 #include <vector>
29
30 using namespace llvm;
31
32 namespace llvm {
33 FunctionPass *createHexagonSplitDoubleRegs();
34 void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
35 }
36
37 namespace {
38 static cl::opt<int> MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1),
39 cl::desc("Maximum number of split partitions"));
40 static cl::opt<bool> MemRefsFixed("hsdr-no-mem", cl::Hidden, cl::init(true),
41 cl::desc("Do not split loads or stores"));
42
43 class HexagonSplitDoubleRegs : public MachineFunctionPass {
44 public:
45 static char ID;
HexagonSplitDoubleRegs()46 HexagonSplitDoubleRegs() : MachineFunctionPass(ID), TRI(nullptr),
47 TII(nullptr) {
48 initializeHexagonSplitDoubleRegsPass(*PassRegistry::getPassRegistry());
49 }
getPassName() const50 const char *getPassName() const override {
51 return "Hexagon Split Double Registers";
52 }
getAnalysisUsage(AnalysisUsage & AU) const53 void getAnalysisUsage(AnalysisUsage &AU) const override {
54 AU.addRequired<MachineLoopInfo>();
55 AU.addPreserved<MachineLoopInfo>();
56 MachineFunctionPass::getAnalysisUsage(AU);
57 }
58 bool runOnMachineFunction(MachineFunction &MF) override;
59
60 private:
61 static const TargetRegisterClass *const DoubleRC;
62
63 const HexagonRegisterInfo *TRI;
64 const HexagonInstrInfo *TII;
65 const MachineLoopInfo *MLI;
66 MachineRegisterInfo *MRI;
67
68 typedef std::set<unsigned> USet;
69 typedef std::map<unsigned,USet> UUSetMap;
70 typedef std::pair<unsigned,unsigned> UUPair;
71 typedef std::map<unsigned,UUPair> UUPairMap;
72 typedef std::map<const MachineLoop*,USet> LoopRegMap;
73
74 bool isInduction(unsigned Reg, LoopRegMap &IRM) const;
75 bool isVolatileInstr(const MachineInstr *MI) const;
76 bool isFixedInstr(const MachineInstr *MI) const;
77 void partitionRegisters(UUSetMap &P2Rs);
78 int32_t profit(const MachineInstr *MI) const;
79 bool isProfitable(const USet &Part, LoopRegMap &IRM) const;
80
81 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
82 void collectIndRegs(LoopRegMap &IRM);
83
84 void createHalfInstr(unsigned Opc, MachineInstr *MI,
85 const UUPairMap &PairMap, unsigned SubR);
86 void splitMemRef(MachineInstr *MI, const UUPairMap &PairMap);
87 void splitImmediate(MachineInstr *MI, const UUPairMap &PairMap);
88 void splitCombine(MachineInstr *MI, const UUPairMap &PairMap);
89 void splitExt(MachineInstr *MI, const UUPairMap &PairMap);
90 void splitShift(MachineInstr *MI, const UUPairMap &PairMap);
91 void splitAslOr(MachineInstr *MI, const UUPairMap &PairMap);
92 bool splitInstr(MachineInstr *MI, const UUPairMap &PairMap);
93 void replaceSubregUses(MachineInstr *MI, const UUPairMap &PairMap);
94 void collapseRegPairs(MachineInstr *MI, const UUPairMap &PairMap);
95 bool splitPartition(const USet &Part);
96
97 static int Counter;
98 static void dump_partition(raw_ostream&, const USet&,
99 const TargetRegisterInfo&);
100 };
101 char HexagonSplitDoubleRegs::ID;
102 int HexagonSplitDoubleRegs::Counter = 0;
103 const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC
104 = &Hexagon::DoubleRegsRegClass;
105 }
106
107 INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",
108 "Hexagon Split Double Registers", false, false)
109
110
dump_partition(raw_ostream & os,const USet & Part,const TargetRegisterInfo & TRI)111 void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,
112 const USet &Part, const TargetRegisterInfo &TRI) {
113 dbgs() << '{';
114 for (auto I : Part)
115 dbgs() << ' ' << PrintReg(I, &TRI);
116 dbgs() << " }";
117 }
118
119
isInduction(unsigned Reg,LoopRegMap & IRM) const120 bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const {
121 for (auto I : IRM) {
122 const USet &Rs = I.second;
123 if (Rs.find(Reg) != Rs.end())
124 return true;
125 }
126 return false;
127 }
128
129
isVolatileInstr(const MachineInstr * MI) const130 bool HexagonSplitDoubleRegs::isVolatileInstr(const MachineInstr *MI) const {
131 for (auto &I : MI->memoperands())
132 if (I->isVolatile())
133 return true;
134 return false;
135 }
136
137
isFixedInstr(const MachineInstr * MI) const138 bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
139 if (MI->mayLoad() || MI->mayStore())
140 if (MemRefsFixed || isVolatileInstr(MI))
141 return true;
142 if (MI->isDebugValue())
143 return false;
144
145 unsigned Opc = MI->getOpcode();
146 switch (Opc) {
147 default:
148 return true;
149
150 case TargetOpcode::PHI:
151 case TargetOpcode::COPY:
152 break;
153
154 case Hexagon::L2_loadrd_io:
155 // Not handling stack stores (only reg-based addresses).
156 if (MI->getOperand(1).isReg())
157 break;
158 return true;
159 case Hexagon::S2_storerd_io:
160 // Not handling stack stores (only reg-based addresses).
161 if (MI->getOperand(0).isReg())
162 break;
163 return true;
164 case Hexagon::L2_loadrd_pi:
165 case Hexagon::S2_storerd_pi:
166
167 case Hexagon::A2_tfrpi:
168 case Hexagon::A2_combineii:
169 case Hexagon::A4_combineir:
170 case Hexagon::A4_combineii:
171 case Hexagon::A4_combineri:
172 case Hexagon::A2_combinew:
173 case Hexagon::CONST64_Int_Real:
174
175 case Hexagon::A2_sxtw:
176
177 case Hexagon::A2_andp:
178 case Hexagon::A2_orp:
179 case Hexagon::A2_xorp:
180 case Hexagon::S2_asl_i_p_or:
181 case Hexagon::S2_asl_i_p:
182 case Hexagon::S2_asr_i_p:
183 case Hexagon::S2_lsr_i_p:
184 break;
185 }
186
187 for (auto &Op : MI->operands()) {
188 if (!Op.isReg())
189 continue;
190 unsigned R = Op.getReg();
191 if (!TargetRegisterInfo::isVirtualRegister(R))
192 return true;
193 }
194 return false;
195 }
196
197
partitionRegisters(UUSetMap & P2Rs)198 void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
199 typedef std::map<unsigned,unsigned> UUMap;
200 typedef std::vector<unsigned> UVect;
201
202 unsigned NumRegs = MRI->getNumVirtRegs();
203 BitVector DoubleRegs(NumRegs);
204 for (unsigned i = 0; i < NumRegs; ++i) {
205 unsigned R = TargetRegisterInfo::index2VirtReg(i);
206 if (MRI->getRegClass(R) == DoubleRC)
207 DoubleRegs.set(i);
208 }
209
210 BitVector FixedRegs(NumRegs);
211 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
212 unsigned R = TargetRegisterInfo::index2VirtReg(x);
213 MachineInstr *DefI = MRI->getVRegDef(R);
214 // In some cases a register may exist, but never be defined or used.
215 // It should never appear anywhere, but mark it as "fixed", just to be
216 // safe.
217 if (!DefI || isFixedInstr(DefI))
218 FixedRegs.set(x);
219 }
220
221 UUSetMap AssocMap;
222 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
223 if (FixedRegs[x])
224 continue;
225 unsigned R = TargetRegisterInfo::index2VirtReg(x);
226 DEBUG(dbgs() << PrintReg(R, TRI) << " ~~");
227 USet &Asc = AssocMap[R];
228 for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end();
229 U != Z; ++U) {
230 MachineOperand &Op = *U;
231 MachineInstr *UseI = Op.getParent();
232 if (isFixedInstr(UseI))
233 continue;
234 for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) {
235 MachineOperand &MO = UseI->getOperand(i);
236 // Skip non-registers or registers with subregisters.
237 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
238 continue;
239 unsigned T = MO.getReg();
240 if (!TargetRegisterInfo::isVirtualRegister(T)) {
241 FixedRegs.set(x);
242 continue;
243 }
244 if (MRI->getRegClass(T) != DoubleRC)
245 continue;
246 unsigned u = TargetRegisterInfo::virtReg2Index(T);
247 if (FixedRegs[u])
248 continue;
249 DEBUG(dbgs() << ' ' << PrintReg(T, TRI));
250 Asc.insert(T);
251 // Make it symmetric.
252 AssocMap[T].insert(R);
253 }
254 }
255 DEBUG(dbgs() << '\n');
256 }
257
258 UUMap R2P;
259 unsigned NextP = 1;
260 USet Visited;
261 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
262 unsigned R = TargetRegisterInfo::index2VirtReg(x);
263 if (Visited.count(R))
264 continue;
265 // Create a new partition for R.
266 unsigned ThisP = FixedRegs[x] ? 0 : NextP++;
267 UVect WorkQ;
268 WorkQ.push_back(R);
269 for (unsigned i = 0; i < WorkQ.size(); ++i) {
270 unsigned T = WorkQ[i];
271 if (Visited.count(T))
272 continue;
273 R2P[T] = ThisP;
274 Visited.insert(T);
275 // Add all registers associated with T.
276 USet &Asc = AssocMap[T];
277 for (USet::iterator J = Asc.begin(), F = Asc.end(); J != F; ++J)
278 WorkQ.push_back(*J);
279 }
280 }
281
282 for (auto I : R2P)
283 P2Rs[I.second].insert(I.first);
284 }
285
286
profitImm(unsigned Lo,unsigned Hi)287 static inline int32_t profitImm(unsigned Lo, unsigned Hi) {
288 int32_t P = 0;
289 bool LoZ1 = false, HiZ1 = false;
290 if (Lo == 0 || Lo == 0xFFFFFFFF)
291 P += 10, LoZ1 = true;
292 if (Hi == 0 || Hi == 0xFFFFFFFF)
293 P += 10, HiZ1 = true;
294 if (!LoZ1 && !HiZ1 && Lo == Hi)
295 P += 3;
296 return P;
297 }
298
299
profit(const MachineInstr * MI) const300 int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
301 unsigned ImmX = 0;
302 unsigned Opc = MI->getOpcode();
303 switch (Opc) {
304 case TargetOpcode::PHI:
305 for (const auto &Op : MI->operands())
306 if (!Op.getSubReg())
307 return 0;
308 return 10;
309 case TargetOpcode::COPY:
310 if (MI->getOperand(1).getSubReg() != 0)
311 return 10;
312 return 0;
313
314 case Hexagon::L2_loadrd_io:
315 case Hexagon::S2_storerd_io:
316 return -1;
317 case Hexagon::L2_loadrd_pi:
318 case Hexagon::S2_storerd_pi:
319 return 2;
320
321 case Hexagon::A2_tfrpi:
322 case Hexagon::CONST64_Int_Real: {
323 uint64_t D = MI->getOperand(1).getImm();
324 unsigned Lo = D & 0xFFFFFFFFULL;
325 unsigned Hi = D >> 32;
326 return profitImm(Lo, Hi);
327 }
328 case Hexagon::A2_combineii:
329 case Hexagon::A4_combineii:
330 return profitImm(MI->getOperand(1).getImm(),
331 MI->getOperand(2).getImm());
332 case Hexagon::A4_combineri:
333 ImmX++;
334 case Hexagon::A4_combineir: {
335 ImmX++;
336 int64_t V = MI->getOperand(ImmX).getImm();
337 if (V == 0 || V == -1)
338 return 10;
339 // Fall through into A2_combinew.
340 }
341 case Hexagon::A2_combinew:
342 return 2;
343
344 case Hexagon::A2_sxtw:
345 return 3;
346
347 case Hexagon::A2_andp:
348 case Hexagon::A2_orp:
349 case Hexagon::A2_xorp:
350 return 1;
351
352 case Hexagon::S2_asl_i_p_or: {
353 unsigned S = MI->getOperand(3).getImm();
354 if (S == 0 || S == 32)
355 return 10;
356 return -1;
357 }
358 case Hexagon::S2_asl_i_p:
359 case Hexagon::S2_asr_i_p:
360 case Hexagon::S2_lsr_i_p:
361 unsigned S = MI->getOperand(2).getImm();
362 if (S == 0 || S == 32)
363 return 10;
364 if (S == 16)
365 return 5;
366 if (S == 48)
367 return 7;
368 return -10;
369 }
370
371 return 0;
372 }
373
374
isProfitable(const USet & Part,LoopRegMap & IRM) const375 bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM)
376 const {
377 unsigned FixedNum = 0, SplitNum = 0, LoopPhiNum = 0;
378 int32_t TotalP = 0;
379
380 for (unsigned DR : Part) {
381 MachineInstr *DefI = MRI->getVRegDef(DR);
382 int32_t P = profit(DefI);
383 if (P == INT_MIN)
384 return false;
385 TotalP += P;
386 // Reduce the profitability of splitting induction registers.
387 if (isInduction(DR, IRM))
388 TotalP -= 30;
389
390 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
391 U != W; ++U) {
392 MachineInstr *UseI = U->getParent();
393 if (isFixedInstr(UseI)) {
394 FixedNum++;
395 // Calculate the cost of generating REG_SEQUENCE instructions.
396 for (auto &Op : UseI->operands()) {
397 if (Op.isReg() && Part.count(Op.getReg()))
398 if (Op.getSubReg())
399 TotalP -= 2;
400 }
401 continue;
402 }
403 // If a register from this partition is used in a fixed instruction,
404 // and there is also a register in this partition that is used in
405 // a loop phi node, then decrease the splitting profit as this can
406 // confuse the modulo scheduler.
407 if (UseI->isPHI()) {
408 const MachineBasicBlock *PB = UseI->getParent();
409 const MachineLoop *L = MLI->getLoopFor(PB);
410 if (L && L->getHeader() == PB)
411 LoopPhiNum++;
412 }
413 // Splittable instruction.
414 SplitNum++;
415 int32_t P = profit(UseI);
416 if (P == INT_MIN)
417 return false;
418 TotalP += P;
419 }
420 }
421
422 if (FixedNum > 0 && LoopPhiNum > 0)
423 TotalP -= 20*LoopPhiNum;
424
425 DEBUG(dbgs() << "Partition profit: " << TotalP << '\n');
426 return TotalP > 0;
427 }
428
429
collectIndRegsForLoop(const MachineLoop * L,USet & Rs)430 void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
431 USet &Rs) {
432 const MachineBasicBlock *HB = L->getHeader();
433 const MachineBasicBlock *LB = L->getLoopLatch();
434 if (!HB || !LB)
435 return;
436
437 // Examine the latch branch. Expect it to be a conditional branch to
438 // the header (either "br-cond header" or "br-cond exit; br header").
439 MachineBasicBlock *TB = 0, *FB = 0;
440 MachineBasicBlock *TmpLB = const_cast<MachineBasicBlock*>(LB);
441 SmallVector<MachineOperand,2> Cond;
442 bool BadLB = TII->analyzeBranch(*TmpLB, TB, FB, Cond, false);
443 // Only analyzable conditional branches. HII::AnalyzeBranch will put
444 // the branch opcode as the first element of Cond, and the predicate
445 // operand as the second.
446 if (BadLB || Cond.size() != 2)
447 return;
448 // Only simple jump-conditional (with or without negation).
449 if (!TII->PredOpcodeHasJMP_c(Cond[0].getImm()))
450 return;
451 // Must go to the header.
452 if (TB != HB && FB != HB)
453 return;
454 assert(Cond[1].isReg() && "Unexpected Cond vector from AnalyzeBranch");
455 // Expect a predicate register.
456 unsigned PR = Cond[1].getReg();
457 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);
458
459 // Get the registers on which the loop controlling compare instruction
460 // depends.
461 unsigned CmpR1 = 0, CmpR2 = 0;
462 const MachineInstr *CmpI = MRI->getVRegDef(PR);
463 while (CmpI->getOpcode() == Hexagon::C2_not)
464 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg());
465
466 int Mask = 0, Val = 0;
467 bool OkCI = TII->analyzeCompare(*CmpI, CmpR1, CmpR2, Mask, Val);
468 if (!OkCI)
469 return;
470 // Eliminate non-double input registers.
471 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC)
472 CmpR1 = 0;
473 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC)
474 CmpR2 = 0;
475 if (!CmpR1 && !CmpR2)
476 return;
477
478 // Now examine the top of the loop: the phi nodes that could poten-
479 // tially define loop induction registers. The registers defined by
480 // such a phi node would be used in a 64-bit add, which then would
481 // be used in the loop compare instruction.
482
483 // Get the set of all double registers defined by phi nodes in the
484 // loop header.
485 typedef std::vector<unsigned> UVect;
486 UVect DP;
487 for (auto &MI : *HB) {
488 if (!MI.isPHI())
489 break;
490 const MachineOperand &MD = MI.getOperand(0);
491 unsigned R = MD.getReg();
492 if (MRI->getRegClass(R) == DoubleRC)
493 DP.push_back(R);
494 }
495 if (DP.empty())
496 return;
497
498 auto NoIndOp = [this, CmpR1, CmpR2] (unsigned R) -> bool {
499 for (auto I = MRI->use_nodbg_begin(R), E = MRI->use_nodbg_end();
500 I != E; ++I) {
501 const MachineInstr *UseI = I->getParent();
502 if (UseI->getOpcode() != Hexagon::A2_addp)
503 continue;
504 // Get the output from the add. If it is one of the inputs to the
505 // loop-controlling compare instruction, then R is likely an induc-
506 // tion register.
507 unsigned T = UseI->getOperand(0).getReg();
508 if (T == CmpR1 || T == CmpR2)
509 return false;
510 }
511 return true;
512 };
513 UVect::iterator End = std::remove_if(DP.begin(), DP.end(), NoIndOp);
514 Rs.insert(DP.begin(), End);
515 Rs.insert(CmpR1);
516 Rs.insert(CmpR2);
517
518 DEBUG({
519 dbgs() << "For loop at BB#" << HB->getNumber() << " ind regs: ";
520 dump_partition(dbgs(), Rs, *TRI);
521 dbgs() << '\n';
522 });
523 }
524
525
collectIndRegs(LoopRegMap & IRM)526 void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
527 typedef std::vector<MachineLoop*> LoopVector;
528 LoopVector WorkQ;
529
530 for (auto I : *MLI)
531 WorkQ.push_back(I);
532 for (unsigned i = 0; i < WorkQ.size(); ++i) {
533 for (auto I : *WorkQ[i])
534 WorkQ.push_back(I);
535 }
536
537 USet Rs;
538 for (unsigned i = 0, n = WorkQ.size(); i < n; ++i) {
539 MachineLoop *L = WorkQ[i];
540 Rs.clear();
541 collectIndRegsForLoop(L, Rs);
542 if (!Rs.empty())
543 IRM.insert(std::make_pair(L, Rs));
544 }
545 }
546
547
createHalfInstr(unsigned Opc,MachineInstr * MI,const UUPairMap & PairMap,unsigned SubR)548 void HexagonSplitDoubleRegs::createHalfInstr(unsigned Opc, MachineInstr *MI,
549 const UUPairMap &PairMap, unsigned SubR) {
550 MachineBasicBlock &B = *MI->getParent();
551 DebugLoc DL = MI->getDebugLoc();
552 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc));
553
554 for (auto &Op : MI->operands()) {
555 if (!Op.isReg()) {
556 NewI->addOperand(Op);
557 continue;
558 }
559 // For register operands, set the subregister.
560 unsigned R = Op.getReg();
561 unsigned SR = Op.getSubReg();
562 bool isVirtReg = TargetRegisterInfo::isVirtualRegister(R);
563 bool isKill = Op.isKill();
564 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) {
565 isKill = false;
566 UUPairMap::const_iterator F = PairMap.find(R);
567 if (F == PairMap.end()) {
568 SR = SubR;
569 } else {
570 const UUPair &P = F->second;
571 R = (SubR == Hexagon::subreg_loreg) ? P.first : P.second;
572 SR = 0;
573 }
574 }
575 auto CO = MachineOperand::CreateReg(R, Op.isDef(), Op.isImplicit(), isKill,
576 Op.isDead(), Op.isUndef(), Op.isEarlyClobber(), SR, Op.isDebug(),
577 Op.isInternalRead());
578 NewI->addOperand(CO);
579 }
580 }
581
582
splitMemRef(MachineInstr * MI,const UUPairMap & PairMap)583 void HexagonSplitDoubleRegs::splitMemRef(MachineInstr *MI,
584 const UUPairMap &PairMap) {
585 bool Load = MI->mayLoad();
586 unsigned OrigOpc = MI->getOpcode();
587 bool PostInc = (OrigOpc == Hexagon::L2_loadrd_pi ||
588 OrigOpc == Hexagon::S2_storerd_pi);
589 MachineInstr *LowI, *HighI;
590 MachineBasicBlock &B = *MI->getParent();
591 DebugLoc DL = MI->getDebugLoc();
592
593 // Index of the base-address-register operand.
594 unsigned AdrX = PostInc ? (Load ? 2 : 1)
595 : (Load ? 1 : 0);
596 MachineOperand &AdrOp = MI->getOperand(AdrX);
597 unsigned RSA = getRegState(AdrOp);
598 MachineOperand &ValOp = Load ? MI->getOperand(0)
599 : (PostInc ? MI->getOperand(3)
600 : MI->getOperand(2));
601 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg());
602 assert(F != PairMap.end());
603
604 if (Load) {
605 const UUPair &P = F->second;
606 int64_t Off = PostInc ? 0 : MI->getOperand(2).getImm();
607 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first)
608 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
609 .addImm(Off);
610 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second)
611 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
612 .addImm(Off+4);
613 } else {
614 const UUPair &P = F->second;
615 int64_t Off = PostInc ? 0 : MI->getOperand(1).getImm();
616 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
617 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
618 .addImm(Off)
619 .addReg(P.first);
620 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
621 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
622 .addImm(Off+4)
623 .addReg(P.second);
624 }
625
626 if (PostInc) {
627 // Create the increment of the address register.
628 int64_t Inc = Load ? MI->getOperand(3).getImm()
629 : MI->getOperand(2).getImm();
630 MachineOperand &UpdOp = Load ? MI->getOperand(1) : MI->getOperand(0);
631 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg());
632 unsigned NewR = MRI->createVirtualRegister(RC);
633 assert(!UpdOp.getSubReg() && "Def operand with subreg");
634 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR)
635 .addReg(AdrOp.getReg(), RSA)
636 .addImm(Inc);
637 MRI->replaceRegWith(UpdOp.getReg(), NewR);
638 // The original instruction will be deleted later.
639 }
640
641 // Generate a new pair of memory-operands.
642 MachineFunction &MF = *B.getParent();
643 for (auto &MO : MI->memoperands()) {
644 const MachinePointerInfo &Ptr = MO->getPointerInfo();
645 unsigned F = MO->getFlags();
646 int A = MO->getAlignment();
647
648 auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4/*size*/, A);
649 LowI->addMemOperand(MF, Tmp1);
650 auto *Tmp2 = MF.getMachineMemOperand(Ptr, F, 4/*size*/, std::min(A, 4));
651 HighI->addMemOperand(MF, Tmp2);
652 }
653 }
654
655
splitImmediate(MachineInstr * MI,const UUPairMap & PairMap)656 void HexagonSplitDoubleRegs::splitImmediate(MachineInstr *MI,
657 const UUPairMap &PairMap) {
658 MachineOperand &Op0 = MI->getOperand(0);
659 MachineOperand &Op1 = MI->getOperand(1);
660 assert(Op0.isReg() && Op1.isImm());
661 uint64_t V = Op1.getImm();
662
663 MachineBasicBlock &B = *MI->getParent();
664 DebugLoc DL = MI->getDebugLoc();
665 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
666 assert(F != PairMap.end());
667 const UUPair &P = F->second;
668
669 // The operand to A2_tfrsi can only have 32 significant bits. Immediate
670 // values in MachineOperand are stored as 64-bit integers, and so the
671 // value -1 may be represented either as 64-bit -1, or 4294967295. Both
672 // will have the 32 higher bits truncated in the end, but -1 will remain
673 // as -1, while the latter may appear to be a large unsigned value
674 // requiring a constant extender. The casting to int32_t will select the
675 // former representation. (The same reasoning applies to all 32-bit
676 // values.)
677 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
678 .addImm(int32_t(V & 0xFFFFFFFFULL));
679 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
680 .addImm(int32_t(V >> 32));
681 }
682
683
splitCombine(MachineInstr * MI,const UUPairMap & PairMap)684 void HexagonSplitDoubleRegs::splitCombine(MachineInstr *MI,
685 const UUPairMap &PairMap) {
686 MachineOperand &Op0 = MI->getOperand(0);
687 MachineOperand &Op1 = MI->getOperand(1);
688 MachineOperand &Op2 = MI->getOperand(2);
689 assert(Op0.isReg());
690
691 MachineBasicBlock &B = *MI->getParent();
692 DebugLoc DL = MI->getDebugLoc();
693 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
694 assert(F != PairMap.end());
695 const UUPair &P = F->second;
696
697 if (Op1.isImm()) {
698 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
699 .addImm(Op1.getImm());
700 } else if (Op1.isReg()) {
701 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second)
702 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
703 } else
704 llvm_unreachable("Unexpected operand");
705
706 if (Op2.isImm()) {
707 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
708 .addImm(Op2.getImm());
709 } else if (Op2.isReg()) {
710 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
711 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
712 } else
713 llvm_unreachable("Unexpected operand");
714 }
715
716
splitExt(MachineInstr * MI,const UUPairMap & PairMap)717 void HexagonSplitDoubleRegs::splitExt(MachineInstr *MI,
718 const UUPairMap &PairMap) {
719 MachineOperand &Op0 = MI->getOperand(0);
720 MachineOperand &Op1 = MI->getOperand(1);
721 assert(Op0.isReg() && Op1.isReg());
722
723 MachineBasicBlock &B = *MI->getParent();
724 DebugLoc DL = MI->getDebugLoc();
725 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
726 assert(F != PairMap.end());
727 const UUPair &P = F->second;
728 unsigned RS = getRegState(Op1);
729
730 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
731 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
732 BuildMI(B, MI, DL, TII->get(Hexagon::S2_asr_i_r), P.second)
733 .addReg(Op1.getReg(), RS, Op1.getSubReg())
734 .addImm(31);
735 }
736
737
splitShift(MachineInstr * MI,const UUPairMap & PairMap)738 void HexagonSplitDoubleRegs::splitShift(MachineInstr *MI,
739 const UUPairMap &PairMap) {
740 MachineOperand &Op0 = MI->getOperand(0);
741 MachineOperand &Op1 = MI->getOperand(1);
742 MachineOperand &Op2 = MI->getOperand(2);
743 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
744 int64_t Sh64 = Op2.getImm();
745 assert(Sh64 >= 0 && Sh64 < 64);
746 unsigned S = Sh64;
747
748 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
749 assert(F != PairMap.end());
750 const UUPair &P = F->second;
751 unsigned LoR = P.first;
752 unsigned HiR = P.second;
753 using namespace Hexagon;
754
755 unsigned Opc = MI->getOpcode();
756 bool Right = (Opc == S2_lsr_i_p || Opc == S2_asr_i_p);
757 bool Left = !Right;
758 bool Signed = (Opc == S2_asr_i_p);
759
760 MachineBasicBlock &B = *MI->getParent();
761 DebugLoc DL = MI->getDebugLoc();
762 unsigned RS = getRegState(Op1);
763 unsigned ShiftOpc = Left ? S2_asl_i_r
764 : (Signed ? S2_asr_i_r : S2_lsr_i_r);
765 unsigned LoSR = subreg_loreg;
766 unsigned HiSR = subreg_hireg;
767
768 if (S == 0) {
769 // No shift, subregister copy.
770 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
771 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
772 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), HiR)
773 .addReg(Op1.getReg(), RS, HiSR);
774 } else if (S < 32) {
775 const TargetRegisterClass *IntRC = &IntRegsRegClass;
776 unsigned TmpR = MRI->createVirtualRegister(IntRC);
777 // Expansion:
778 // Shift left: DR = shl R, #s
779 // LoR = shl R.lo, #s
780 // TmpR = extractu R.lo, #s, #32-s
781 // HiR = or (TmpR, asl(R.hi, #s))
782 // Shift right: DR = shr R, #s
783 // HiR = shr R.hi, #s
784 // TmpR = shr R.lo, #s
785 // LoR = insert TmpR, R.hi, #s, #32-s
786
787 // Shift left:
788 // LoR = shl R.lo, #s
789 // Shift right:
790 // TmpR = shr R.lo, #s
791
792 // Make a special case for A2_aslh and A2_asrh (they are predicable as
793 // opposed to S2_asl_i_r/S2_asr_i_r).
794 if (S == 16 && Left)
795 BuildMI(B, MI, DL, TII->get(A2_aslh), LoR)
796 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
797 else if (S == 16 && Signed)
798 BuildMI(B, MI, DL, TII->get(A2_asrh), TmpR)
799 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
800 else
801 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR))
802 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
803 .addImm(S);
804
805 if (Left) {
806 // TmpR = extractu R.lo, #s, #32-s
807 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR)
808 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
809 .addImm(S)
810 .addImm(32-S);
811 // HiR = or (TmpR, asl(R.hi, #s))
812 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
813 .addReg(TmpR)
814 .addReg(Op1.getReg(), RS, HiSR)
815 .addImm(S);
816 } else {
817 // HiR = shr R.hi, #s
818 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR)
819 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)
820 .addImm(S);
821 // LoR = insert TmpR, R.hi, #s, #32-s
822 BuildMI(B, MI, DL, TII->get(S2_insert), LoR)
823 .addReg(TmpR)
824 .addReg(Op1.getReg(), RS, HiSR)
825 .addImm(S)
826 .addImm(32-S);
827 }
828 } else if (S == 32) {
829 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), (Left ? HiR : LoR))
830 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
831 if (!Signed)
832 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
833 .addImm(0);
834 else // Must be right shift.
835 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
836 .addReg(Op1.getReg(), RS, HiSR)
837 .addImm(31);
838 } else if (S < 64) {
839 S -= 32;
840 if (S == 16 && Left)
841 BuildMI(B, MI, DL, TII->get(A2_aslh), HiR)
842 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
843 else if (S == 16 && Signed)
844 BuildMI(B, MI, DL, TII->get(A2_asrh), LoR)
845 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);
846 else
847 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR))
848 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
849 .addImm(S);
850
851 if (Signed)
852 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
853 .addReg(Op1.getReg(), RS, HiSR)
854 .addImm(31);
855 else
856 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
857 .addImm(0);
858 }
859 }
860
861
splitAslOr(MachineInstr * MI,const UUPairMap & PairMap)862 void HexagonSplitDoubleRegs::splitAslOr(MachineInstr *MI,
863 const UUPairMap &PairMap) {
864 MachineOperand &Op0 = MI->getOperand(0);
865 MachineOperand &Op1 = MI->getOperand(1);
866 MachineOperand &Op2 = MI->getOperand(2);
867 MachineOperand &Op3 = MI->getOperand(3);
868 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
869 int64_t Sh64 = Op3.getImm();
870 assert(Sh64 >= 0 && Sh64 < 64);
871 unsigned S = Sh64;
872
873 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
874 assert(F != PairMap.end());
875 const UUPair &P = F->second;
876 unsigned LoR = P.first;
877 unsigned HiR = P.second;
878 using namespace Hexagon;
879
880 MachineBasicBlock &B = *MI->getParent();
881 DebugLoc DL = MI->getDebugLoc();
882 unsigned RS1 = getRegState(Op1);
883 unsigned RS2 = getRegState(Op2);
884 const TargetRegisterClass *IntRC = &IntRegsRegClass;
885
886 unsigned LoSR = subreg_loreg;
887 unsigned HiSR = subreg_hireg;
888
889 // Op0 = S2_asl_i_p_or Op1, Op2, Op3
890 // means: Op0 = or (Op1, asl(Op2, Op3))
891
892 // Expansion of
893 // DR = or (R1, asl(R2, #s))
894 //
895 // LoR = or (R1.lo, asl(R2.lo, #s))
896 // Tmp1 = extractu R2.lo, #s, #32-s
897 // Tmp2 = or R1.hi, Tmp1
898 // HiR = or (Tmp2, asl(R2.hi, #s))
899
900 if (S == 0) {
901 // DR = or (R1, asl(R2, #0))
902 // -> or (R1, R2)
903 // i.e. LoR = or R1.lo, R2.lo
904 // HiR = or R1.hi, R2.hi
905 BuildMI(B, MI, DL, TII->get(A2_or), LoR)
906 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
907 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
908 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
909 .addReg(Op1.getReg(), RS1, HiSR)
910 .addReg(Op2.getReg(), RS2, HiSR);
911 } else if (S < 32) {
912 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), LoR)
913 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
914 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
915 .addImm(S);
916 unsigned TmpR1 = MRI->createVirtualRegister(IntRC);
917 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR1)
918 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
919 .addImm(S)
920 .addImm(32-S);
921 unsigned TmpR2 = MRI->createVirtualRegister(IntRC);
922 BuildMI(B, MI, DL, TII->get(A2_or), TmpR2)
923 .addReg(Op1.getReg(), RS1, HiSR)
924 .addReg(TmpR1);
925 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
926 .addReg(TmpR2)
927 .addReg(Op2.getReg(), RS2, HiSR)
928 .addImm(S);
929 } else if (S == 32) {
930 // DR = or (R1, asl(R2, #32))
931 // -> or R1, R2.lo
932 // LoR = R1.lo
933 // HiR = or R1.hi, R2.lo
934 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
935 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
936 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
937 .addReg(Op1.getReg(), RS1, HiSR)
938 .addReg(Op2.getReg(), RS2, LoSR);
939 } else if (S < 64) {
940 // DR = or (R1, asl(R2, #s))
941 //
942 // LoR = R1:lo
943 // HiR = or (R1:hi, asl(R2:lo, #s-32))
944 S -= 32;
945 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
946 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
947 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
948 .addReg(Op1.getReg(), RS1, HiSR)
949 .addReg(Op2.getReg(), RS2, LoSR)
950 .addImm(S);
951 }
952 }
953
954
splitInstr(MachineInstr * MI,const UUPairMap & PairMap)955 bool HexagonSplitDoubleRegs::splitInstr(MachineInstr *MI,
956 const UUPairMap &PairMap) {
957 DEBUG(dbgs() << "Splitting: " << *MI);
958 bool Split = false;
959 unsigned Opc = MI->getOpcode();
960 using namespace Hexagon;
961
962 switch (Opc) {
963 case TargetOpcode::PHI:
964 case TargetOpcode::COPY: {
965 unsigned DstR = MI->getOperand(0).getReg();
966 if (MRI->getRegClass(DstR) == DoubleRC) {
967 createHalfInstr(Opc, MI, PairMap, subreg_loreg);
968 createHalfInstr(Opc, MI, PairMap, subreg_hireg);
969 Split = true;
970 }
971 break;
972 }
973 case A2_andp:
974 createHalfInstr(A2_and, MI, PairMap, subreg_loreg);
975 createHalfInstr(A2_and, MI, PairMap, subreg_hireg);
976 Split = true;
977 break;
978 case A2_orp:
979 createHalfInstr(A2_or, MI, PairMap, subreg_loreg);
980 createHalfInstr(A2_or, MI, PairMap, subreg_hireg);
981 Split = true;
982 break;
983 case A2_xorp:
984 createHalfInstr(A2_xor, MI, PairMap, subreg_loreg);
985 createHalfInstr(A2_xor, MI, PairMap, subreg_hireg);
986 Split = true;
987 break;
988
989 case L2_loadrd_io:
990 case L2_loadrd_pi:
991 case S2_storerd_io:
992 case S2_storerd_pi:
993 splitMemRef(MI, PairMap);
994 Split = true;
995 break;
996
997 case A2_tfrpi:
998 case CONST64_Int_Real:
999 splitImmediate(MI, PairMap);
1000 Split = true;
1001 break;
1002
1003 case A2_combineii:
1004 case A4_combineir:
1005 case A4_combineii:
1006 case A4_combineri:
1007 case A2_combinew:
1008 splitCombine(MI, PairMap);
1009 Split = true;
1010 break;
1011
1012 case A2_sxtw:
1013 splitExt(MI, PairMap);
1014 Split = true;
1015 break;
1016
1017 case S2_asl_i_p:
1018 case S2_asr_i_p:
1019 case S2_lsr_i_p:
1020 splitShift(MI, PairMap);
1021 Split = true;
1022 break;
1023
1024 case S2_asl_i_p_or:
1025 splitAslOr(MI, PairMap);
1026 Split = true;
1027 break;
1028
1029 default:
1030 llvm_unreachable("Instruction not splitable");
1031 return false;
1032 }
1033
1034 return Split;
1035 }
1036
1037
replaceSubregUses(MachineInstr * MI,const UUPairMap & PairMap)1038 void HexagonSplitDoubleRegs::replaceSubregUses(MachineInstr *MI,
1039 const UUPairMap &PairMap) {
1040 for (auto &Op : MI->operands()) {
1041 if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())
1042 continue;
1043 unsigned R = Op.getReg();
1044 UUPairMap::const_iterator F = PairMap.find(R);
1045 if (F == PairMap.end())
1046 continue;
1047 const UUPair &P = F->second;
1048 switch (Op.getSubReg()) {
1049 case Hexagon::subreg_loreg:
1050 Op.setReg(P.first);
1051 break;
1052 case Hexagon::subreg_hireg:
1053 Op.setReg(P.second);
1054 break;
1055 }
1056 Op.setSubReg(0);
1057 }
1058 }
1059
1060
collapseRegPairs(MachineInstr * MI,const UUPairMap & PairMap)1061 void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
1062 const UUPairMap &PairMap) {
1063 MachineBasicBlock &B = *MI->getParent();
1064 DebugLoc DL = MI->getDebugLoc();
1065
1066 for (auto &Op : MI->operands()) {
1067 if (!Op.isReg() || !Op.isUse())
1068 continue;
1069 unsigned R = Op.getReg();
1070 if (!TargetRegisterInfo::isVirtualRegister(R))
1071 continue;
1072 if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())
1073 continue;
1074 UUPairMap::const_iterator F = PairMap.find(R);
1075 if (F == PairMap.end())
1076 continue;
1077 const UUPair &Pr = F->second;
1078 unsigned NewDR = MRI->createVirtualRegister(DoubleRC);
1079 BuildMI(B, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), NewDR)
1080 .addReg(Pr.first)
1081 .addImm(Hexagon::subreg_loreg)
1082 .addReg(Pr.second)
1083 .addImm(Hexagon::subreg_hireg);
1084 Op.setReg(NewDR);
1085 }
1086 }
1087
1088
splitPartition(const USet & Part)1089 bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
1090 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
1091 typedef std::set<MachineInstr*> MISet;
1092 bool Changed = false;
1093
1094 DEBUG(dbgs() << "Splitting partition: "; dump_partition(dbgs(), Part, *TRI);
1095 dbgs() << '\n');
1096
1097 UUPairMap PairMap;
1098
1099 MISet SplitIns;
1100 for (unsigned DR : Part) {
1101 MachineInstr *DefI = MRI->getVRegDef(DR);
1102 SplitIns.insert(DefI);
1103
1104 // Collect all instructions, including fixed ones. We won't split them,
1105 // but we need to visit them again to insert the REG_SEQUENCE instructions.
1106 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
1107 U != W; ++U)
1108 SplitIns.insert(U->getParent());
1109
1110 unsigned LoR = MRI->createVirtualRegister(IntRC);
1111 unsigned HiR = MRI->createVirtualRegister(IntRC);
1112 DEBUG(dbgs() << "Created mapping: " << PrintReg(DR, TRI) << " -> "
1113 << PrintReg(HiR, TRI) << ':' << PrintReg(LoR, TRI) << '\n');
1114 PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR)));
1115 }
1116
1117 MISet Erase;
1118 for (auto MI : SplitIns) {
1119 if (isFixedInstr(MI)) {
1120 collapseRegPairs(MI, PairMap);
1121 } else {
1122 bool Done = splitInstr(MI, PairMap);
1123 if (Done)
1124 Erase.insert(MI);
1125 Changed |= Done;
1126 }
1127 }
1128
1129 for (unsigned DR : Part) {
1130 // Before erasing "double" instructions, revisit all uses of the double
1131 // registers in this partition, and replace all uses of them with subre-
1132 // gisters, with the corresponding single registers.
1133 MISet Uses;
1134 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
1135 U != W; ++U)
1136 Uses.insert(U->getParent());
1137 for (auto M : Uses)
1138 replaceSubregUses(M, PairMap);
1139 }
1140
1141 for (auto MI : Erase) {
1142 MachineBasicBlock *B = MI->getParent();
1143 B->erase(MI);
1144 }
1145
1146 return Changed;
1147 }
1148
1149
runOnMachineFunction(MachineFunction & MF)1150 bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) {
1151 DEBUG(dbgs() << "Splitting double registers in function: "
1152 << MF.getName() << '\n');
1153
1154 if (skipFunction(*MF.getFunction()))
1155 return false;
1156
1157 auto &ST = MF.getSubtarget<HexagonSubtarget>();
1158 TRI = ST.getRegisterInfo();
1159 TII = ST.getInstrInfo();
1160 MRI = &MF.getRegInfo();
1161 MLI = &getAnalysis<MachineLoopInfo>();
1162
1163 UUSetMap P2Rs;
1164 LoopRegMap IRM;
1165
1166 collectIndRegs(IRM);
1167 partitionRegisters(P2Rs);
1168
1169 DEBUG({
1170 dbgs() << "Register partitioning: (partition #0 is fixed)\n";
1171 for (UUSetMap::iterator I = P2Rs.begin(), E = P2Rs.end(); I != E; ++I) {
1172 dbgs() << '#' << I->first << " -> ";
1173 dump_partition(dbgs(), I->second, *TRI);
1174 dbgs() << '\n';
1175 }
1176 });
1177
1178 bool Changed = false;
1179 int Limit = MaxHSDR;
1180
1181 for (UUSetMap::iterator I = P2Rs.begin(), E = P2Rs.end(); I != E; ++I) {
1182 if (I->first == 0)
1183 continue;
1184 if (Limit >= 0 && Counter >= Limit)
1185 break;
1186 USet &Part = I->second;
1187 DEBUG(dbgs() << "Calculating profit for partition #" << I->first << '\n');
1188 if (!isProfitable(Part, IRM))
1189 continue;
1190 Counter++;
1191 Changed |= splitPartition(Part);
1192 }
1193
1194 return Changed;
1195 }
1196
createHexagonSplitDoubleRegs()1197 FunctionPass *llvm::createHexagonSplitDoubleRegs() {
1198 return new HexagonSplitDoubleRegs();
1199 }
1200