1; Show that we know how to translate lsl. 2 3; NOTE: We use -O2 to get rid of memory stores. 4 5; REQUIRES: allow_dump 6 7; Compile using standalone assembler. 8; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 9; RUN: | FileCheck %s --check-prefix=ASM 10 11; Show bytes in assembled standalone code. 12; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 13; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 14 15; Compile using integrated assembler. 16; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ 17; RUN: | FileCheck %s --check-prefix=IASM 18 19; Show bytes in assembled integrated code. 20; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 21; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 22 23define internal i32 @ShlAmt(i32 %a) { 24; ASM-LABEL:ShlAmt: 25; DIS-LABEL:00000000 <ShlAmt>: 26; IASM-LABEL:ShlAmt: 27 28entry: 29; ASM-NEXT:.LShlAmt$entry: 30; IASM-NEXT:.LShlAmt$entry: 31 32 %shl = shl i32 %a, 23 33 34; ASM-NEXT: lsl r0, r0, #23 35; DIS-NEXT: 0: e1a00b80 36; IASM-NOT: lsl 37 38 ret i32 %shl 39} 40 41define internal i32 @ShlReg(i32 %a, i32 %b) { 42; ASM-LABEL:ShlReg: 43; DIS-LABEL:00000010 <ShlReg>: 44; IASM-LABEL:ShlReg: 45 46entry: 47; ASM-NEXT:.LShlReg$entry: 48; IASM-NEXT:.LShlReg$entry: 49 50 %shl = shl i32 %a, %b 51 52; ASM-NEXT: lsl r0, r0, r1 53; DIS-NEXT: 10: e1a00110 54; IASM-NOT: lsl 55 56 ret i32 %shl 57} 58 59define internal <4 x i32> @ShlVec(<4 x i32> %a, <4 x i32> %b) { 60; ASM-LABEL:ShlVec: 61; DIS-LABEL:00000020 <ShlVec>: 62; IASM-LABEL:ShlVec: 63 64entry: 65; ASM-NEXT:.LShlVec$entry: 66; IASM-NEXT:.LShlVec$entry: 67 68 %shl = shl <4 x i32> %a, %b 69 70; ASM: vshl.u32 q0, q0, q1 71; DIS: 20: f3220440 72; IASM-NOT: vshl 73 74 ret <4 x i32> %shl 75} 76 77define internal <8 x i16> @ShlVeci16(<8 x i16> %a, <8 x i16> %b) { 78; ASM-LABEL:ShlVeci16: 79 80entry: 81 82 %v = shl <8 x i16> %a, %b 83 84; ASM: vshl.u16 q0, q0, q1 85; DIS: 30: f3120440 86; IASM-NOT: vshl 87 88 ret <8 x i16> %v 89} 90 91define internal <16 x i8> @ShlVeci8(<16 x i8> %a, <16 x i8> %b) { 92; ASM-LABEL:ShlVeci8: 93 94entry: 95 96 %v = shl <16 x i8> %a, %b 97 98; ASM: vshl.u8 q0, q0, q1 99; DIS: 40: f3020440 100; IASM-NOT: vshl 101 102 ret <16 x i8> %v 103} 104