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1//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains instruction formats, definitions and patterns needed for
11// VIS, VIS II, VIS II instructions on SPARC.
12//===----------------------------------------------------------------------===//
13
14// VIS Instruction Format.
15class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
16      list<dag> pattern>
17      : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
18
19class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
20       : VISInstFormat<opfval,
21        (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
22        !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
23
24// VIS Instruction with integer destination register.
25class VISInstID<bits<9> opfval, string OpcStr>
26       : VISInstFormat<opfval,
27        (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
28        !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
29
30// For VIS Instructions with no operand.
31let rd = 0, rs1 = 0, rs2 = 0 in
32class VISInst0<bits<9> opfval, string asmstr>
33       : VISInstFormat<opfval, (outs), (ins), asmstr, []>;
34
35// For VIS Instructions with only rs1, rd operands.
36let rs2 = 0 in
37class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
38       : VISInstFormat<opfval,
39        (outs RC:$rd), (ins RC:$rs1),
40        !strconcat(OpcStr, " $rs1, $rd"), []>;
41
42// For VIS Instructions with only rs2, rd operands.
43let rs1 = 0 in
44class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
45       : VISInstFormat<opfval,
46        (outs RC:$rd), (ins RC:$rs2),
47        !strconcat(OpcStr, " $rs2, $rd"), []>;
48
49// For VIS Instructions with only rd operand.
50let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
51class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
52       : VISInstFormat<opfval,
53        (outs RC:$rd), (ins RC:$f),
54        !strconcat(OpcStr, " $rd"), []>;
55
56// VIS 1 Instructions
57let Predicates = [HasVIS] in {
58
59def FPADD16     : VISInst<0b001010000, "fpadd16">;
60def FPADD16S    : VISInst<0b001010001, "fpadd16s">;
61def FPADD32     : VISInst<0b001010010, "fpadd32">;
62def FPADD32S    : VISInst<0b001010011, "fpadd32s">;
63def FPSUB16     : VISInst<0b001010100, "fpsub16">;
64def FPSUB16S    : VISInst<0b001010101, "fpsub16S">;
65def FPSUB32     : VISInst<0b001010110, "fpsub32">;
66def FPSUB32S    : VISInst<0b001010111, "fpsub32S">;
67
68def FPACK16     : VISInst2<0b000111011, "fpack16">;
69def FPACK32     : VISInst <0b000111010, "fpack32">;
70def FPACKFIX    : VISInst2<0b000111101, "fpackfix">;
71def FEXPAND     : VISInst2<0b001001101, "fexpand">;
72def FPMERGE     : VISInst <0b001001011, "fpmerge">;
73
74def FMUL8X16    : VISInst<0b000110001, "fmul8x16">;
75def FMUL8X16AU  : VISInst<0b000110011, "fmul8x16au">;
76def FMUL8X16AL  : VISInst<0b000110101, "fmul8x16al">;
77def FMUL8SUX16  : VISInst<0b000110110, "fmul8sux16">;
78def FMUL8ULX16  : VISInst<0b000110111, "fmul8ulx16">;
79def FMULD8SUX16 : VISInst<0b000111000, "fmuld8sux16">;
80def FMULD8ULX16 : VISInst<0b000111001, "fmuld8ulx16">;
81
82def ALIGNADDR   : VISInst<0b000011000, "alignaddr", I64Regs>;
83def ALIGNADDRL  : VISInst<0b000011010, "alignaddrl", I64Regs>;
84def FALIGNADATA : VISInst<0b001001000, "faligndata">;
85
86def FZERO       : VISInstD<0b001100000, "fzero">;
87def FZEROS      : VISInstD<0b001100001, "fzeros", FPRegs>;
88def FONE        : VISInstD<0b001111110, "fone">;
89def FONES       : VISInstD<0b001111111, "fones", FPRegs>;
90def FSRC1       : VISInst1<0b001110100, "fsrc1">;
91def FSRC1S      : VISInst1<0b001110101, "fsrc1s", FPRegs>;
92def FSRC2       : VISInst2<0b001111000, "fsrc2">;
93def FSRC2S      : VISInst2<0b001111001, "fsrc2s", FPRegs>;
94def FNOT1       : VISInst1<0b001101010, "fnot1">;
95def FNOT1S      : VISInst1<0b001101011, "fnot1s", FPRegs>;
96def FNOT2       : VISInst2<0b001100110, "fnot2">;
97def FNOT2S      : VISInst2<0b001100111, "fnot2s", FPRegs>;
98def FOR         : VISInst<0b001111100,  "for">;
99def FORS        : VISInst<0b001111101,  "fors",  FPRegs>;
100def FNOR        : VISInst<0b001100010,  "fnor">;
101def FNORS       : VISInst<0b001100011,  "fnors", FPRegs>;
102def FAND        : VISInst<0b001110000,  "fand">;
103def FANDS       : VISInst<0b001110001,  "fands", FPRegs>;
104def FNAND       : VISInst<0b001101110,  "fnand">;
105def FNANDS      : VISInst<0b001101111,  "fnands", FPRegs>;
106def FXOR        : VISInst<0b001101100,  "fxor">;
107def FXORS       : VISInst<0b001101101,  "fxors", FPRegs>;
108def FXNOR       : VISInst<0b001110010,  "fxnor">;
109def FXNORS      : VISInst<0b001110011,  "fxnors", FPRegs>;
110
111def FORNOT1     : VISInst<0b001111010,  "fornot1">;
112def FORNOT1S    : VISInst<0b001111011,  "fornot1s",  FPRegs>;
113def FORNOT2     : VISInst<0b001110110,  "fornot2">;
114def FORNOT2S    : VISInst<0b001110111,  "fornot2s",  FPRegs>;
115def FANDNOT1    : VISInst<0b001101000,  "fandnot1">;
116def FANDNOT1S   : VISInst<0b001101001,  "fandnot1s", FPRegs>;
117def FANDNOT2    : VISInst<0b001100100,  "fandnot2">;
118def FANDNOT2S   : VISInst<0b001100101,  "fandnot2s", FPRegs>;
119
120def FCMPGT16    : VISInstID<0b000101000,  "fcmpgt16">;
121def FCMPGT32    : VISInstID<0b000101100,  "fcmpgt32">;
122def FCMPLE16    : VISInstID<0b000100000,  "fcmple16">;
123def FCMPLE32    : VISInstID<0b000100100,  "fcmple32">;
124def FCMPNE16    : VISInstID<0b000100010,  "fcmpne16">;
125def FCMPNE32    : VISInstID<0b000100110,  "fcmpne32">;
126def FCMPEQ16    : VISInstID<0b000101010,  "fcmpeq16">;
127def FCMPEQ32    : VISInstID<0b000101110,  "fcmpeq32">;
128
129
130def EDGE8       : VISInst<0b000000000,  "edge8",   I64Regs>;
131def EDGE8L      : VISInst<0b000000010,  "edge8l",  I64Regs>;
132def EDGE16      : VISInst<0b000000100,  "edge16",  I64Regs>;
133def EDGE16L     : VISInst<0b000000110,  "edge16l", I64Regs>;
134def EDGE32      : VISInst<0b000001000,  "edge32",  I64Regs>;
135def EDGE32L     : VISInst<0b000001010,  "edge32l", I64Regs>;
136
137def PDIST       : VISInst<0b000111110, "pdist">;
138
139def ARRAY8      : VISInst<0b000010000, "array8",  I64Regs>;
140def ARRAY16     : VISInst<0b000010010, "array16", I64Regs>;
141def ARRAY32     : VISInst<0b000010100, "array32", I64Regs>;
142
143def SHUTDOWN    : VISInst0<0b010000000, "shutdown">;
144
145} // Predicates = [HasVIS]
146
147
148// VIS 2 Instructions.
149let Predicates = [HasVIS2] in {
150
151def BMASK     : VISInst<0b000011001, "bmask", I64Regs>;
152def BSHUFFLE  : VISInst<0b000011100, "bshuffle">;
153
154def SIAM      : VISInst0<0b010000001, "siam">;
155
156def EDGE8N    : VISInst<0b000000001,  "edge8n",   I64Regs>;
157def EDGE8LN   : VISInst<0b000000011,  "edge8ln",  I64Regs>;
158def EDGE16N   : VISInst<0b000000101,  "edge16n",  I64Regs>;
159def EDGE16LN  : VISInst<0b000000111,  "edge16ln", I64Regs>;
160def EDGE32N   : VISInst<0b000001001,  "edge32n",  I64Regs>;
161def EDGE32LN  : VISInst<0b000001011,  "edge32ln", I64Regs>;
162} // Predicates = [HasVIS2]
163
164
165// VIS 3 Instructions.
166let Predicates = [HasVIS3] in {
167
168let Uses = [ICC] in
169def ADDXC : VISInst<0b000010001, "addxc", I64Regs>;
170
171let Defs = [ICC], Uses = [ICC] in
172def ADDXCCC : VISInst<0b000010011, "addxccc", I64Regs>;
173
174let rd = 0, rs1 = 0 in {
175def CMASK8  : VISInstFormat<0b000011011, (outs), (ins I64Regs:$rs2),
176              "cmask8 $rs2", []>;
177def CMASK16  : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2),
178              "cmask16 $rs2", []>;
179def CMASK32  : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
180              "cmask32 $rs2", []>;
181
182}
183
184def FCHKSM16 : VISInst<0b001000100, "fchksm16">;
185
186def FHADDS   : F3_3<0b10, 0b110100, 0b001100001,
187                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
188                    "fhadds $rs1, $rs2, $rd", []>;
189def FHADDD   : F3_3<0b10, 0b110100, 0b001100010,
190                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
191                    "fhaddd $rs1, $rs2, $rd", []>;
192def FHSUBS   : F3_3<0b10, 0b110100, 0b001100101,
193                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
194                    "fhsubs $rs1, $rs2, $rd", []>;
195def FHSUBD   : F3_3<0b10, 0b110100, 0b001100110,
196                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
197                    "fhsubd $rs1, $rs2, $rd", []>;
198def FLCMPS   : VISInstFormat<0b101010001, (outs FCCRegs:$rd),
199                     (ins DFPRegs:$rs1, DFPRegs:$rs2),
200                     "flcmps $rd, $rs1, $rs2", []>;
201def FLCMPD   : VISInstFormat<0b101010010, (outs FCCRegs:$rd),
202                     (ins DFPRegs:$rs1, DFPRegs:$rs2),
203                     "flcmpd $rd, $rs1, $rs2", []>;
204
205def FMEAN16  : VISInst<0b001000000, "fmean16">;
206
207def FNADDS   : F3_3<0b10, 0b110100, 0b001010001,
208                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
209                    "fnadds $rs1, $rs2, $rd", []>;
210def FNADDD   : F3_3<0b10, 0b110100, 0b001010010,
211                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
212                    "fnaddd $rs1, $rs2, $rd", []>;
213def FNHADDS  : F3_3<0b10, 0b110100, 0b001110001,
214                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
215                    "fnhadds $rs1, $rs2, $rd", []>;
216def FNHADDD  : F3_3<0b10, 0b110100, 0b001110010,
217                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
218                    "fnhaddd $rs1, $rs2, $rd", []>;
219
220def FNMULS   : F3_3<0b10, 0b110100, 0b001011001,
221                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
222                    "fnhadds $rs1, $rs2, $rd", []>;
223def FNMULD   : F3_3<0b10, 0b110100, 0b001011010,
224                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
225                    "fnhaddd $rs1, $rs2, $rd", []>;
226def FNSMULD  : F3_3<0b10, 0b110100, 0b001111001,
227                    (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
228                    "fnhadds $rs1, $rs2, $rd", []>;
229
230def FPADD64   : VISInst<0b001000010, "fpadd64">;
231
232def FSLL16    : VISInst<0b000100001, "fsll16">;
233def FSRL16    : VISInst<0b000100011, "fsrl16">;
234def FSLL32    : VISInst<0b000100101, "fsll32">;
235def FSRL32    : VISInst<0b000100111, "fsrl32">;
236def FSLAS16   : VISInst<0b000101001, "fslas16">;
237def FSRA16    : VISInst<0b000101011, "fsra16">;
238def FSLAS32   : VISInst<0b000101101, "fslas32">;
239def FSRA32    : VISInst<0b000101111, "fsra32">;
240
241let rs1 = 0 in
242def LZCNT     : VISInstFormat<0b000010111, (outs I64Regs:$rd),
243                   (ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
244
245let rs1 = 0 in {
246def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
247                   (ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;
248def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd),
249                   (ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>;
250def MOVDTOX  : VISInstFormat<0b100010000, (outs I64Regs:$rd),
251                   (ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>;
252def MOVWTOS  :  VISInstFormat<0b100011001, (outs DFPRegs:$rd),
253                   (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
254def MOVXTOD  :  VISInstFormat<0b100011000, (outs DFPRegs:$rd),
255                   (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
256}
257
258def PDISTN   : VISInst<0b000111111, "pdistn">;
259
260def UMULXHI  : VISInst<0b000010110, "umulxhi", I64Regs>;
261def XMULX    : VISInst<0b100010101, "xmulx",   I64Regs>;
262def XMULXHI  : VISInst<0b100010111, "xmulxhi", I64Regs>;
263} // Predicates = [IsVIS3]
264