1//===- TableGen'erated file -------------------------------------*- C++ -*-===// 2// 3// Assembly Matcher Source Fragment 4// 5// Automatically generated file, do not edit! 6// 7//===----------------------------------------------------------------------===// 8 9 10#ifdef GET_ASSEMBLER_HEADER 11#undef GET_ASSEMBLER_HEADER 12 // This should be included into the middle of the declaration of 13 // your subclasses implementation of MCTargetAsmParser. 14 unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const; 15 bool ConvertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 16 const SmallVectorImpl<MCParsedAsmOperand*> &Operands); 17 bool MnemonicIsValid(StringRef Mnemonic); 18 unsigned MatchInstructionImpl( 19 const SmallVectorImpl<MCParsedAsmOperand*> &Operands, 20 MCInst &Inst, unsigned &ErrorInfo); 21#endif // GET_ASSEMBLER_HEADER_INFO 22 23 24#ifdef GET_REGISTER_MATCHER 25#undef GET_REGISTER_MATCHER 26 27// Flags for subtarget features that participate in instruction matching. 28enum SubtargetFeatureFlag { 29 Feature_In32BitMode = (1 << 0), 30 Feature_In64BitMode = (1 << 1), 31 Feature_IsNaCl = (1 << 2), 32 Feature_IsNaCl32 = (1 << 3), 33 Feature_IsNaCl64 = (1 << 4), 34 Feature_NotNaCl = (1 << 5), 35 Feature_None = 0 36}; 37 38static unsigned MatchRegisterName(StringRef Name) { 39 switch (Name.size()) { 40 default: break; 41 case 2: // 25 strings to match. 42 switch (Name[0]) { 43 default: break; 44 case 'a': // 3 strings to match. 45 switch (Name[1]) { 46 default: break; 47 case 'h': // 1 string to match. 48 return 1; // "ah" 49 case 'l': // 1 string to match. 50 return 2; // "al" 51 case 'x': // 1 string to match. 52 return 3; // "ax" 53 } 54 break; 55 case 'b': // 4 strings to match. 56 switch (Name[1]) { 57 default: break; 58 case 'h': // 1 string to match. 59 return 4; // "bh" 60 case 'l': // 1 string to match. 61 return 5; // "bl" 62 case 'p': // 1 string to match. 63 return 6; // "bp" 64 case 'x': // 1 string to match. 65 return 8; // "bx" 66 } 67 break; 68 case 'c': // 4 strings to match. 69 switch (Name[1]) { 70 default: break; 71 case 'h': // 1 string to match. 72 return 9; // "ch" 73 case 'l': // 1 string to match. 74 return 10; // "cl" 75 case 's': // 1 string to match. 76 return 27; // "cs" 77 case 'x': // 1 string to match. 78 return 28; // "cx" 79 } 80 break; 81 case 'd': // 5 strings to match. 82 switch (Name[1]) { 83 default: break; 84 case 'h': // 1 string to match. 85 return 29; // "dh" 86 case 'i': // 1 string to match. 87 return 30; // "di" 88 case 'l': // 1 string to match. 89 return 32; // "dl" 90 case 's': // 1 string to match. 91 return 41; // "ds" 92 case 'x': // 1 string to match. 93 return 42; // "dx" 94 } 95 break; 96 case 'e': // 1 string to match. 97 if (Name[1] != 's') 98 break; 99 return 52; // "es" 100 case 'f': // 1 string to match. 101 if (Name[1] != 's') 102 break; 103 return 62; // "fs" 104 case 'g': // 1 string to match. 105 if (Name[1] != 's') 106 break; 107 return 63; // "gs" 108 case 'i': // 1 string to match. 109 if (Name[1] != 'p') 110 break; 111 return 64; // "ip" 112 case 'r': // 2 strings to match. 113 switch (Name[1]) { 114 default: break; 115 case '8': // 1 string to match. 116 return 73; // "r8" 117 case '9': // 1 string to match. 118 return 77; // "r9" 119 } 120 break; 121 case 's': // 3 strings to match. 122 switch (Name[1]) { 123 default: break; 124 case 'i': // 1 string to match. 125 return 115; // "si" 126 case 'p': // 1 string to match. 127 return 117; // "sp" 128 case 's': // 1 string to match. 129 return 119; // "ss" 130 } 131 break; 132 } 133 break; 134 case 3: // 69 strings to match. 135 switch (Name[0]) { 136 default: break; 137 case 'b': // 1 string to match. 138 if (Name.substr(1, 2) != "pl") 139 break; 140 return 7; // "bpl" 141 case 'c': // 10 strings to match. 142 if (Name[1] != 'r') 143 break; 144 switch (Name[2]) { 145 default: break; 146 case '0': // 1 string to match. 147 return 11; // "cr0" 148 case '1': // 1 string to match. 149 return 12; // "cr1" 150 case '2': // 1 string to match. 151 return 13; // "cr2" 152 case '3': // 1 string to match. 153 return 14; // "cr3" 154 case '4': // 1 string to match. 155 return 15; // "cr4" 156 case '5': // 1 string to match. 157 return 16; // "cr5" 158 case '6': // 1 string to match. 159 return 17; // "cr6" 160 case '7': // 1 string to match. 161 return 18; // "cr7" 162 case '8': // 1 string to match. 163 return 19; // "cr8" 164 case '9': // 1 string to match. 165 return 20; // "cr9" 166 } 167 break; 168 case 'd': // 9 strings to match. 169 switch (Name[1]) { 170 default: break; 171 case 'i': // 1 string to match. 172 if (Name[2] != 'l') 173 break; 174 return 31; // "dil" 175 case 'r': // 8 strings to match. 176 switch (Name[2]) { 177 default: break; 178 case '0': // 1 string to match. 179 return 33; // "dr0" 180 case '1': // 1 string to match. 181 return 34; // "dr1" 182 case '2': // 1 string to match. 183 return 35; // "dr2" 184 case '3': // 1 string to match. 185 return 36; // "dr3" 186 case '4': // 1 string to match. 187 return 37; // "dr4" 188 case '5': // 1 string to match. 189 return 38; // "dr5" 190 case '6': // 1 string to match. 191 return 39; // "dr6" 192 case '7': // 1 string to match. 193 return 40; // "dr7" 194 } 195 break; 196 } 197 break; 198 case 'e': // 10 strings to match. 199 switch (Name[1]) { 200 default: break; 201 case 'a': // 1 string to match. 202 if (Name[2] != 'x') 203 break; 204 return 43; // "eax" 205 case 'b': // 2 strings to match. 206 switch (Name[2]) { 207 default: break; 208 case 'p': // 1 string to match. 209 return 44; // "ebp" 210 case 'x': // 1 string to match. 211 return 45; // "ebx" 212 } 213 break; 214 case 'c': // 1 string to match. 215 if (Name[2] != 'x') 216 break; 217 return 46; // "ecx" 218 case 'd': // 2 strings to match. 219 switch (Name[2]) { 220 default: break; 221 case 'i': // 1 string to match. 222 return 47; // "edi" 223 case 'x': // 1 string to match. 224 return 48; // "edx" 225 } 226 break; 227 case 'i': // 2 strings to match. 228 switch (Name[2]) { 229 default: break; 230 case 'p': // 1 string to match. 231 return 50; // "eip" 232 case 'z': // 1 string to match. 233 return 51; // "eiz" 234 } 235 break; 236 case 's': // 2 strings to match. 237 switch (Name[2]) { 238 default: break; 239 case 'i': // 1 string to match. 240 return 53; // "esi" 241 case 'p': // 1 string to match. 242 return 54; // "esp" 243 } 244 break; 245 } 246 break; 247 case 'f': // 7 strings to match. 248 if (Name[1] != 'p') 249 break; 250 switch (Name[2]) { 251 default: break; 252 case '0': // 1 string to match. 253 return 55; // "fp0" 254 case '1': // 1 string to match. 255 return 56; // "fp1" 256 case '2': // 1 string to match. 257 return 57; // "fp2" 258 case '3': // 1 string to match. 259 return 58; // "fp3" 260 case '4': // 1 string to match. 261 return 59; // "fp4" 262 case '5': // 1 string to match. 263 return 60; // "fp5" 264 case '6': // 1 string to match. 265 return 61; // "fp6" 266 } 267 break; 268 case 'm': // 8 strings to match. 269 if (Name[1] != 'm') 270 break; 271 switch (Name[2]) { 272 default: break; 273 case '0': // 1 string to match. 274 return 65; // "mm0" 275 case '1': // 1 string to match. 276 return 66; // "mm1" 277 case '2': // 1 string to match. 278 return 67; // "mm2" 279 case '3': // 1 string to match. 280 return 68; // "mm3" 281 case '4': // 1 string to match. 282 return 69; // "mm4" 283 case '5': // 1 string to match. 284 return 70; // "mm5" 285 case '6': // 1 string to match. 286 return 71; // "mm6" 287 case '7': // 1 string to match. 288 return 72; // "mm7" 289 } 290 break; 291 case 'r': // 22 strings to match. 292 switch (Name[1]) { 293 default: break; 294 case '1': // 6 strings to match. 295 switch (Name[2]) { 296 default: break; 297 case '0': // 1 string to match. 298 return 81; // "r10" 299 case '1': // 1 string to match. 300 return 85; // "r11" 301 case '2': // 1 string to match. 302 return 89; // "r12" 303 case '3': // 1 string to match. 304 return 93; // "r13" 305 case '4': // 1 string to match. 306 return 97; // "r14" 307 case '5': // 1 string to match. 308 return 101; // "r15" 309 } 310 break; 311 case '8': // 3 strings to match. 312 switch (Name[2]) { 313 default: break; 314 case 'b': // 1 string to match. 315 return 74; // "r8b" 316 case 'd': // 1 string to match. 317 return 75; // "r8d" 318 case 'w': // 1 string to match. 319 return 76; // "r8w" 320 } 321 break; 322 case '9': // 3 strings to match. 323 switch (Name[2]) { 324 default: break; 325 case 'b': // 1 string to match. 326 return 78; // "r9b" 327 case 'd': // 1 string to match. 328 return 79; // "r9d" 329 case 'w': // 1 string to match. 330 return 80; // "r9w" 331 } 332 break; 333 case 'a': // 1 string to match. 334 if (Name[2] != 'x') 335 break; 336 return 105; // "rax" 337 case 'b': // 2 strings to match. 338 switch (Name[2]) { 339 default: break; 340 case 'p': // 1 string to match. 341 return 106; // "rbp" 342 case 'x': // 1 string to match. 343 return 107; // "rbx" 344 } 345 break; 346 case 'c': // 1 string to match. 347 if (Name[2] != 'x') 348 break; 349 return 108; // "rcx" 350 case 'd': // 2 strings to match. 351 switch (Name[2]) { 352 default: break; 353 case 'i': // 1 string to match. 354 return 109; // "rdi" 355 case 'x': // 1 string to match. 356 return 110; // "rdx" 357 } 358 break; 359 case 'i': // 2 strings to match. 360 switch (Name[2]) { 361 default: break; 362 case 'p': // 1 string to match. 363 return 111; // "rip" 364 case 'z': // 1 string to match. 365 return 112; // "riz" 366 } 367 break; 368 case 's': // 2 strings to match. 369 switch (Name[2]) { 370 default: break; 371 case 'i': // 1 string to match. 372 return 113; // "rsi" 373 case 'p': // 1 string to match. 374 return 114; // "rsp" 375 } 376 break; 377 } 378 break; 379 case 's': // 2 strings to match. 380 switch (Name[1]) { 381 default: break; 382 case 'i': // 1 string to match. 383 if (Name[2] != 'l') 384 break; 385 return 116; // "sil" 386 case 'p': // 1 string to match. 387 if (Name[2] != 'l') 388 break; 389 return 118; // "spl" 390 } 391 break; 392 } 393 break; 394 case 4: // 44 strings to match. 395 switch (Name[0]) { 396 default: break; 397 case 'c': // 6 strings to match. 398 if (Name.substr(1, 2) != "r1") 399 break; 400 switch (Name[3]) { 401 default: break; 402 case '0': // 1 string to match. 403 return 21; // "cr10" 404 case '1': // 1 string to match. 405 return 22; // "cr11" 406 case '2': // 1 string to match. 407 return 23; // "cr12" 408 case '3': // 1 string to match. 409 return 24; // "cr13" 410 case '4': // 1 string to match. 411 return 25; // "cr14" 412 case '5': // 1 string to match. 413 return 26; // "cr15" 414 } 415 break; 416 case 'r': // 18 strings to match. 417 if (Name[1] != '1') 418 break; 419 switch (Name[2]) { 420 default: break; 421 case '0': // 3 strings to match. 422 switch (Name[3]) { 423 default: break; 424 case 'b': // 1 string to match. 425 return 82; // "r10b" 426 case 'd': // 1 string to match. 427 return 83; // "r10d" 428 case 'w': // 1 string to match. 429 return 84; // "r10w" 430 } 431 break; 432 case '1': // 3 strings to match. 433 switch (Name[3]) { 434 default: break; 435 case 'b': // 1 string to match. 436 return 86; // "r11b" 437 case 'd': // 1 string to match. 438 return 87; // "r11d" 439 case 'w': // 1 string to match. 440 return 88; // "r11w" 441 } 442 break; 443 case '2': // 3 strings to match. 444 switch (Name[3]) { 445 default: break; 446 case 'b': // 1 string to match. 447 return 90; // "r12b" 448 case 'd': // 1 string to match. 449 return 91; // "r12d" 450 case 'w': // 1 string to match. 451 return 92; // "r12w" 452 } 453 break; 454 case '3': // 3 strings to match. 455 switch (Name[3]) { 456 default: break; 457 case 'b': // 1 string to match. 458 return 94; // "r13b" 459 case 'd': // 1 string to match. 460 return 95; // "r13d" 461 case 'w': // 1 string to match. 462 return 96; // "r13w" 463 } 464 break; 465 case '4': // 3 strings to match. 466 switch (Name[3]) { 467 default: break; 468 case 'b': // 1 string to match. 469 return 98; // "r14b" 470 case 'd': // 1 string to match. 471 return 99; // "r14d" 472 case 'w': // 1 string to match. 473 return 100; // "r14w" 474 } 475 break; 476 case '5': // 3 strings to match. 477 switch (Name[3]) { 478 default: break; 479 case 'b': // 1 string to match. 480 return 102; // "r15b" 481 case 'd': // 1 string to match. 482 return 103; // "r15d" 483 case 'w': // 1 string to match. 484 return 104; // "r15w" 485 } 486 break; 487 } 488 break; 489 case 'x': // 10 strings to match. 490 if (Name.substr(1, 2) != "mm") 491 break; 492 switch (Name[3]) { 493 default: break; 494 case '0': // 1 string to match. 495 return 128; // "xmm0" 496 case '1': // 1 string to match. 497 return 129; // "xmm1" 498 case '2': // 1 string to match. 499 return 130; // "xmm2" 500 case '3': // 1 string to match. 501 return 131; // "xmm3" 502 case '4': // 1 string to match. 503 return 132; // "xmm4" 504 case '5': // 1 string to match. 505 return 133; // "xmm5" 506 case '6': // 1 string to match. 507 return 134; // "xmm6" 508 case '7': // 1 string to match. 509 return 135; // "xmm7" 510 case '8': // 1 string to match. 511 return 136; // "xmm8" 512 case '9': // 1 string to match. 513 return 137; // "xmm9" 514 } 515 break; 516 case 'y': // 10 strings to match. 517 if (Name.substr(1, 2) != "mm") 518 break; 519 switch (Name[3]) { 520 default: break; 521 case '0': // 1 string to match. 522 return 144; // "ymm0" 523 case '1': // 1 string to match. 524 return 145; // "ymm1" 525 case '2': // 1 string to match. 526 return 146; // "ymm2" 527 case '3': // 1 string to match. 528 return 147; // "ymm3" 529 case '4': // 1 string to match. 530 return 148; // "ymm4" 531 case '5': // 1 string to match. 532 return 149; // "ymm5" 533 case '6': // 1 string to match. 534 return 150; // "ymm6" 535 case '7': // 1 string to match. 536 return 151; // "ymm7" 537 case '8': // 1 string to match. 538 return 152; // "ymm8" 539 case '9': // 1 string to match. 540 return 153; // "ymm9" 541 } 542 break; 543 } 544 break; 545 case 5: // 21 strings to match. 546 switch (Name[0]) { 547 default: break; 548 case 'f': // 1 string to match. 549 if (Name.substr(1, 4) != "lags") 550 break; 551 return 49; // "flags" 552 case 's': // 8 strings to match. 553 if (Name.substr(1, 2) != "t(") 554 break; 555 switch (Name[3]) { 556 default: break; 557 case '0': // 1 string to match. 558 if (Name[4] != ')') 559 break; 560 return 120; // "st(0)" 561 case '1': // 1 string to match. 562 if (Name[4] != ')') 563 break; 564 return 121; // "st(1)" 565 case '2': // 1 string to match. 566 if (Name[4] != ')') 567 break; 568 return 122; // "st(2)" 569 case '3': // 1 string to match. 570 if (Name[4] != ')') 571 break; 572 return 123; // "st(3)" 573 case '4': // 1 string to match. 574 if (Name[4] != ')') 575 break; 576 return 124; // "st(4)" 577 case '5': // 1 string to match. 578 if (Name[4] != ')') 579 break; 580 return 125; // "st(5)" 581 case '6': // 1 string to match. 582 if (Name[4] != ')') 583 break; 584 return 126; // "st(6)" 585 case '7': // 1 string to match. 586 if (Name[4] != ')') 587 break; 588 return 127; // "st(7)" 589 } 590 break; 591 case 'x': // 6 strings to match. 592 if (Name.substr(1, 3) != "mm1") 593 break; 594 switch (Name[4]) { 595 default: break; 596 case '0': // 1 string to match. 597 return 138; // "xmm10" 598 case '1': // 1 string to match. 599 return 139; // "xmm11" 600 case '2': // 1 string to match. 601 return 140; // "xmm12" 602 case '3': // 1 string to match. 603 return 141; // "xmm13" 604 case '4': // 1 string to match. 605 return 142; // "xmm14" 606 case '5': // 1 string to match. 607 return 143; // "xmm15" 608 } 609 break; 610 case 'y': // 6 strings to match. 611 if (Name.substr(1, 3) != "mm1") 612 break; 613 switch (Name[4]) { 614 default: break; 615 case '0': // 1 string to match. 616 return 154; // "ymm10" 617 case '1': // 1 string to match. 618 return 155; // "ymm11" 619 case '2': // 1 string to match. 620 return 156; // "ymm12" 621 case '3': // 1 string to match. 622 return 157; // "ymm13" 623 case '4': // 1 string to match. 624 return 158; // "ymm14" 625 case '5': // 1 string to match. 626 return 159; // "ymm15" 627 } 628 break; 629 } 630 break; 631 } 632 return 0; 633} 634 635#endif // GET_REGISTER_MATCHER 636 637 638#ifdef GET_MATCHER_IMPLEMENTATION 639#undef GET_MATCHER_IMPLEMENTATION 640 641static void ApplyMnemonicAliases(StringRef &Mnemonic, unsigned Features) { 642 switch (Mnemonic.size()) { 643 default: break; 644 case 2: // 2 strings to match. 645 if (Mnemonic[0] != 'j') 646 break; 647 switch (Mnemonic[1]) { 648 default: break; 649 case 'c': // 1 string to match. 650 Mnemonic = "jb"; // "jc" 651 return; 652 case 'z': // 1 string to match. 653 Mnemonic = "je"; // "jz" 654 return; 655 } 656 break; 657 case 3: // 12 strings to match. 658 switch (Mnemonic[0]) { 659 default: break; 660 case 'c': // 3 strings to match. 661 switch (Mnemonic[1]) { 662 default: break; 663 case 'b': // 1 string to match. 664 if (Mnemonic[2] != 'w') 665 break; 666 Mnemonic = "cbtw"; // "cbw" 667 return; 668 case 'd': // 1 string to match. 669 if (Mnemonic[2] != 'q') 670 break; 671 Mnemonic = "cltd"; // "cdq" 672 return; 673 case 'w': // 1 string to match. 674 if (Mnemonic[2] != 'd') 675 break; 676 Mnemonic = "cwtd"; // "cwd" 677 return; 678 } 679 break; 680 case 'j': // 8 strings to match. 681 switch (Mnemonic[1]) { 682 default: break; 683 case 'n': // 6 strings to match. 684 switch (Mnemonic[2]) { 685 default: break; 686 case 'a': // 1 string to match. 687 Mnemonic = "jbe"; // "jna" 688 return; 689 case 'b': // 1 string to match. 690 Mnemonic = "jae"; // "jnb" 691 return; 692 case 'c': // 1 string to match. 693 Mnemonic = "jae"; // "jnc" 694 return; 695 case 'g': // 1 string to match. 696 Mnemonic = "jle"; // "jng" 697 return; 698 case 'l': // 1 string to match. 699 Mnemonic = "jge"; // "jnl" 700 return; 701 case 'z': // 1 string to match. 702 Mnemonic = "jne"; // "jnz" 703 return; 704 } 705 break; 706 case 'p': // 2 strings to match. 707 switch (Mnemonic[2]) { 708 default: break; 709 case 'e': // 1 string to match. 710 Mnemonic = "jp"; // "jpe" 711 return; 712 case 'o': // 1 string to match. 713 Mnemonic = "jnp"; // "jpo" 714 return; 715 } 716 break; 717 } 718 break; 719 case 'p': // 1 string to match. 720 if (Mnemonic.substr(1, 2) != "op") 721 break; 722 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "pop" 723 Mnemonic = "popl"; 724 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode) 725 Mnemonic = "popq"; 726 return; 727 } 728 break; 729 case 4: // 22 strings to match. 730 switch (Mnemonic[0]) { 731 default: break; 732 case 'c': // 3 strings to match. 733 switch (Mnemonic[1]) { 734 default: break; 735 case 'a': // 1 string to match. 736 if (Mnemonic.substr(2, 2) != "ll") 737 break; 738 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "call" 739 Mnemonic = "calll"; 740 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode) 741 Mnemonic = "callq"; 742 return; 743 case 'd': // 1 string to match. 744 if (Mnemonic.substr(2, 2) != "qe") 745 break; 746 Mnemonic = "cltq"; // "cdqe" 747 return; 748 case 'w': // 1 string to match. 749 if (Mnemonic.substr(2, 2) != "de") 750 break; 751 Mnemonic = "cwtl"; // "cwde" 752 return; 753 } 754 break; 755 case 'i': // 1 string to match. 756 if (Mnemonic.substr(1, 3) != "ret") 757 break; 758 Mnemonic = "iretl"; // "iret" 759 return; 760 case 'j': // 4 strings to match. 761 if (Mnemonic[1] != 'n') 762 break; 763 switch (Mnemonic[2]) { 764 default: break; 765 case 'a': // 1 string to match. 766 if (Mnemonic[3] != 'e') 767 break; 768 Mnemonic = "jb"; // "jnae" 769 return; 770 case 'b': // 1 string to match. 771 if (Mnemonic[3] != 'e') 772 break; 773 Mnemonic = "ja"; // "jnbe" 774 return; 775 case 'g': // 1 string to match. 776 if (Mnemonic[3] != 'e') 777 break; 778 Mnemonic = "jl"; // "jnge" 779 return; 780 case 'l': // 1 string to match. 781 if (Mnemonic[3] != 'e') 782 break; 783 Mnemonic = "jg"; // "jnle" 784 return; 785 } 786 break; 787 case 'l': // 1 string to match. 788 if (Mnemonic.substr(1, 3) != "ret") 789 break; 790 Mnemonic = "lretl"; // "lret" 791 return; 792 case 'p': // 2 strings to match. 793 switch (Mnemonic[1]) { 794 default: break; 795 case 'o': // 1 string to match. 796 if (Mnemonic.substr(2, 2) != "pf") 797 break; 798 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "popf" 799 Mnemonic = "popfl"; 800 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode) 801 Mnemonic = "popfq"; 802 return; 803 case 'u': // 1 string to match. 804 if (Mnemonic.substr(2, 2) != "sh") 805 break; 806 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "push" 807 Mnemonic = "pushl"; 808 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode) 809 Mnemonic = "pushq"; 810 return; 811 } 812 break; 813 case 'r': // 4 strings to match. 814 if (Mnemonic[1] != 'e') 815 break; 816 switch (Mnemonic[2]) { 817 default: break; 818 case 'p': // 2 strings to match. 819 switch (Mnemonic[3]) { 820 default: break; 821 case 'e': // 1 string to match. 822 Mnemonic = "rep"; // "repe" 823 return; 824 case 'z': // 1 string to match. 825 Mnemonic = "rep"; // "repz" 826 return; 827 } 828 break; 829 case 't': // 2 strings to match. 830 switch (Mnemonic[3]) { 831 default: break; 832 case 'l': // 1 string to match. 833 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "retl" 834 Mnemonic = "ret"; 835 return; 836 case 'q': // 1 string to match. 837 if ((Features & Feature_In64BitMode) == Feature_In64BitMode) // "retq" 838 Mnemonic = "ret"; 839 return; 840 } 841 break; 842 } 843 break; 844 case 's': // 6 strings to match. 845 switch (Mnemonic[1]) { 846 default: break; 847 case 'a': // 4 strings to match. 848 if (Mnemonic[2] != 'l') 849 break; 850 switch (Mnemonic[3]) { 851 default: break; 852 case 'b': // 1 string to match. 853 Mnemonic = "shlb"; // "salb" 854 return; 855 case 'l': // 1 string to match. 856 Mnemonic = "shll"; // "sall" 857 return; 858 case 'q': // 1 string to match. 859 Mnemonic = "shlq"; // "salq" 860 return; 861 case 'w': // 1 string to match. 862 Mnemonic = "shlw"; // "salw" 863 return; 864 } 865 break; 866 case 'e': // 2 strings to match. 867 if (Mnemonic[2] != 't') 868 break; 869 switch (Mnemonic[3]) { 870 default: break; 871 case 'c': // 1 string to match. 872 Mnemonic = "setb"; // "setc" 873 return; 874 case 'z': // 1 string to match. 875 Mnemonic = "sete"; // "setz" 876 return; 877 } 878 break; 879 } 880 break; 881 case 'u': // 1 string to match. 882 if (Mnemonic.substr(1, 3) != "d2a") 883 break; 884 Mnemonic = "ud2"; // "ud2a" 885 return; 886 } 887 break; 888 case 5: // 27 strings to match. 889 switch (Mnemonic[0]) { 890 default: break; 891 case 'f': // 2 strings to match. 892 switch (Mnemonic[1]) { 893 default: break; 894 case 'i': // 1 string to match. 895 if (Mnemonic.substr(2, 3) != "ldq") 896 break; 897 Mnemonic = "fildll"; // "fildq" 898 return; 899 case 'w': // 1 string to match. 900 if (Mnemonic.substr(2, 3) != "ait") 901 break; 902 Mnemonic = "wait"; // "fwait" 903 return; 904 } 905 break; 906 case 'l': // 5 strings to match. 907 switch (Mnemonic[1]) { 908 default: break; 909 case 'g': // 2 strings to match. 910 if (Mnemonic.substr(2, 2) != "dt") 911 break; 912 switch (Mnemonic[4]) { 913 default: break; 914 case 'l': // 1 string to match. 915 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "lgdtl" 916 Mnemonic = "lgdt"; 917 return; 918 case 'q': // 1 string to match. 919 if ((Features & Feature_In64BitMode) == Feature_In64BitMode) // "lgdtq" 920 Mnemonic = "lgdt"; 921 return; 922 } 923 break; 924 case 'i': // 2 strings to match. 925 if (Mnemonic.substr(2, 2) != "dt") 926 break; 927 switch (Mnemonic[4]) { 928 default: break; 929 case 'l': // 1 string to match. 930 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "lidtl" 931 Mnemonic = "lidt"; 932 return; 933 case 'q': // 1 string to match. 934 if ((Features & Feature_In64BitMode) == Feature_In64BitMode) // "lidtq" 935 Mnemonic = "lidt"; 936 return; 937 } 938 break; 939 case 'o': // 1 string to match. 940 if (Mnemonic.substr(2, 3) != "opz") 941 break; 942 Mnemonic = "loope"; // "loopz" 943 return; 944 } 945 break; 946 case 'p': // 2 strings to match. 947 switch (Mnemonic[1]) { 948 default: break; 949 case 'o': // 1 string to match. 950 if (Mnemonic.substr(2, 3) != "pfd") 951 break; 952 Mnemonic = "popfl"; // "popfd" 953 return; 954 case 'u': // 1 string to match. 955 if (Mnemonic.substr(2, 3) != "shf") 956 break; 957 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "pushf" 958 Mnemonic = "pushfl"; 959 else if ((Features & Feature_In64BitMode) == Feature_In64BitMode) 960 Mnemonic = "pushfq"; 961 return; 962 } 963 break; 964 case 'r': // 1 string to match. 965 if (Mnemonic.substr(1, 4) != "epnz") 966 break; 967 Mnemonic = "repne"; // "repnz" 968 return; 969 case 's': // 16 strings to match. 970 switch (Mnemonic[1]) { 971 default: break; 972 case 'e': // 8 strings to match. 973 if (Mnemonic[2] != 't') 974 break; 975 switch (Mnemonic[3]) { 976 default: break; 977 case 'n': // 6 strings to match. 978 switch (Mnemonic[4]) { 979 default: break; 980 case 'a': // 1 string to match. 981 Mnemonic = "setbe"; // "setna" 982 return; 983 case 'b': // 1 string to match. 984 Mnemonic = "setae"; // "setnb" 985 return; 986 case 'c': // 1 string to match. 987 Mnemonic = "setae"; // "setnc" 988 return; 989 case 'g': // 1 string to match. 990 Mnemonic = "setle"; // "setng" 991 return; 992 case 'l': // 1 string to match. 993 Mnemonic = "setge"; // "setnl" 994 return; 995 case 'z': // 1 string to match. 996 Mnemonic = "setne"; // "setnz" 997 return; 998 } 999 break; 1000 case 'p': // 2 strings to match. 1001 switch (Mnemonic[4]) { 1002 default: break; 1003 case 'e': // 1 string to match. 1004 Mnemonic = "setp"; // "setpe" 1005 return; 1006 case 'o': // 1 string to match. 1007 Mnemonic = "setnp"; // "setpo" 1008 return; 1009 } 1010 break; 1011 } 1012 break; 1013 case 'g': // 2 strings to match. 1014 if (Mnemonic.substr(2, 2) != "dt") 1015 break; 1016 switch (Mnemonic[4]) { 1017 default: break; 1018 case 'l': // 1 string to match. 1019 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "sgdtl" 1020 Mnemonic = "sgdt"; 1021 return; 1022 case 'q': // 1 string to match. 1023 if ((Features & Feature_In64BitMode) == Feature_In64BitMode) // "sgdtq" 1024 Mnemonic = "sgdt"; 1025 return; 1026 } 1027 break; 1028 case 'i': // 2 strings to match. 1029 if (Mnemonic.substr(2, 2) != "dt") 1030 break; 1031 switch (Mnemonic[4]) { 1032 default: break; 1033 case 'l': // 1 string to match. 1034 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "sidtl" 1035 Mnemonic = "sidt"; 1036 return; 1037 case 'q': // 1 string to match. 1038 if ((Features & Feature_In64BitMode) == Feature_In64BitMode) // "sidtq" 1039 Mnemonic = "sidt"; 1040 return; 1041 } 1042 break; 1043 case 'm': // 4 strings to match. 1044 if (Mnemonic.substr(2, 2) != "ov") 1045 break; 1046 switch (Mnemonic[4]) { 1047 default: break; 1048 case 'b': // 1 string to match. 1049 Mnemonic = "movsb"; // "smovb" 1050 return; 1051 case 'l': // 1 string to match. 1052 Mnemonic = "movsl"; // "smovl" 1053 return; 1054 case 'q': // 1 string to match. 1055 Mnemonic = "movsq"; // "smovq" 1056 return; 1057 case 'w': // 1 string to match. 1058 Mnemonic = "movsw"; // "smovw" 1059 return; 1060 } 1061 break; 1062 } 1063 break; 1064 case 'v': // 1 string to match. 1065 if (Mnemonic.substr(1, 4) != "errw") 1066 break; 1067 Mnemonic = "verr"; // "verrw" 1068 return; 1069 } 1070 break; 1071 case 6: // 19 strings to match. 1072 switch (Mnemonic[0]) { 1073 default: break; 1074 case 'c': // 6 strings to match. 1075 if (Mnemonic.substr(1, 3) != "mov") 1076 break; 1077 switch (Mnemonic[4]) { 1078 default: break; 1079 case 'c': // 3 strings to match. 1080 switch (Mnemonic[5]) { 1081 default: break; 1082 case 'l': // 1 string to match. 1083 Mnemonic = "cmovbl"; // "cmovcl" 1084 return; 1085 case 'q': // 1 string to match. 1086 Mnemonic = "cmovbq"; // "cmovcq" 1087 return; 1088 case 'w': // 1 string to match. 1089 Mnemonic = "cmovbw"; // "cmovcw" 1090 return; 1091 } 1092 break; 1093 case 'z': // 3 strings to match. 1094 switch (Mnemonic[5]) { 1095 default: break; 1096 case 'l': // 1 string to match. 1097 Mnemonic = "cmovel"; // "cmovzl" 1098 return; 1099 case 'q': // 1 string to match. 1100 Mnemonic = "cmoveq"; // "cmovzq" 1101 return; 1102 case 'w': // 1 string to match. 1103 Mnemonic = "cmovew"; // "cmovzw" 1104 return; 1105 } 1106 break; 1107 } 1108 break; 1109 case 'f': // 4 strings to match. 1110 switch (Mnemonic[1]) { 1111 default: break; 1112 case 'c': // 3 strings to match. 1113 switch (Mnemonic[2]) { 1114 default: break; 1115 case 'm': // 2 strings to match. 1116 if (Mnemonic.substr(3, 2) != "ov") 1117 break; 1118 switch (Mnemonic[5]) { 1119 default: break; 1120 case 'a': // 1 string to match. 1121 Mnemonic = "fcmovnbe"; // "fcmova" 1122 return; 1123 case 'z': // 1 string to match. 1124 Mnemonic = "fcmove"; // "fcmovz" 1125 return; 1126 } 1127 break; 1128 case 'o': // 1 string to match. 1129 if (Mnemonic.substr(3, 3) != "mip") 1130 break; 1131 Mnemonic = "fcompi"; // "fcomip" 1132 return; 1133 } 1134 break; 1135 case 'l': // 1 string to match. 1136 if (Mnemonic.substr(2, 4) != "dcww") 1137 break; 1138 Mnemonic = "fldcw"; // "fldcww" 1139 return; 1140 } 1141 break; 1142 case 'l': // 3 strings to match. 1143 switch (Mnemonic[1]) { 1144 default: break; 1145 case 'e': // 2 strings to match. 1146 if (Mnemonic.substr(2, 3) != "ave") 1147 break; 1148 switch (Mnemonic[5]) { 1149 default: break; 1150 case 'l': // 1 string to match. 1151 if ((Features & Feature_In32BitMode) == Feature_In32BitMode) // "leavel" 1152 Mnemonic = "leave"; 1153 return; 1154 case 'q': // 1 string to match. 1155 if ((Features & Feature_In64BitMode) == Feature_In64BitMode) // "leaveq" 1156 Mnemonic = "leave"; 1157 return; 1158 } 1159 break; 1160 case 'o': // 1 string to match. 1161 if (Mnemonic.substr(2, 4) != "opnz") 1162 break; 1163 Mnemonic = "loopne"; // "loopnz" 1164 return; 1165 } 1166 break; 1167 case 'p': // 1 string to match. 1168 if (Mnemonic.substr(1, 5) != "ushfd") 1169 break; 1170 Mnemonic = "pushfl"; // "pushfd" 1171 return; 1172 case 's': // 5 strings to match. 1173 switch (Mnemonic[1]) { 1174 default: break; 1175 case 'e': // 4 strings to match. 1176 if (Mnemonic.substr(2, 2) != "tn") 1177 break; 1178 switch (Mnemonic[4]) { 1179 default: break; 1180 case 'a': // 1 string to match. 1181 if (Mnemonic[5] != 'e') 1182 break; 1183 Mnemonic = "setb"; // "setnae" 1184 return; 1185 case 'b': // 1 string to match. 1186 if (Mnemonic[5] != 'e') 1187 break; 1188 Mnemonic = "seta"; // "setnbe" 1189 return; 1190 case 'g': // 1 string to match. 1191 if (Mnemonic[5] != 'e') 1192 break; 1193 Mnemonic = "setl"; // "setnge" 1194 return; 1195 case 'l': // 1 string to match. 1196 if (Mnemonic[5] != 'e') 1197 break; 1198 Mnemonic = "setg"; // "setnle" 1199 return; 1200 } 1201 break; 1202 case 'y': // 1 string to match. 1203 if (Mnemonic.substr(2, 4) != "sret") 1204 break; 1205 Mnemonic = "sysretl"; // "sysret" 1206 return; 1207 } 1208 break; 1209 } 1210 break; 1211 case 7: // 29 strings to match. 1212 switch (Mnemonic[0]) { 1213 default: break; 1214 case 'c': // 24 strings to match. 1215 if (Mnemonic.substr(1, 3) != "mov") 1216 break; 1217 switch (Mnemonic[4]) { 1218 default: break; 1219 case 'n': // 18 strings to match. 1220 switch (Mnemonic[5]) { 1221 default: break; 1222 case 'a': // 3 strings to match. 1223 switch (Mnemonic[6]) { 1224 default: break; 1225 case 'l': // 1 string to match. 1226 Mnemonic = "cmovbel"; // "cmovnal" 1227 return; 1228 case 'q': // 1 string to match. 1229 Mnemonic = "cmovbeq"; // "cmovnaq" 1230 return; 1231 case 'w': // 1 string to match. 1232 Mnemonic = "cmovbew"; // "cmovnaw" 1233 return; 1234 } 1235 break; 1236 case 'b': // 3 strings to match. 1237 switch (Mnemonic[6]) { 1238 default: break; 1239 case 'l': // 1 string to match. 1240 Mnemonic = "cmovael"; // "cmovnbl" 1241 return; 1242 case 'q': // 1 string to match. 1243 Mnemonic = "cmovaeq"; // "cmovnbq" 1244 return; 1245 case 'w': // 1 string to match. 1246 Mnemonic = "cmovaew"; // "cmovnbw" 1247 return; 1248 } 1249 break; 1250 case 'c': // 3 strings to match. 1251 switch (Mnemonic[6]) { 1252 default: break; 1253 case 'l': // 1 string to match. 1254 Mnemonic = "cmovael"; // "cmovncl" 1255 return; 1256 case 'q': // 1 string to match. 1257 Mnemonic = "cmovaeq"; // "cmovncq" 1258 return; 1259 case 'w': // 1 string to match. 1260 Mnemonic = "cmovaew"; // "cmovncw" 1261 return; 1262 } 1263 break; 1264 case 'g': // 3 strings to match. 1265 switch (Mnemonic[6]) { 1266 default: break; 1267 case 'l': // 1 string to match. 1268 Mnemonic = "cmovlel"; // "cmovngl" 1269 return; 1270 case 'q': // 1 string to match. 1271 Mnemonic = "cmovleq"; // "cmovngq" 1272 return; 1273 case 'w': // 1 string to match. 1274 Mnemonic = "cmovlew"; // "cmovngw" 1275 return; 1276 } 1277 break; 1278 case 'l': // 3 strings to match. 1279 switch (Mnemonic[6]) { 1280 default: break; 1281 case 'l': // 1 string to match. 1282 Mnemonic = "cmovgel"; // "cmovnll" 1283 return; 1284 case 'q': // 1 string to match. 1285 Mnemonic = "cmovgeq"; // "cmovnlq" 1286 return; 1287 case 'w': // 1 string to match. 1288 Mnemonic = "cmovgew"; // "cmovnlw" 1289 return; 1290 } 1291 break; 1292 case 'z': // 3 strings to match. 1293 switch (Mnemonic[6]) { 1294 default: break; 1295 case 'l': // 1 string to match. 1296 Mnemonic = "cmovnel"; // "cmovnzl" 1297 return; 1298 case 'q': // 1 string to match. 1299 Mnemonic = "cmovneq"; // "cmovnzq" 1300 return; 1301 case 'w': // 1 string to match. 1302 Mnemonic = "cmovnew"; // "cmovnzw" 1303 return; 1304 } 1305 break; 1306 } 1307 break; 1308 case 'p': // 6 strings to match. 1309 switch (Mnemonic[5]) { 1310 default: break; 1311 case 'e': // 3 strings to match. 1312 switch (Mnemonic[6]) { 1313 default: break; 1314 case 'l': // 1 string to match. 1315 Mnemonic = "cmovpl"; // "cmovpel" 1316 return; 1317 case 'q': // 1 string to match. 1318 Mnemonic = "cmovpq"; // "cmovpeq" 1319 return; 1320 case 'w': // 1 string to match. 1321 Mnemonic = "cmovpw"; // "cmovpew" 1322 return; 1323 } 1324 break; 1325 case 'o': // 3 strings to match. 1326 switch (Mnemonic[6]) { 1327 default: break; 1328 case 'l': // 1 string to match. 1329 Mnemonic = "cmovnpl"; // "cmovpol" 1330 return; 1331 case 'q': // 1 string to match. 1332 Mnemonic = "cmovnpq"; // "cmovpoq" 1333 return; 1334 case 'w': // 1 string to match. 1335 Mnemonic = "cmovnpw"; // "cmovpow" 1336 return; 1337 } 1338 break; 1339 } 1340 break; 1341 } 1342 break; 1343 case 'f': // 5 strings to match. 1344 switch (Mnemonic[1]) { 1345 default: break; 1346 case 'c': // 2 strings to match. 1347 if (Mnemonic.substr(2, 3) != "mov") 1348 break; 1349 switch (Mnemonic[5]) { 1350 default: break; 1351 case 'a': // 1 string to match. 1352 if (Mnemonic[6] != 'e') 1353 break; 1354 Mnemonic = "fcmovnb"; // "fcmovae" 1355 return; 1356 case 'n': // 1 string to match. 1357 if (Mnemonic[6] != 'a') 1358 break; 1359 Mnemonic = "fcmovbe"; // "fcmovna" 1360 return; 1361 } 1362 break; 1363 case 'n': // 2 strings to match. 1364 if (Mnemonic.substr(2, 2) != "st") 1365 break; 1366 switch (Mnemonic[4]) { 1367 default: break; 1368 case 'c': // 1 string to match. 1369 if (Mnemonic.substr(5, 2) != "ww") 1370 break; 1371 Mnemonic = "fnstcw"; // "fnstcww" 1372 return; 1373 case 's': // 1 string to match. 1374 if (Mnemonic.substr(5, 2) != "ww") 1375 break; 1376 Mnemonic = "fnstsw"; // "fnstsww" 1377 return; 1378 } 1379 break; 1380 case 'u': // 1 string to match. 1381 if (Mnemonic.substr(2, 5) != "comip") 1382 break; 1383 Mnemonic = "fucompi"; // "fucomip" 1384 return; 1385 } 1386 break; 1387 } 1388 break; 1389 case 8: // 13 strings to match. 1390 switch (Mnemonic[0]) { 1391 default: break; 1392 case 'c': // 12 strings to match. 1393 if (Mnemonic.substr(1, 4) != "movn") 1394 break; 1395 switch (Mnemonic[5]) { 1396 default: break; 1397 case 'a': // 3 strings to match. 1398 if (Mnemonic[6] != 'e') 1399 break; 1400 switch (Mnemonic[7]) { 1401 default: break; 1402 case 'l': // 1 string to match. 1403 Mnemonic = "cmovbl"; // "cmovnael" 1404 return; 1405 case 'q': // 1 string to match. 1406 Mnemonic = "cmovbq"; // "cmovnaeq" 1407 return; 1408 case 'w': // 1 string to match. 1409 Mnemonic = "cmovbw"; // "cmovnaew" 1410 return; 1411 } 1412 break; 1413 case 'b': // 3 strings to match. 1414 if (Mnemonic[6] != 'e') 1415 break; 1416 switch (Mnemonic[7]) { 1417 default: break; 1418 case 'l': // 1 string to match. 1419 Mnemonic = "cmoval"; // "cmovnbel" 1420 return; 1421 case 'q': // 1 string to match. 1422 Mnemonic = "cmovaq"; // "cmovnbeq" 1423 return; 1424 case 'w': // 1 string to match. 1425 Mnemonic = "cmovaw"; // "cmovnbew" 1426 return; 1427 } 1428 break; 1429 case 'g': // 3 strings to match. 1430 if (Mnemonic[6] != 'e') 1431 break; 1432 switch (Mnemonic[7]) { 1433 default: break; 1434 case 'l': // 1 string to match. 1435 Mnemonic = "cmovll"; // "cmovngel" 1436 return; 1437 case 'q': // 1 string to match. 1438 Mnemonic = "cmovlq"; // "cmovngeq" 1439 return; 1440 case 'w': // 1 string to match. 1441 Mnemonic = "cmovlw"; // "cmovngew" 1442 return; 1443 } 1444 break; 1445 case 'l': // 3 strings to match. 1446 if (Mnemonic[6] != 'e') 1447 break; 1448 switch (Mnemonic[7]) { 1449 default: break; 1450 case 'l': // 1 string to match. 1451 Mnemonic = "cmovgl"; // "cmovnlel" 1452 return; 1453 case 'q': // 1 string to match. 1454 Mnemonic = "cmovgq"; // "cmovnleq" 1455 return; 1456 case 'w': // 1 string to match. 1457 Mnemonic = "cmovgw"; // "cmovnlew" 1458 return; 1459 } 1460 break; 1461 } 1462 break; 1463 case 'f': // 1 string to match. 1464 if (Mnemonic.substr(1, 7) != "cmovnae") 1465 break; 1466 Mnemonic = "fcmovb"; // "fcmovnae" 1467 return; 1468 } 1469 break; 1470 } 1471} 1472 1473// Unified function for converting operands to MCInst instances. 1474 1475enum ConversionKind { 1476 Convert, 1477 Convert__imm10, 1478 Convert__Imm1_0, 1479 Convert__Reg1_1__Tie0__Reg1_0, 1480 Convert__Mem5_1__Reg1_0, 1481 Convert__Reg1_1__Tie0__Imm1_0, 1482 Convert__Mem5_1__Imm1_0, 1483 Convert__Reg1_1__Tie0__Mem5_0, 1484 Convert__Reg1_1__Tie0__ImmSExti32i81_0, 1485 Convert__Mem5_1__ImmSExti32i81_0, 1486 Convert__Reg1_1__Tie0__ImmSExti64i81_0, 1487 Convert__Mem5_1__ImmSExti64i81_0, 1488 Convert__ImmSExti64i321_0, 1489 Convert__Reg1_1__Tie0__ImmSExti64i321_0, 1490 Convert__Mem5_1__ImmSExti64i321_0, 1491 Convert__Reg1_1__Tie0__ImmSExti16i81_0, 1492 Convert__Mem5_1__ImmSExti16i81_0, 1493 Convert__Reg1_1__Reg1_0, 1494 Convert__Reg1_1__Mem5_0, 1495 Convert__Reg1_2__Reg1_1__Imm1_0, 1496 Convert__Reg1_2__Mem5_1__Imm1_0, 1497 Convert__Reg1_2__Reg1_1__Reg1_0, 1498 Convert__Reg1_2__Reg1_1__Mem5_0, 1499 Convert__Reg1_0__Reg1_1, 1500 Convert__Reg1_0__Mem5_1, 1501 Convert__Reg1_2__Tie0__Reg1_1__ImmZExtu32u81_0, 1502 Convert__Reg1_2__Tie0__Mem5_1__ImmZExtu32u81_0, 1503 Convert__Reg1_0__Tie0, 1504 Convert__Reg1_1__ImmSExti32i81_0, 1505 Convert__Reg1_1__ImmSExti64i81_0, 1506 Convert__Reg1_1__ImmSExti16i81_0, 1507 Convert__Imm1_1__Imm1_0, 1508 Convert__AbsMem1_0, 1509 Convert__Reg1_1, 1510 Convert__Mem5_1, 1511 Convert__Mem5_0, 1512 Convert__Reg1_0__Tie0__Reg1_0, 1513 Convert__Reg1_3__Tie0__Reg1_2__Imm1_0, 1514 Convert__Reg1_3__Tie0__Mem5_2__Imm1_0, 1515 Convert__Reg1_1__Imm1_0, 1516 Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, 1517 Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, 1518 Convert__Reg1_1__ImmSExti64i321_0, 1519 Convert__Reg1_0, 1520 Convert__Imm1_0__Imm1_1, 1521 Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, 1522 Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, 1523 Convert__regST0, 1524 Convert__regST1, 1525 Convert__Reg1_1__Reg1_1__ImmSExti32i81_0, 1526 Convert__Reg1_1__Reg1_1__Imm1_0, 1527 Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, 1528 Convert__Reg1_1__Reg1_1__ImmSExti64i81_0, 1529 Convert__Reg1_1__Reg1_1__ImmSExti64i321_0, 1530 Convert__Reg1_2__Reg1_1__ImmSExti64i81_0, 1531 Convert__Reg1_2__Mem5_1__ImmSExti64i81_0, 1532 Convert__Reg1_2__Reg1_1__ImmSExti64i321_0, 1533 Convert__Reg1_2__Mem5_1__ImmSExti64i321_0, 1534 Convert__Reg1_1__Reg1_1__ImmSExti16i81_0, 1535 Convert__Reg1_2__Reg1_1__ImmSExti16i81_0, 1536 Convert__Reg1_2__Mem5_1__ImmSExti16i81_0, 1537 Convert__AbsMem1_1, 1538 Convert__Imm1_1, 1539 Convert__Reg1_1__Tie0__Reg1_0__imm17, 1540 Convert__Reg1_1__Tie0__Mem5_0__imm17, 1541 Convert__Reg1_1__Tie0__Reg1_0__imm1, 1542 Convert__Reg1_1__Tie0__Mem5_0__imm1, 1543 Convert__Reg1_1__Tie0__Reg1_0__imm16, 1544 Convert__Reg1_1__Tie0__Mem5_0__imm16, 1545 Convert__Reg1_1__Tie0__Reg1_0__imm0, 1546 Convert__Reg1_1__Tie0__Mem5_0__imm0, 1547 Convert__Reg1_2__Tie0__Reg1_1__ImmSExti32i81_0, 1548 Convert__Reg1_2__Tie0__Mem5_1__ImmSExti32i81_0, 1549 Convert__ImmSExti32i81_0, 1550 Convert__ImmSExti64i81_0, 1551 Convert__Reg1_1__Tie0, 1552 Convert__Reg1_0__Tie0__Reg1_1__imm1, 1553 Convert__Mem5_0__Reg1_1__imm1, 1554 Convert__Reg1_2__Tie0__Reg1_1, 1555 Convert__Mem5_2__Reg1_1, 1556 Convert__Mem5_2__Reg1_1__Imm1_0, 1557 Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, 1558 Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, 1559 Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, 1560 Convert__Reg1_3__Reg1_2__Mem5_1__Reg1_0, 1561 Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0, 1562 Convert__Reg1_4__Reg1_3__Mem5_2__Imm1_0, 1563 Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, 1564 Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, 1565 Convert__Mem5_2__Reg1_1__Reg1_0, 1566 Convert__Reg1_2__Reg1_1__Reg1_0__imm17, 1567 Convert__Reg1_2__Reg1_1__Mem5_0__imm17, 1568 Convert__Reg1_2__Reg1_1__Reg1_0__imm1, 1569 Convert__Reg1_2__Reg1_1__Mem5_0__imm1, 1570 Convert__Reg1_2__Reg1_1__Reg1_0__imm16, 1571 Convert__Reg1_2__Reg1_1__Mem5_0__imm16, 1572 Convert__Reg1_2__Reg1_1__Reg1_0__imm0, 1573 Convert__Reg1_2__Reg1_1__Mem5_0__imm0, 1574 Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, 1575 Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0, 1576 Convert__Reg1_0__Tie0__Reg1_1, 1577 Convert__Reg1_0__Tie0__Mem5_1, 1578 NumConversionVariants 1579}; 1580 1581bool X86ATTAsmParser:: 1582ConvertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 1583 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1584 Inst.setOpcode(Opcode); 1585 switch (Kind) { 1586 default: 1587 case Convert: 1588 return true; 1589 case Convert__imm10: 1590 Inst.addOperand(MCOperand::CreateImm(10)); 1591 return true; 1592 case Convert__Imm1_0: 1593 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1594 return true; 1595 case Convert__Reg1_1__Tie0__Reg1_0: 1596 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1597 Inst.addOperand(Inst.getOperand(0)); 1598 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1599 return true; 1600 case Convert__Mem5_1__Reg1_0: 1601 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1602 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1603 return true; 1604 case Convert__Reg1_1__Tie0__Imm1_0: 1605 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1606 Inst.addOperand(Inst.getOperand(0)); 1607 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1608 return true; 1609 case Convert__Mem5_1__Imm1_0: 1610 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1611 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1612 return true; 1613 case Convert__Reg1_1__Tie0__Mem5_0: 1614 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1615 Inst.addOperand(Inst.getOperand(0)); 1616 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 1617 return true; 1618 case Convert__Reg1_1__Tie0__ImmSExti32i81_0: 1619 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1620 Inst.addOperand(Inst.getOperand(0)); 1621 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1622 return true; 1623 case Convert__Mem5_1__ImmSExti32i81_0: 1624 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1625 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1626 return true; 1627 case Convert__Reg1_1__Tie0__ImmSExti64i81_0: 1628 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1629 Inst.addOperand(Inst.getOperand(0)); 1630 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1631 return true; 1632 case Convert__Mem5_1__ImmSExti64i81_0: 1633 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1634 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1635 return true; 1636 case Convert__ImmSExti64i321_0: 1637 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1638 return true; 1639 case Convert__Reg1_1__Tie0__ImmSExti64i321_0: 1640 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1641 Inst.addOperand(Inst.getOperand(0)); 1642 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1643 return true; 1644 case Convert__Mem5_1__ImmSExti64i321_0: 1645 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1646 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1647 return true; 1648 case Convert__Reg1_1__Tie0__ImmSExti16i81_0: 1649 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1650 Inst.addOperand(Inst.getOperand(0)); 1651 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1652 return true; 1653 case Convert__Mem5_1__ImmSExti16i81_0: 1654 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1655 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1656 return true; 1657 case Convert__Reg1_1__Reg1_0: 1658 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1659 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1660 return true; 1661 case Convert__Reg1_1__Mem5_0: 1662 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1663 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 1664 return true; 1665 case Convert__Reg1_2__Reg1_1__Imm1_0: 1666 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1667 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1668 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1669 return true; 1670 case Convert__Reg1_2__Mem5_1__Imm1_0: 1671 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1672 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1673 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1674 return true; 1675 case Convert__Reg1_2__Reg1_1__Reg1_0: 1676 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1677 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1678 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1679 return true; 1680 case Convert__Reg1_2__Reg1_1__Mem5_0: 1681 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1682 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1683 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 1684 return true; 1685 case Convert__Reg1_0__Reg1_1: 1686 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1687 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1688 return true; 1689 case Convert__Reg1_0__Mem5_1: 1690 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1691 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1692 return true; 1693 case Convert__Reg1_2__Tie0__Reg1_1__ImmZExtu32u81_0: 1694 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1695 Inst.addOperand(Inst.getOperand(0)); 1696 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1697 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1698 return true; 1699 case Convert__Reg1_2__Tie0__Mem5_1__ImmZExtu32u81_0: 1700 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1701 Inst.addOperand(Inst.getOperand(0)); 1702 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1703 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1704 return true; 1705 case Convert__Reg1_0__Tie0: 1706 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1707 Inst.addOperand(Inst.getOperand(0)); 1708 return true; 1709 case Convert__Reg1_1__ImmSExti32i81_0: 1710 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1711 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1712 return true; 1713 case Convert__Reg1_1__ImmSExti64i81_0: 1714 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1715 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1716 return true; 1717 case Convert__Reg1_1__ImmSExti16i81_0: 1718 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1719 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1720 return true; 1721 case Convert__Imm1_1__Imm1_0: 1722 ((X86Operand*)Operands[2])->addImmOperands(Inst, 1); 1723 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1724 return true; 1725 case Convert__AbsMem1_0: 1726 ((X86Operand*)Operands[1])->addAbsMemOperands(Inst, 1); 1727 return true; 1728 case Convert__Reg1_1: 1729 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1730 return true; 1731 case Convert__Mem5_1: 1732 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1733 return true; 1734 case Convert__Mem5_0: 1735 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 1736 return true; 1737 case Convert__Reg1_0__Tie0__Reg1_0: 1738 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1739 Inst.addOperand(Inst.getOperand(0)); 1740 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1741 return true; 1742 case Convert__Reg1_3__Tie0__Reg1_2__Imm1_0: 1743 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 1744 Inst.addOperand(Inst.getOperand(0)); 1745 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1746 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1747 return true; 1748 case Convert__Reg1_3__Tie0__Mem5_2__Imm1_0: 1749 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 1750 Inst.addOperand(Inst.getOperand(0)); 1751 ((X86Operand*)Operands[3])->addMemOperands(Inst, 5); 1752 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1753 return true; 1754 case Convert__Reg1_1__Imm1_0: 1755 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1756 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1757 return true; 1758 case Convert__Reg1_2__Tie0__Reg1_1__Imm1_0: 1759 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1760 Inst.addOperand(Inst.getOperand(0)); 1761 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1762 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1763 return true; 1764 case Convert__Reg1_2__Tie0__Mem5_1__Imm1_0: 1765 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1766 Inst.addOperand(Inst.getOperand(0)); 1767 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1768 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1769 return true; 1770 case Convert__Reg1_1__ImmSExti64i321_0: 1771 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1772 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1773 return true; 1774 case Convert__Reg1_0: 1775 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1776 return true; 1777 case Convert__Imm1_0__Imm1_1: 1778 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1779 ((X86Operand*)Operands[2])->addImmOperands(Inst, 1); 1780 return true; 1781 case Convert__Reg1_2__Reg1_1__ImmSExti32i81_0: 1782 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1783 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1784 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1785 return true; 1786 case Convert__Mem5_2__Reg1_1__ImmSExti32i81_0: 1787 ((X86Operand*)Operands[3])->addMemOperands(Inst, 5); 1788 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1789 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1790 return true; 1791 case Convert__regST0: 1792 Inst.addOperand(MCOperand::CreateReg(X86::ST0)); 1793 return true; 1794 case Convert__regST1: 1795 Inst.addOperand(MCOperand::CreateReg(X86::ST1)); 1796 return true; 1797 case Convert__Reg1_1__Reg1_1__ImmSExti32i81_0: 1798 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1799 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1800 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1801 return true; 1802 case Convert__Reg1_1__Reg1_1__Imm1_0: 1803 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1804 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1805 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1806 return true; 1807 case Convert__Reg1_2__Mem5_1__ImmSExti32i81_0: 1808 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1809 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1810 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1811 return true; 1812 case Convert__Reg1_1__Reg1_1__ImmSExti64i81_0: 1813 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1814 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1815 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1816 return true; 1817 case Convert__Reg1_1__Reg1_1__ImmSExti64i321_0: 1818 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1819 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1820 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1821 return true; 1822 case Convert__Reg1_2__Reg1_1__ImmSExti64i81_0: 1823 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1824 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1825 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1826 return true; 1827 case Convert__Reg1_2__Mem5_1__ImmSExti64i81_0: 1828 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1829 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1830 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1831 return true; 1832 case Convert__Reg1_2__Reg1_1__ImmSExti64i321_0: 1833 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1834 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1835 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1836 return true; 1837 case Convert__Reg1_2__Mem5_1__ImmSExti64i321_0: 1838 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1839 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1840 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1841 return true; 1842 case Convert__Reg1_1__Reg1_1__ImmSExti16i81_0: 1843 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1844 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1845 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1846 return true; 1847 case Convert__Reg1_2__Reg1_1__ImmSExti16i81_0: 1848 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1849 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1850 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1851 return true; 1852 case Convert__Reg1_2__Mem5_1__ImmSExti16i81_0: 1853 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1854 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1855 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1856 return true; 1857 case Convert__AbsMem1_1: 1858 ((X86Operand*)Operands[2])->addAbsMemOperands(Inst, 1); 1859 return true; 1860 case Convert__Imm1_1: 1861 ((X86Operand*)Operands[2])->addImmOperands(Inst, 1); 1862 return true; 1863 case Convert__Reg1_1__Tie0__Reg1_0__imm17: 1864 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1865 Inst.addOperand(Inst.getOperand(0)); 1866 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1867 Inst.addOperand(MCOperand::CreateImm(17)); 1868 return true; 1869 case Convert__Reg1_1__Tie0__Mem5_0__imm17: 1870 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1871 Inst.addOperand(Inst.getOperand(0)); 1872 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 1873 Inst.addOperand(MCOperand::CreateImm(17)); 1874 return true; 1875 case Convert__Reg1_1__Tie0__Reg1_0__imm1: 1876 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1877 Inst.addOperand(Inst.getOperand(0)); 1878 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1879 Inst.addOperand(MCOperand::CreateImm(1)); 1880 return true; 1881 case Convert__Reg1_1__Tie0__Mem5_0__imm1: 1882 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1883 Inst.addOperand(Inst.getOperand(0)); 1884 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 1885 Inst.addOperand(MCOperand::CreateImm(1)); 1886 return true; 1887 case Convert__Reg1_1__Tie0__Reg1_0__imm16: 1888 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1889 Inst.addOperand(Inst.getOperand(0)); 1890 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1891 Inst.addOperand(MCOperand::CreateImm(16)); 1892 return true; 1893 case Convert__Reg1_1__Tie0__Mem5_0__imm16: 1894 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1895 Inst.addOperand(Inst.getOperand(0)); 1896 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 1897 Inst.addOperand(MCOperand::CreateImm(16)); 1898 return true; 1899 case Convert__Reg1_1__Tie0__Reg1_0__imm0: 1900 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1901 Inst.addOperand(Inst.getOperand(0)); 1902 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1903 Inst.addOperand(MCOperand::CreateImm(0)); 1904 return true; 1905 case Convert__Reg1_1__Tie0__Mem5_0__imm0: 1906 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1907 Inst.addOperand(Inst.getOperand(0)); 1908 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 1909 Inst.addOperand(MCOperand::CreateImm(0)); 1910 return true; 1911 case Convert__Reg1_2__Tie0__Reg1_1__ImmSExti32i81_0: 1912 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1913 Inst.addOperand(Inst.getOperand(0)); 1914 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1915 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1916 return true; 1917 case Convert__Reg1_2__Tie0__Mem5_1__ImmSExti32i81_0: 1918 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1919 Inst.addOperand(Inst.getOperand(0)); 1920 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1921 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1922 return true; 1923 case Convert__ImmSExti32i81_0: 1924 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1925 return true; 1926 case Convert__ImmSExti64i81_0: 1927 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1928 return true; 1929 case Convert__Reg1_1__Tie0: 1930 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1931 Inst.addOperand(Inst.getOperand(0)); 1932 return true; 1933 case Convert__Reg1_0__Tie0__Reg1_1__imm1: 1934 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1935 Inst.addOperand(Inst.getOperand(0)); 1936 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1937 Inst.addOperand(MCOperand::CreateImm(1)); 1938 return true; 1939 case Convert__Mem5_0__Reg1_1__imm1: 1940 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 1941 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1942 Inst.addOperand(MCOperand::CreateImm(1)); 1943 return true; 1944 case Convert__Reg1_2__Tie0__Reg1_1: 1945 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1946 Inst.addOperand(Inst.getOperand(0)); 1947 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1948 return true; 1949 case Convert__Mem5_2__Reg1_1: 1950 ((X86Operand*)Operands[3])->addMemOperands(Inst, 5); 1951 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1952 return true; 1953 case Convert__Mem5_2__Reg1_1__Imm1_0: 1954 ((X86Operand*)Operands[3])->addMemOperands(Inst, 5); 1955 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1956 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1957 return true; 1958 case Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0: 1959 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 1960 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1961 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1962 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1963 return true; 1964 case Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0: 1965 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 1966 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1967 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1968 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1969 return true; 1970 case Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0: 1971 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 1972 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1973 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1974 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1975 return true; 1976 case Convert__Reg1_3__Reg1_2__Mem5_1__Reg1_0: 1977 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 1978 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1979 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 1980 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 1981 return true; 1982 case Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0: 1983 ((X86Operand*)Operands[5])->addRegOperands(Inst, 1); 1984 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 1985 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1986 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1987 return true; 1988 case Convert__Reg1_4__Reg1_3__Mem5_2__Imm1_0: 1989 ((X86Operand*)Operands[5])->addRegOperands(Inst, 1); 1990 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 1991 ((X86Operand*)Operands[3])->addMemOperands(Inst, 5); 1992 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1993 return true; 1994 case Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0: 1995 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 1996 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 1997 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 1998 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 1999 return true; 2000 case Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0: 2001 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 2002 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2003 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 2004 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 2005 return true; 2006 case Convert__Mem5_2__Reg1_1__Reg1_0: 2007 ((X86Operand*)Operands[3])->addMemOperands(Inst, 5); 2008 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2009 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 2010 return true; 2011 case Convert__Reg1_2__Reg1_1__Reg1_0__imm17: 2012 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2013 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2014 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 2015 Inst.addOperand(MCOperand::CreateImm(17)); 2016 return true; 2017 case Convert__Reg1_2__Reg1_1__Mem5_0__imm17: 2018 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2019 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2020 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 2021 Inst.addOperand(MCOperand::CreateImm(17)); 2022 return true; 2023 case Convert__Reg1_2__Reg1_1__Reg1_0__imm1: 2024 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2025 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2026 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 2027 Inst.addOperand(MCOperand::CreateImm(1)); 2028 return true; 2029 case Convert__Reg1_2__Reg1_1__Mem5_0__imm1: 2030 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2031 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2032 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 2033 Inst.addOperand(MCOperand::CreateImm(1)); 2034 return true; 2035 case Convert__Reg1_2__Reg1_1__Reg1_0__imm16: 2036 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2037 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2038 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 2039 Inst.addOperand(MCOperand::CreateImm(16)); 2040 return true; 2041 case Convert__Reg1_2__Reg1_1__Mem5_0__imm16: 2042 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2043 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2044 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 2045 Inst.addOperand(MCOperand::CreateImm(16)); 2046 return true; 2047 case Convert__Reg1_2__Reg1_1__Reg1_0__imm0: 2048 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2049 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2050 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 2051 Inst.addOperand(MCOperand::CreateImm(0)); 2052 return true; 2053 case Convert__Reg1_2__Reg1_1__Mem5_0__imm0: 2054 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2055 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2056 ((X86Operand*)Operands[1])->addMemOperands(Inst, 5); 2057 Inst.addOperand(MCOperand::CreateImm(0)); 2058 return true; 2059 case Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0: 2060 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 2061 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2062 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2063 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 2064 return true; 2065 case Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0: 2066 ((X86Operand*)Operands[4])->addRegOperands(Inst, 1); 2067 ((X86Operand*)Operands[3])->addRegOperands(Inst, 1); 2068 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 2069 ((X86Operand*)Operands[1])->addImmOperands(Inst, 1); 2070 return true; 2071 case Convert__Reg1_0__Tie0__Reg1_1: 2072 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 2073 Inst.addOperand(Inst.getOperand(0)); 2074 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1); 2075 return true; 2076 case Convert__Reg1_0__Tie0__Mem5_1: 2077 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1); 2078 Inst.addOperand(Inst.getOperand(0)); 2079 ((X86Operand*)Operands[2])->addMemOperands(Inst, 5); 2080 return true; 2081 } 2082 return false; 2083} 2084 2085namespace { 2086 2087/// MatchClassKind - The kinds of classes which participate in 2088/// instruction matching. 2089enum MatchClassKind { 2090 InvalidMatchClass = 0, 2091 MCK__STAR_, // '*' 2092 MCK_pd, // 'pd' 2093 MCK_ps, // 'ps' 2094 MCK_sd, // 'sd' 2095 MCK_ss, // 'ss' 2096 MCK_AL, // register class 'AL' 2097 MCK_CL, // register class 'CL' 2098 MCK_GR8_ABCD_L, // register class 'GR8_ABCD_L' 2099 MCK_GR8_ABCD_H, // register class 'GR8_ABCD_H' 2100 MCK_GR8_NOREX, // register class 'GR8_NOREX' 2101 MCK_GR8, // register class 'GR8' 2102 MCK_AX, // register class 'AX' 2103 MCK_DX, // register class 'DX' 2104 MCK_GR16_ABCD, // register class 'GR16_ABCD' 2105 MCK_GR16_NOREX, // register class 'GR16_NOREX' 2106 MCK_GR16, // register class 'GR16' 2107 MCK_EAX, // register class 'EAX' 2108 MCK_EDX, // register class 'EDX' 2109 MCK_Reg20, // derived register class 2110 MCK_Reg21, // derived register class 2111 MCK_Reg22, // derived register class 2112 MCK_Reg24, // derived register class 2113 MCK_GR32_AD, // register class 'GR32_AD' 2114 MCK_ECX, // register class 'ECX' 2115 MCK_GR32_TC, // register class 'GR32_TC' 2116 MCK_GR32_ABCD, // register class 'GR32_ABCD' 2117 MCK_GR32_NOAX, // register class 'GR32_NOAX' 2118 MCK_GR32_NOREX_NOSP, // register class 'GR32_NOREX_NOSP' 2119 MCK_GR32_NOREX, // register class 'GR32_NOREX' 2120 MCK_GR32_NOSP, // register class 'GR32_NOSP' 2121 MCK_GR32, // register class 'GR32' 2122 MCK_RAX, // register class 'RAX' 2123 MCK_RDX, // register class 'RDX' 2124 MCK_RCX, // register class 'RCX' 2125 MCK_Reg27, // derived register class 2126 MCK_Reg35, // derived register class 2127 MCK_GR64_ABCD, // register class 'GR64_ABCD' 2128 MCK_GR64_NOREX_NOSP, // register class 'GR64_NOREX_NOSP' 2129 MCK_Reg30, // derived register class 2130 MCK_Reg31, // derived register class 2131 MCK_GR64_NOREX, // register class 'GR64_NOREX' 2132 MCK_GR64_TCW64, // register class 'GR64_TCW64' 2133 MCK_Reg36, // derived register class 2134 MCK_Reg38, // derived register class 2135 MCK_GR64_NOSP, // register class 'GR64_NOSP' 2136 MCK_GR64_TC, // register class 'GR64_TC' 2137 MCK_GR64, // register class 'GR64' 2138 MCK_VR64, // register class 'VR64' 2139 MCK_RFP32, // register class 'RFP32,RFP64,RFP80' 2140 MCK_FR32, // register class 'FR32,FR64,VR128' 2141 MCK_VR256, // register class 'VR256' 2142 MCK_ST0, // register class 'ST0' 2143 MCK_RST, // register class 'RST' 2144 MCK_CCR, // register class 'CCR' 2145 MCK_CS, // register class 'CS' 2146 MCK_DS, // register class 'DS' 2147 MCK_SS, // register class 'SS' 2148 MCK_ES, // register class 'ES' 2149 MCK_FS, // register class 'FS' 2150 MCK_GS, // register class 'GS' 2151 MCK_SEGMENT_REG, // register class 'SEGMENT_REG' 2152 MCK_DEBUG_REG, // register class 'DEBUG_REG' 2153 MCK_CONTROL_REG, // register class 'CONTROL_REG' 2154 MCK_ImmSExti64i8, // user defined class 'ImmSExti64i8AsmOperand' 2155 MCK_ImmSExti16i8, // user defined class 'ImmSExti16i8AsmOperand' 2156 MCK_ImmSExti32i8, // user defined class 'ImmSExti32i8AsmOperand' 2157 MCK_ImmSExti64i32, // user defined class 'ImmSExti64i32AsmOperand' 2158 MCK_ImmZExtu32u8, // user defined class 'ImmZExtu32u8AsmOperand' 2159 MCK_Imm, // user defined class 'ImmAsmOperand' 2160 MCK_AbsMem, // user defined class 'X86AbsMemAsmOperand' 2161 MCK_Mem, // user defined class 'X86MemAsmOperand' 2162 NumMatchClassKinds 2163}; 2164 2165} 2166 2167static MatchClassKind MatchTokenString(StringRef Name) { 2168 switch (Name.size()) { 2169 default: break; 2170 case 1: // 1 string to match. 2171 if (Name[0] != '*') 2172 break; 2173 return MCK__STAR_; // "*" 2174 case 2: // 4 strings to match. 2175 switch (Name[0]) { 2176 default: break; 2177 case 'p': // 2 strings to match. 2178 switch (Name[1]) { 2179 default: break; 2180 case 'd': // 1 string to match. 2181 return MCK_pd; // "pd" 2182 case 's': // 1 string to match. 2183 return MCK_ps; // "ps" 2184 } 2185 break; 2186 case 's': // 2 strings to match. 2187 switch (Name[1]) { 2188 default: break; 2189 case 'd': // 1 string to match. 2190 return MCK_sd; // "sd" 2191 case 's': // 1 string to match. 2192 return MCK_ss; // "ss" 2193 } 2194 break; 2195 } 2196 break; 2197 } 2198 return InvalidMatchClass; 2199} 2200 2201/// IsSubclass - Compute whether \arg A is a subclass of \arg B. 2202static bool IsSubclass(MatchClassKind A, MatchClassKind B) { 2203 if (A == B) 2204 return true; 2205 2206 switch (A) { 2207 default: 2208 return false; 2209 2210 case MCK_AL: 2211 switch (B) { 2212 default: return false; 2213 case MCK_GR8_ABCD_L: return true; 2214 case MCK_GR8_NOREX: return true; 2215 case MCK_GR8: return true; 2216 } 2217 2218 case MCK_CL: 2219 switch (B) { 2220 default: return false; 2221 case MCK_GR8_ABCD_L: return true; 2222 case MCK_GR8_NOREX: return true; 2223 case MCK_GR8: return true; 2224 } 2225 2226 case MCK_GR8_ABCD_L: 2227 switch (B) { 2228 default: return false; 2229 case MCK_GR8_NOREX: return true; 2230 case MCK_GR8: return true; 2231 } 2232 2233 case MCK_GR8_ABCD_H: 2234 switch (B) { 2235 default: return false; 2236 case MCK_GR8_NOREX: return true; 2237 case MCK_GR8: return true; 2238 } 2239 2240 case MCK_GR8_NOREX: 2241 return B == MCK_GR8; 2242 2243 case MCK_AX: 2244 switch (B) { 2245 default: return false; 2246 case MCK_GR16_ABCD: return true; 2247 case MCK_GR16_NOREX: return true; 2248 case MCK_GR16: return true; 2249 } 2250 2251 case MCK_DX: 2252 switch (B) { 2253 default: return false; 2254 case MCK_GR16_ABCD: return true; 2255 case MCK_GR16_NOREX: return true; 2256 case MCK_GR16: return true; 2257 } 2258 2259 case MCK_GR16_ABCD: 2260 switch (B) { 2261 default: return false; 2262 case MCK_GR16_NOREX: return true; 2263 case MCK_GR16: return true; 2264 } 2265 2266 case MCK_GR16_NOREX: 2267 return B == MCK_GR16; 2268 2269 case MCK_EAX: 2270 switch (B) { 2271 default: return false; 2272 case MCK_GR32_AD: return true; 2273 case MCK_GR32_TC: return true; 2274 case MCK_GR32_ABCD: return true; 2275 case MCK_GR32_NOREX_NOSP: return true; 2276 case MCK_GR32_NOREX: return true; 2277 case MCK_GR32_NOSP: return true; 2278 case MCK_GR32: return true; 2279 } 2280 2281 case MCK_EDX: 2282 switch (B) { 2283 default: return false; 2284 case MCK_Reg20: return true; 2285 case MCK_Reg21: return true; 2286 case MCK_Reg22: return true; 2287 case MCK_Reg24: return true; 2288 case MCK_GR32_AD: return true; 2289 case MCK_GR32_TC: return true; 2290 case MCK_GR32_ABCD: return true; 2291 case MCK_GR32_NOAX: return true; 2292 case MCK_GR32_NOREX_NOSP: return true; 2293 case MCK_GR32_NOREX: return true; 2294 case MCK_GR32_NOSP: return true; 2295 case MCK_GR32: return true; 2296 } 2297 2298 case MCK_Reg20: 2299 switch (B) { 2300 default: return false; 2301 case MCK_Reg21: return true; 2302 case MCK_Reg22: return true; 2303 case MCK_Reg24: return true; 2304 case MCK_GR32_ABCD: return true; 2305 case MCK_GR32_NOAX: return true; 2306 case MCK_GR32_NOREX_NOSP: return true; 2307 case MCK_GR32_NOREX: return true; 2308 case MCK_GR32_NOSP: return true; 2309 case MCK_GR32: return true; 2310 } 2311 2312 case MCK_Reg21: 2313 switch (B) { 2314 default: return false; 2315 case MCK_Reg22: return true; 2316 case MCK_Reg24: return true; 2317 case MCK_GR32_NOAX: return true; 2318 case MCK_GR32_NOREX_NOSP: return true; 2319 case MCK_GR32_NOREX: return true; 2320 case MCK_GR32_NOSP: return true; 2321 case MCK_GR32: return true; 2322 } 2323 2324 case MCK_Reg22: 2325 switch (B) { 2326 default: return false; 2327 case MCK_GR32_NOAX: return true; 2328 case MCK_GR32_NOREX: return true; 2329 case MCK_GR32: return true; 2330 } 2331 2332 case MCK_Reg24: 2333 switch (B) { 2334 default: return false; 2335 case MCK_GR32_NOAX: return true; 2336 case MCK_GR32_NOSP: return true; 2337 case MCK_GR32: return true; 2338 } 2339 2340 case MCK_GR32_AD: 2341 switch (B) { 2342 default: return false; 2343 case MCK_GR32_TC: return true; 2344 case MCK_GR32_ABCD: return true; 2345 case MCK_GR32_NOREX_NOSP: return true; 2346 case MCK_GR32_NOREX: return true; 2347 case MCK_GR32_NOSP: return true; 2348 case MCK_GR32: return true; 2349 } 2350 2351 case MCK_ECX: 2352 switch (B) { 2353 default: return false; 2354 case MCK_Reg20: return true; 2355 case MCK_Reg21: return true; 2356 case MCK_Reg22: return true; 2357 case MCK_Reg24: return true; 2358 case MCK_GR32_TC: return true; 2359 case MCK_GR32_ABCD: return true; 2360 case MCK_GR32_NOAX: return true; 2361 case MCK_GR32_NOREX_NOSP: return true; 2362 case MCK_GR32_NOREX: return true; 2363 case MCK_GR32_NOSP: return true; 2364 case MCK_GR32: return true; 2365 } 2366 2367 case MCK_GR32_TC: 2368 switch (B) { 2369 default: return false; 2370 case MCK_GR32_ABCD: return true; 2371 case MCK_GR32_NOREX_NOSP: return true; 2372 case MCK_GR32_NOREX: return true; 2373 case MCK_GR32_NOSP: return true; 2374 case MCK_GR32: return true; 2375 } 2376 2377 case MCK_GR32_ABCD: 2378 switch (B) { 2379 default: return false; 2380 case MCK_GR32_NOREX_NOSP: return true; 2381 case MCK_GR32_NOREX: return true; 2382 case MCK_GR32_NOSP: return true; 2383 case MCK_GR32: return true; 2384 } 2385 2386 case MCK_GR32_NOAX: 2387 return B == MCK_GR32; 2388 2389 case MCK_GR32_NOREX_NOSP: 2390 switch (B) { 2391 default: return false; 2392 case MCK_GR32_NOREX: return true; 2393 case MCK_GR32_NOSP: return true; 2394 case MCK_GR32: return true; 2395 } 2396 2397 case MCK_GR32_NOREX: 2398 return B == MCK_GR32; 2399 2400 case MCK_GR32_NOSP: 2401 return B == MCK_GR32; 2402 2403 case MCK_RAX: 2404 switch (B) { 2405 default: return false; 2406 case MCK_Reg27: return true; 2407 case MCK_Reg35: return true; 2408 case MCK_GR64_ABCD: return true; 2409 case MCK_GR64_NOREX_NOSP: return true; 2410 case MCK_Reg30: return true; 2411 case MCK_Reg31: return true; 2412 case MCK_GR64_NOREX: return true; 2413 case MCK_GR64_TCW64: return true; 2414 case MCK_Reg36: return true; 2415 case MCK_Reg38: return true; 2416 case MCK_GR64_NOSP: return true; 2417 case MCK_GR64_TC: return true; 2418 case MCK_GR64: return true; 2419 } 2420 2421 case MCK_RDX: 2422 switch (B) { 2423 default: return false; 2424 case MCK_Reg27: return true; 2425 case MCK_Reg35: return true; 2426 case MCK_GR64_ABCD: return true; 2427 case MCK_GR64_NOREX_NOSP: return true; 2428 case MCK_Reg30: return true; 2429 case MCK_Reg31: return true; 2430 case MCK_GR64_NOREX: return true; 2431 case MCK_GR64_TCW64: return true; 2432 case MCK_Reg36: return true; 2433 case MCK_Reg38: return true; 2434 case MCK_GR64_NOSP: return true; 2435 case MCK_GR64_TC: return true; 2436 case MCK_GR64: return true; 2437 } 2438 2439 case MCK_RCX: 2440 switch (B) { 2441 default: return false; 2442 case MCK_Reg27: return true; 2443 case MCK_Reg35: return true; 2444 case MCK_GR64_ABCD: return true; 2445 case MCK_GR64_NOREX_NOSP: return true; 2446 case MCK_Reg30: return true; 2447 case MCK_Reg31: return true; 2448 case MCK_GR64_NOREX: return true; 2449 case MCK_GR64_TCW64: return true; 2450 case MCK_Reg36: return true; 2451 case MCK_Reg38: return true; 2452 case MCK_GR64_NOSP: return true; 2453 case MCK_GR64_TC: return true; 2454 case MCK_GR64: return true; 2455 } 2456 2457 case MCK_Reg27: 2458 switch (B) { 2459 default: return false; 2460 case MCK_Reg35: return true; 2461 case MCK_GR64_ABCD: return true; 2462 case MCK_GR64_NOREX_NOSP: return true; 2463 case MCK_Reg30: return true; 2464 case MCK_Reg31: return true; 2465 case MCK_GR64_NOREX: return true; 2466 case MCK_GR64_TCW64: return true; 2467 case MCK_Reg36: return true; 2468 case MCK_Reg38: return true; 2469 case MCK_GR64_NOSP: return true; 2470 case MCK_GR64_TC: return true; 2471 case MCK_GR64: return true; 2472 } 2473 2474 case MCK_Reg35: 2475 switch (B) { 2476 default: return false; 2477 case MCK_GR64_NOREX_NOSP: return true; 2478 case MCK_Reg30: return true; 2479 case MCK_Reg31: return true; 2480 case MCK_GR64_NOREX: return true; 2481 case MCK_Reg36: return true; 2482 case MCK_Reg38: return true; 2483 case MCK_GR64_NOSP: return true; 2484 case MCK_GR64_TC: return true; 2485 case MCK_GR64: return true; 2486 } 2487 2488 case MCK_GR64_ABCD: 2489 switch (B) { 2490 default: return false; 2491 case MCK_GR64_NOREX_NOSP: return true; 2492 case MCK_Reg30: return true; 2493 case MCK_Reg31: return true; 2494 case MCK_GR64_NOREX: return true; 2495 case MCK_GR64_NOSP: return true; 2496 case MCK_GR64: return true; 2497 } 2498 2499 case MCK_GR64_NOREX_NOSP: 2500 switch (B) { 2501 default: return false; 2502 case MCK_Reg30: return true; 2503 case MCK_Reg31: return true; 2504 case MCK_GR64_NOREX: return true; 2505 case MCK_GR64_NOSP: return true; 2506 case MCK_GR64: return true; 2507 } 2508 2509 case MCK_Reg30: 2510 switch (B) { 2511 default: return false; 2512 case MCK_Reg31: return true; 2513 case MCK_GR64_NOREX: return true; 2514 case MCK_GR64: return true; 2515 } 2516 2517 case MCK_Reg31: 2518 return B == MCK_GR64; 2519 2520 case MCK_GR64_NOREX: 2521 return B == MCK_GR64; 2522 2523 case MCK_GR64_TCW64: 2524 switch (B) { 2525 default: return false; 2526 case MCK_Reg31: return true; 2527 case MCK_Reg36: return true; 2528 case MCK_GR64_NOSP: return true; 2529 case MCK_GR64_TC: return true; 2530 case MCK_GR64: return true; 2531 } 2532 2533 case MCK_Reg36: 2534 switch (B) { 2535 default: return false; 2536 case MCK_Reg31: return true; 2537 case MCK_GR64_NOSP: return true; 2538 case MCK_GR64_TC: return true; 2539 case MCK_GR64: return true; 2540 } 2541 2542 case MCK_Reg38: 2543 switch (B) { 2544 default: return false; 2545 case MCK_GR64_NOREX: return true; 2546 case MCK_GR64_TC: return true; 2547 case MCK_GR64: return true; 2548 } 2549 2550 case MCK_GR64_NOSP: 2551 switch (B) { 2552 default: return false; 2553 case MCK_Reg31: return true; 2554 case MCK_GR64: return true; 2555 } 2556 2557 case MCK_GR64_TC: 2558 return B == MCK_GR64; 2559 2560 case MCK_ST0: 2561 return B == MCK_RST; 2562 2563 case MCK_CS: 2564 return B == MCK_SEGMENT_REG; 2565 2566 case MCK_DS: 2567 return B == MCK_SEGMENT_REG; 2568 2569 case MCK_SS: 2570 return B == MCK_SEGMENT_REG; 2571 2572 case MCK_ES: 2573 return B == MCK_SEGMENT_REG; 2574 2575 case MCK_FS: 2576 return B == MCK_SEGMENT_REG; 2577 2578 case MCK_GS: 2579 return B == MCK_SEGMENT_REG; 2580 2581 case MCK_ImmSExti64i8: 2582 switch (B) { 2583 default: return false; 2584 case MCK_ImmSExti16i8: return true; 2585 case MCK_ImmSExti32i8: return true; 2586 case MCK_ImmSExti64i32: return true; 2587 case MCK_Imm: return true; 2588 } 2589 2590 case MCK_ImmSExti16i8: 2591 switch (B) { 2592 default: return false; 2593 case MCK_ImmSExti64i32: return true; 2594 case MCK_Imm: return true; 2595 } 2596 2597 case MCK_ImmSExti32i8: 2598 return B == MCK_Imm; 2599 2600 case MCK_ImmSExti64i32: 2601 return B == MCK_Imm; 2602 2603 case MCK_ImmZExtu32u8: 2604 return B == MCK_Imm; 2605 2606 case MCK_AbsMem: 2607 return B == MCK_Mem; 2608 } 2609} 2610 2611static bool ValidateOperandClass(MCParsedAsmOperand *GOp, MatchClassKind Kind) { 2612 X86Operand &Operand = *(X86Operand*)GOp; 2613 if (Kind == InvalidMatchClass) 2614 return false; 2615 2616 if (Operand.isToken()) 2617 return MatchTokenString(Operand.getToken()) == Kind; 2618 2619 if (Operand.isReg()) { 2620 MatchClassKind OpKind; 2621 switch (Operand.getReg()) { 2622 default: OpKind = InvalidMatchClass; break; 2623 case X86::AL: OpKind = MCK_AL; break; 2624 case X86::DL: OpKind = MCK_GR8_ABCD_L; break; 2625 case X86::CL: OpKind = MCK_CL; break; 2626 case X86::BL: OpKind = MCK_GR8_ABCD_L; break; 2627 case X86::SIL: OpKind = MCK_GR8; break; 2628 case X86::DIL: OpKind = MCK_GR8; break; 2629 case X86::BPL: OpKind = MCK_GR8; break; 2630 case X86::SPL: OpKind = MCK_GR8; break; 2631 case X86::R8B: OpKind = MCK_GR8; break; 2632 case X86::R9B: OpKind = MCK_GR8; break; 2633 case X86::R10B: OpKind = MCK_GR8; break; 2634 case X86::R11B: OpKind = MCK_GR8; break; 2635 case X86::R12B: OpKind = MCK_GR8; break; 2636 case X86::R13B: OpKind = MCK_GR8; break; 2637 case X86::R14B: OpKind = MCK_GR8; break; 2638 case X86::R15B: OpKind = MCK_GR8; break; 2639 case X86::AH: OpKind = MCK_GR8_ABCD_H; break; 2640 case X86::DH: OpKind = MCK_GR8_ABCD_H; break; 2641 case X86::CH: OpKind = MCK_GR8_ABCD_H; break; 2642 case X86::BH: OpKind = MCK_GR8_ABCD_H; break; 2643 case X86::AX: OpKind = MCK_AX; break; 2644 case X86::DX: OpKind = MCK_DX; break; 2645 case X86::CX: OpKind = MCK_GR16_ABCD; break; 2646 case X86::BX: OpKind = MCK_GR16_ABCD; break; 2647 case X86::SI: OpKind = MCK_GR16_NOREX; break; 2648 case X86::DI: OpKind = MCK_GR16_NOREX; break; 2649 case X86::BP: OpKind = MCK_GR16_NOREX; break; 2650 case X86::SP: OpKind = MCK_GR16_NOREX; break; 2651 case X86::R8W: OpKind = MCK_GR16; break; 2652 case X86::R9W: OpKind = MCK_GR16; break; 2653 case X86::R10W: OpKind = MCK_GR16; break; 2654 case X86::R11W: OpKind = MCK_GR16; break; 2655 case X86::R12W: OpKind = MCK_GR16; break; 2656 case X86::R13W: OpKind = MCK_GR16; break; 2657 case X86::R14W: OpKind = MCK_GR16; break; 2658 case X86::R15W: OpKind = MCK_GR16; break; 2659 case X86::EAX: OpKind = MCK_EAX; break; 2660 case X86::EDX: OpKind = MCK_EDX; break; 2661 case X86::ECX: OpKind = MCK_ECX; break; 2662 case X86::EBX: OpKind = MCK_Reg20; break; 2663 case X86::ESI: OpKind = MCK_Reg21; break; 2664 case X86::EDI: OpKind = MCK_Reg21; break; 2665 case X86::EBP: OpKind = MCK_Reg21; break; 2666 case X86::ESP: OpKind = MCK_Reg22; break; 2667 case X86::R8D: OpKind = MCK_Reg24; break; 2668 case X86::R9D: OpKind = MCK_Reg24; break; 2669 case X86::R10D: OpKind = MCK_Reg24; break; 2670 case X86::R11D: OpKind = MCK_Reg24; break; 2671 case X86::R12D: OpKind = MCK_Reg24; break; 2672 case X86::R13D: OpKind = MCK_Reg24; break; 2673 case X86::R14D: OpKind = MCK_Reg24; break; 2674 case X86::R15D: OpKind = MCK_Reg24; break; 2675 case X86::RAX: OpKind = MCK_RAX; break; 2676 case X86::RDX: OpKind = MCK_RDX; break; 2677 case X86::RCX: OpKind = MCK_RCX; break; 2678 case X86::RBX: OpKind = MCK_GR64_ABCD; break; 2679 case X86::RSI: OpKind = MCK_Reg35; break; 2680 case X86::RDI: OpKind = MCK_Reg35; break; 2681 case X86::RBP: OpKind = MCK_GR64_NOREX_NOSP; break; 2682 case X86::RSP: OpKind = MCK_Reg30; break; 2683 case X86::R8: OpKind = MCK_GR64_TCW64; break; 2684 case X86::R9: OpKind = MCK_GR64_TCW64; break; 2685 case X86::R10: OpKind = MCK_GR64_NOSP; break; 2686 case X86::R11: OpKind = MCK_GR64_TCW64; break; 2687 case X86::R12: OpKind = MCK_GR64_NOSP; break; 2688 case X86::R13: OpKind = MCK_GR64_NOSP; break; 2689 case X86::R14: OpKind = MCK_GR64_NOSP; break; 2690 case X86::R15: OpKind = MCK_GR64_NOSP; break; 2691 case X86::RIP: OpKind = MCK_Reg38; break; 2692 case X86::MM0: OpKind = MCK_VR64; break; 2693 case X86::MM1: OpKind = MCK_VR64; break; 2694 case X86::MM2: OpKind = MCK_VR64; break; 2695 case X86::MM3: OpKind = MCK_VR64; break; 2696 case X86::MM4: OpKind = MCK_VR64; break; 2697 case X86::MM5: OpKind = MCK_VR64; break; 2698 case X86::MM6: OpKind = MCK_VR64; break; 2699 case X86::MM7: OpKind = MCK_VR64; break; 2700 case X86::FP0: OpKind = MCK_RFP32; break; 2701 case X86::FP1: OpKind = MCK_RFP32; break; 2702 case X86::FP2: OpKind = MCK_RFP32; break; 2703 case X86::FP3: OpKind = MCK_RFP32; break; 2704 case X86::FP4: OpKind = MCK_RFP32; break; 2705 case X86::FP5: OpKind = MCK_RFP32; break; 2706 case X86::FP6: OpKind = MCK_RFP32; break; 2707 case X86::XMM0: OpKind = MCK_FR32; break; 2708 case X86::XMM1: OpKind = MCK_FR32; break; 2709 case X86::XMM2: OpKind = MCK_FR32; break; 2710 case X86::XMM3: OpKind = MCK_FR32; break; 2711 case X86::XMM4: OpKind = MCK_FR32; break; 2712 case X86::XMM5: OpKind = MCK_FR32; break; 2713 case X86::XMM6: OpKind = MCK_FR32; break; 2714 case X86::XMM7: OpKind = MCK_FR32; break; 2715 case X86::XMM8: OpKind = MCK_FR32; break; 2716 case X86::XMM9: OpKind = MCK_FR32; break; 2717 case X86::XMM10: OpKind = MCK_FR32; break; 2718 case X86::XMM11: OpKind = MCK_FR32; break; 2719 case X86::XMM12: OpKind = MCK_FR32; break; 2720 case X86::XMM13: OpKind = MCK_FR32; break; 2721 case X86::XMM14: OpKind = MCK_FR32; break; 2722 case X86::XMM15: OpKind = MCK_FR32; break; 2723 case X86::YMM0: OpKind = MCK_VR256; break; 2724 case X86::YMM1: OpKind = MCK_VR256; break; 2725 case X86::YMM2: OpKind = MCK_VR256; break; 2726 case X86::YMM3: OpKind = MCK_VR256; break; 2727 case X86::YMM4: OpKind = MCK_VR256; break; 2728 case X86::YMM5: OpKind = MCK_VR256; break; 2729 case X86::YMM6: OpKind = MCK_VR256; break; 2730 case X86::YMM7: OpKind = MCK_VR256; break; 2731 case X86::YMM8: OpKind = MCK_VR256; break; 2732 case X86::YMM9: OpKind = MCK_VR256; break; 2733 case X86::YMM10: OpKind = MCK_VR256; break; 2734 case X86::YMM11: OpKind = MCK_VR256; break; 2735 case X86::YMM12: OpKind = MCK_VR256; break; 2736 case X86::YMM13: OpKind = MCK_VR256; break; 2737 case X86::YMM14: OpKind = MCK_VR256; break; 2738 case X86::YMM15: OpKind = MCK_VR256; break; 2739 case X86::ST0: OpKind = MCK_ST0; break; 2740 case X86::ST1: OpKind = MCK_RST; break; 2741 case X86::ST2: OpKind = MCK_RST; break; 2742 case X86::ST3: OpKind = MCK_RST; break; 2743 case X86::ST4: OpKind = MCK_RST; break; 2744 case X86::ST5: OpKind = MCK_RST; break; 2745 case X86::ST6: OpKind = MCK_RST; break; 2746 case X86::ST7: OpKind = MCK_RST; break; 2747 case X86::EFLAGS: OpKind = MCK_CCR; break; 2748 case X86::CS: OpKind = MCK_CS; break; 2749 case X86::DS: OpKind = MCK_DS; break; 2750 case X86::SS: OpKind = MCK_SS; break; 2751 case X86::ES: OpKind = MCK_ES; break; 2752 case X86::FS: OpKind = MCK_FS; break; 2753 case X86::GS: OpKind = MCK_GS; break; 2754 case X86::DR0: OpKind = MCK_DEBUG_REG; break; 2755 case X86::DR1: OpKind = MCK_DEBUG_REG; break; 2756 case X86::DR2: OpKind = MCK_DEBUG_REG; break; 2757 case X86::DR3: OpKind = MCK_DEBUG_REG; break; 2758 case X86::DR4: OpKind = MCK_DEBUG_REG; break; 2759 case X86::DR5: OpKind = MCK_DEBUG_REG; break; 2760 case X86::DR6: OpKind = MCK_DEBUG_REG; break; 2761 case X86::DR7: OpKind = MCK_DEBUG_REG; break; 2762 case X86::CR0: OpKind = MCK_CONTROL_REG; break; 2763 case X86::CR1: OpKind = MCK_CONTROL_REG; break; 2764 case X86::CR2: OpKind = MCK_CONTROL_REG; break; 2765 case X86::CR3: OpKind = MCK_CONTROL_REG; break; 2766 case X86::CR4: OpKind = MCK_CONTROL_REG; break; 2767 case X86::CR5: OpKind = MCK_CONTROL_REG; break; 2768 case X86::CR6: OpKind = MCK_CONTROL_REG; break; 2769 case X86::CR7: OpKind = MCK_CONTROL_REG; break; 2770 case X86::CR8: OpKind = MCK_CONTROL_REG; break; 2771 case X86::CR9: OpKind = MCK_CONTROL_REG; break; 2772 case X86::CR10: OpKind = MCK_CONTROL_REG; break; 2773 case X86::CR11: OpKind = MCK_CONTROL_REG; break; 2774 case X86::CR12: OpKind = MCK_CONTROL_REG; break; 2775 case X86::CR13: OpKind = MCK_CONTROL_REG; break; 2776 case X86::CR14: OpKind = MCK_CONTROL_REG; break; 2777 case X86::CR15: OpKind = MCK_CONTROL_REG; break; 2778 } 2779 return IsSubclass(OpKind, Kind); 2780 } 2781 2782 // 'ImmSExti64i8' class 2783 if (Kind == MCK_ImmSExti64i8 && Operand.isImmSExti64i8()) { 2784 return true; 2785 } 2786 2787 // 'ImmSExti16i8' class 2788 if (Kind == MCK_ImmSExti16i8 && Operand.isImmSExti16i8()) { 2789 return true; 2790 } 2791 2792 // 'ImmSExti32i8' class 2793 if (Kind == MCK_ImmSExti32i8 && Operand.isImmSExti32i8()) { 2794 return true; 2795 } 2796 2797 // 'ImmSExti64i32' class 2798 if (Kind == MCK_ImmSExti64i32 && Operand.isImmSExti64i32()) { 2799 return true; 2800 } 2801 2802 // 'ImmZExtu32u8' class 2803 if (Kind == MCK_ImmZExtu32u8 && Operand.isImmZExtu32u8()) { 2804 return true; 2805 } 2806 2807 // 'Imm' class 2808 if (Kind == MCK_Imm && Operand.isImm()) { 2809 return true; 2810 } 2811 2812 // 'AbsMem' class 2813 if (Kind == MCK_AbsMem && Operand.isAbsMem()) { 2814 return true; 2815 } 2816 2817 // 'Mem' class 2818 if (Kind == MCK_Mem && Operand.isMem()) { 2819 return true; 2820 } 2821 2822 return false; 2823} 2824 2825unsigned X86ATTAsmParser:: 2826ComputeAvailableFeatures(uint64_t FB) const { 2827 unsigned Features = 0; 2828 if (((FB & X86::Mode64Bit) == 0)) 2829 Features |= Feature_In32BitMode; 2830 if (((FB & X86::Mode64Bit) != 0)) 2831 Features |= Feature_In64BitMode; 2832 if (((FB & X86::ModeNaCl) != 0)) 2833 Features |= Feature_IsNaCl; 2834 if (((FB & X86::ModeNaCl) != 0) && ((FB & X86::Mode64Bit) == 0)) 2835 Features |= Feature_IsNaCl32; 2836 if (((FB & X86::ModeNaCl) != 0) && ((FB & X86::Mode64Bit) != 0)) 2837 Features |= Feature_IsNaCl64; 2838 if (((FB & X86::ModeNaCl) == 0)) 2839 Features |= Feature_NotNaCl; 2840 return Features; 2841} 2842 2843namespace { 2844 struct MatchEntry { 2845 unsigned Opcode; 2846 const char *Mnemonic; 2847 ConversionKind ConvertFn; 2848 MatchClassKind Classes[5]; 2849 unsigned RequiredFeatures; 2850 }; 2851 2852 // Predicate for searching for an opcode. 2853 struct LessOpcode { 2854 bool operator()(const MatchEntry &LHS, StringRef RHS) { 2855 return StringRef(LHS.Mnemonic) < RHS; 2856 } 2857 bool operator()(StringRef LHS, const MatchEntry &RHS) { 2858 return LHS < StringRef(RHS.Mnemonic); 2859 } 2860 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { 2861 return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic); 2862 } 2863 }; 2864} // end anonymous namespace. 2865 2866static const MatchEntry MatchTable[3300] = { 2867 { X86::AAA, "aaa", Convert, { }, Feature_In32BitMode}, 2868 { X86::AAD8i8, "aad", Convert__imm10, { }, 0}, 2869 { X86::AAD8i8, "aad", Convert__Imm1_0, { MCK_Imm }, Feature_In32BitMode}, 2870 { X86::AAM8i8, "aam", Convert__imm10, { }, 0}, 2871 { X86::AAM8i8, "aam", Convert__Imm1_0, { MCK_Imm }, Feature_In32BitMode}, 2872 { X86::AAS, "aas", Convert, { }, Feature_In32BitMode}, 2873 { X86::ADC8rr, "adcb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 2874 { X86::ADC8mr, "adcb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 2875 { X86::ADC8i8, "adcb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 2876 { X86::ADC8ri, "adcb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 2877 { X86::ADC8mi, "adcb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 2878 { X86::ADC8rm, "adcb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 2879 { X86::ADC32rr, "adcl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 2880 { X86::ADC32mr, "adcl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 2881 { X86::ADC32ri8, "adcl", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 2882 { X86::ADC32mi8, "adcl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 2883 { X86::ADC32i32, "adcl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 2884 { X86::ADC32ri, "adcl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 2885 { X86::ADC32mi, "adcl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 2886 { X86::ADC32rm, "adcl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 2887 { X86::ADC64rr, "adcq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 2888 { X86::ADC64mr, "adcq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 2889 { X86::ADC64ri8, "adcq", Convert__Reg1_1__Tie0__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 2890 { X86::ADC64mi8, "adcq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 2891 { X86::ADC64i32, "adcq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_RAX }, 0}, 2892 { X86::ADC64ri32, "adcq", Convert__Reg1_1__Tie0__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 2893 { X86::ADC64mi32, "adcq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 2894 { X86::ADC64rm, "adcq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 2895 { X86::ADC16rr, "adcw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 2896 { X86::ADC16mr, "adcw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 2897 { X86::ADC16ri8, "adcw", Convert__Reg1_1__Tie0__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 2898 { X86::ADC16mi8, "adcw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 2899 { X86::ADC16i16, "adcw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 2900 { X86::ADC16ri, "adcw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 2901 { X86::ADC16mi, "adcw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 2902 { X86::ADC16rm, "adcw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 2903 { X86::ADD8rr, "addb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 2904 { X86::ADD8mr, "addb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 2905 { X86::ADD8i8, "addb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 2906 { X86::ADD8ri, "addb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 2907 { X86::ADD8mi, "addb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 2908 { X86::ADD8rm, "addb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 2909 { X86::ADD32rr, "addl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 2910 { X86::ADD32mr, "addl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 2911 { X86::ADD32ri8, "addl", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 2912 { X86::ADD32mi8, "addl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 2913 { X86::ADD32i32, "addl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 2914 { X86::ADD32ri, "addl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 2915 { X86::ADD32mi, "addl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 2916 { X86::ADD32rm, "addl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 2917 { X86::ADDPDrr, "addpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2918 { X86::ADDPDrm, "addpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2919 { X86::ADDPSrr, "addps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2920 { X86::ADDPSrm, "addps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2921 { X86::ADD64rr, "addq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 2922 { X86::ADD64mr, "addq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 2923 { X86::ADD64ri8, "addq", Convert__Reg1_1__Tie0__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 2924 { X86::ADD64mi8, "addq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 2925 { X86::ADD64i32, "addq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_RAX }, 0}, 2926 { X86::ADD64ri32, "addq", Convert__Reg1_1__Tie0__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 2927 { X86::ADD64mi32, "addq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 2928 { X86::ADD64rm, "addq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 2929 { X86::ADDSDrr, "addsd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2930 { X86::ADDSDrm, "addsd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2931 { X86::ADDSSrr, "addss", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2932 { X86::ADDSSrm, "addss", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2933 { X86::ADDSUBPDrr, "addsubpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2934 { X86::ADDSUBPDrm, "addsubpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2935 { X86::ADDSUBPSrr, "addsubps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2936 { X86::ADDSUBPSrm, "addsubps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2937 { X86::ADD16rr, "addw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 2938 { X86::ADD16mr, "addw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 2939 { X86::ADD16ri8, "addw", Convert__Reg1_1__Tie0__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 2940 { X86::ADD16mi8, "addw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 2941 { X86::ADD16i16, "addw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 2942 { X86::ADD16ri, "addw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 2943 { X86::ADD16mi, "addw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 2944 { X86::ADD16rm, "addw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 2945 { X86::AESDECrr, "aesdec", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2946 { X86::AESDECrm, "aesdec", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2947 { X86::AESDECLASTrr, "aesdeclast", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2948 { X86::AESDECLASTrm, "aesdeclast", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2949 { X86::AESENCrr, "aesenc", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2950 { X86::AESENCrm, "aesenc", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2951 { X86::AESENCLASTrr, "aesenclast", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2952 { X86::AESENCLASTrm, "aesenclast", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2953 { X86::AESIMCrr, "aesimc", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2954 { X86::AESIMCrm, "aesimc", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2955 { X86::AESKEYGENASSIST128rr, "aeskeygenassist", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 2956 { X86::AESKEYGENASSIST128rm, "aeskeygenassist", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 2957 { X86::AND8rr, "andb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 2958 { X86::AND8mr, "andb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 2959 { X86::AND8i8, "andb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 2960 { X86::AND8ri, "andb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 2961 { X86::AND8mi, "andb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 2962 { X86::AND8rm, "andb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 2963 { X86::AND32rr, "andl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 2964 { X86::AND32mr, "andl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 2965 { X86::AND32ri8, "andl", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 2966 { X86::AND32mi8, "andl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 2967 { X86::AND32i32, "andl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 2968 { X86::AND32ri, "andl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 2969 { X86::AND32mi, "andl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 2970 { X86::AND32rm, "andl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 2971 { X86::ANDN32rr, "andnl", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32, MCK_GR32 }, 0}, 2972 { X86::ANDN32rm, "andnl", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32, MCK_GR32 }, 0}, 2973 { X86::ANDNPDrr, "andnpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2974 { X86::FsANDNPDrr, "andnpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2975 { X86::ANDNPDrm, "andnpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2976 { X86::FsANDNPDrm, "andnpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2977 { X86::ANDNPSrr, "andnps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2978 { X86::FsANDNPSrr, "andnps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2979 { X86::ANDNPSrm, "andnps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2980 { X86::FsANDNPSrm, "andnps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2981 { X86::ANDN64rr, "andnq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64, MCK_GR64 }, 0}, 2982 { X86::ANDN64rm, "andnq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64, MCK_GR64 }, 0}, 2983 { X86::ANDPDrr, "andpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2984 { X86::FsANDPDrr, "andpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2985 { X86::ANDPDrm, "andpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2986 { X86::FsANDPDrm, "andpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2987 { X86::ANDPSrr, "andps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2988 { X86::FsANDPSrr, "andps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 2989 { X86::ANDPSrm, "andps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2990 { X86::FsANDPSrm, "andps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 2991 { X86::AND64rr, "andq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 2992 { X86::AND64mr, "andq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 2993 { X86::AND64ri8, "andq", Convert__Reg1_1__Tie0__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 2994 { X86::AND64mi8, "andq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 2995 { X86::AND64i32, "andq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_RAX }, 0}, 2996 { X86::AND64ri32, "andq", Convert__Reg1_1__Tie0__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 2997 { X86::AND64mi32, "andq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 2998 { X86::AND64rm, "andq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 2999 { X86::AND16rr, "andw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3000 { X86::AND16mr, "andw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 3001 { X86::AND16ri8, "andw", Convert__Reg1_1__Tie0__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 3002 { X86::AND16mi8, "andw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 3003 { X86::AND16i16, "andw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 3004 { X86::AND16ri, "andw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 3005 { X86::AND16mi, "andw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 3006 { X86::AND16rm, "andw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3007 { X86::ARPL16rr, "arpl", Convert__Reg1_0__Reg1_1, { MCK_GR16, MCK_GR16 }, Feature_In32BitMode}, 3008 { X86::ARPL16mr, "arpl", Convert__Reg1_0__Mem5_1, { MCK_GR16, MCK_Mem }, Feature_In32BitMode}, 3009 { X86::BLENDPDrri, "blendpd", Convert__Reg1_2__Tie0__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32 }, 0}, 3010 { X86::BLENDPDrmi, "blendpd", Convert__Reg1_2__Tie0__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32 }, 0}, 3011 { X86::BLENDPSrri, "blendps", Convert__Reg1_2__Tie0__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32 }, 0}, 3012 { X86::BLENDPSrmi, "blendps", Convert__Reg1_2__Tie0__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32 }, 0}, 3013 { X86::BLENDVPDrr0, "blendvpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3014 { X86::BLENDVPDrm0, "blendvpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3015 { X86::BLENDVPSrr0, "blendvps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3016 { X86::BLENDVPSrm0, "blendvps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3017 { X86::BOUNDS16rm, "bound", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, Feature_In32BitMode}, 3018 { X86::BOUNDS32rm, "bound", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, Feature_In32BitMode}, 3019 { X86::BSF32rr, "bsfl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3020 { X86::BSF32rm, "bsfl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3021 { X86::BSF64rr, "bsfq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3022 { X86::BSF64rm, "bsfq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3023 { X86::BSF16rr, "bsfw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3024 { X86::BSF16rm, "bsfw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3025 { X86::BSR32rr, "bsrl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3026 { X86::BSR32rm, "bsrl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3027 { X86::BSR64rr, "bsrq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3028 { X86::BSR64rm, "bsrq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3029 { X86::BSR16rr, "bsrw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3030 { X86::BSR16rm, "bsrw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3031 { X86::BSWAP32r, "bswapl", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 3032 { X86::BSWAP64r, "bswapq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 3033 { X86::BT32mi8, "bt", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 3034 { X86::BTC32rr, "btcl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3035 { X86::BTC32mr, "btcl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 3036 { X86::BTC32ri8, "btcl", Convert__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 3037 { X86::BTC32mi8, "btcl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 3038 { X86::BTC64rr, "btcq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3039 { X86::BTC64mr, "btcq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 3040 { X86::BTC64ri8, "btcq", Convert__Reg1_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 3041 { X86::BTC64mi8, "btcq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 3042 { X86::BTC16rr, "btcw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3043 { X86::BTC16mr, "btcw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 3044 { X86::BTC16ri8, "btcw", Convert__Reg1_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 3045 { X86::BTC16mi8, "btcw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 3046 { X86::BT32rr, "btl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3047 { X86::BT32mr, "btl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 3048 { X86::BT32ri8, "btl", Convert__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 3049 { X86::BT32mi8, "btl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 3050 { X86::BT64rr, "btq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3051 { X86::BT64mr, "btq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 3052 { X86::BT64ri8, "btq", Convert__Reg1_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 3053 { X86::BT64mi8, "btq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 3054 { X86::BTR32rr, "btrl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3055 { X86::BTR32mr, "btrl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 3056 { X86::BTR32ri8, "btrl", Convert__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 3057 { X86::BTR32mi8, "btrl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 3058 { X86::BTR64rr, "btrq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3059 { X86::BTR64mr, "btrq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 3060 { X86::BTR64ri8, "btrq", Convert__Reg1_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 3061 { X86::BTR64mi8, "btrq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 3062 { X86::BTR16rr, "btrw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3063 { X86::BTR16mr, "btrw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 3064 { X86::BTR16ri8, "btrw", Convert__Reg1_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 3065 { X86::BTR16mi8, "btrw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 3066 { X86::BTS32rr, "btsl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3067 { X86::BTS32mr, "btsl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 3068 { X86::BTS32ri8, "btsl", Convert__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 3069 { X86::BTS32mi8, "btsl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 3070 { X86::BTS64rr, "btsq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3071 { X86::BTS64mr, "btsq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 3072 { X86::BTS64ri8, "btsq", Convert__Reg1_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 3073 { X86::BTS64mi8, "btsq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 3074 { X86::BTS16rr, "btsw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3075 { X86::BTS16mr, "btsw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 3076 { X86::BTS16ri8, "btsw", Convert__Reg1_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 3077 { X86::BTS16mi8, "btsw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 3078 { X86::BT16rr, "btw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3079 { X86::BT16mr, "btw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 3080 { X86::BT16ri8, "btw", Convert__Reg1_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 3081 { X86::BT16mi8, "btw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 3082 { X86::FARCALL32i, "call", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3083 { X86::CALLpcrel32, "calll", Convert__AbsMem1_0, { MCK_AbsMem }, Feature_In32BitMode}, 3084 { X86::CALL32r, "calll", Convert__Reg1_1, { MCK__STAR_, MCK_GR32 }, Feature_In32BitMode}, 3085 { X86::CALL32m, "calll", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, Feature_In32BitMode}, 3086 { X86::FARCALL32i, "calll", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3087 { X86::CALL64pcrel32, "callq", Convert__AbsMem1_0, { MCK_AbsMem }, Feature_In64BitMode}, 3088 { X86::CALL64r, "callq", Convert__Reg1_1, { MCK__STAR_, MCK_GR64 }, Feature_In64BitMode}, 3089 { X86::CALL64m, "callq", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, Feature_In64BitMode}, 3090 { X86::CALLpcrel16, "callw", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3091 { X86::FARCALL16i, "callw", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3092 { X86::CBW, "cbtw", Convert, { }, 0}, 3093 { X86::CLC, "clc", Convert, { }, 0}, 3094 { X86::CLD, "cld", Convert, { }, 0}, 3095 { X86::CLFLUSH, "clflush", Convert__Mem5_0, { MCK_Mem }, 0}, 3096 { X86::CLI, "cli", Convert, { }, 0}, 3097 { X86::XOR8rr, "clrb", Convert__Reg1_0__Tie0__Reg1_0, { MCK_GR8 }, 0}, 3098 { X86::XOR32rr, "clrl", Convert__Reg1_0__Tie0__Reg1_0, { MCK_GR32 }, 0}, 3099 { X86::XOR64rr, "clrq", Convert__Reg1_0__Tie0__Reg1_0, { MCK_GR64 }, 0}, 3100 { X86::XOR16rr, "clrw", Convert__Reg1_0__Tie0__Reg1_0, { MCK_GR16 }, 0}, 3101 { X86::CDQ, "cltd", Convert, { }, 0}, 3102 { X86::CDQE, "cltq", Convert, { }, 0}, 3103 { X86::CLTS, "clts", Convert, { }, 0}, 3104 { X86::CMC, "cmc", Convert, { }, 0}, 3105 { X86::CMOVAE32rr, "cmovael", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3106 { X86::CMOVAE32rm, "cmovael", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3107 { X86::CMOVAE64rr, "cmovaeq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3108 { X86::CMOVAE64rm, "cmovaeq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3109 { X86::CMOVAE16rr, "cmovaew", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3110 { X86::CMOVAE16rm, "cmovaew", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3111 { X86::CMOVA32rr, "cmoval", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3112 { X86::CMOVA32rm, "cmoval", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3113 { X86::CMOVA64rr, "cmovaq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3114 { X86::CMOVA64rm, "cmovaq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3115 { X86::CMOVA16rr, "cmovaw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3116 { X86::CMOVA16rm, "cmovaw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3117 { X86::CMOVBE32rr, "cmovbel", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3118 { X86::CMOVBE32rm, "cmovbel", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3119 { X86::CMOVBE64rr, "cmovbeq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3120 { X86::CMOVBE64rm, "cmovbeq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3121 { X86::CMOVBE16rr, "cmovbew", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3122 { X86::CMOVBE16rm, "cmovbew", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3123 { X86::CMOVB32rr, "cmovbl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3124 { X86::CMOVB32rm, "cmovbl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3125 { X86::CMOVB64rr, "cmovbq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3126 { X86::CMOVB64rm, "cmovbq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3127 { X86::CMOVB16rr, "cmovbw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3128 { X86::CMOVB16rm, "cmovbw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3129 { X86::CMOVE32rr, "cmovel", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3130 { X86::CMOVE32rm, "cmovel", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3131 { X86::CMOVE64rr, "cmoveq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3132 { X86::CMOVE64rm, "cmoveq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3133 { X86::CMOVE16rr, "cmovew", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3134 { X86::CMOVE16rm, "cmovew", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3135 { X86::CMOVGE32rr, "cmovgel", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3136 { X86::CMOVGE32rm, "cmovgel", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3137 { X86::CMOVGE64rr, "cmovgeq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3138 { X86::CMOVGE64rm, "cmovgeq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3139 { X86::CMOVGE16rr, "cmovgew", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3140 { X86::CMOVGE16rm, "cmovgew", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3141 { X86::CMOVG32rr, "cmovgl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3142 { X86::CMOVG32rm, "cmovgl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3143 { X86::CMOVG64rr, "cmovgq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3144 { X86::CMOVG64rm, "cmovgq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3145 { X86::CMOVG16rr, "cmovgw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3146 { X86::CMOVG16rm, "cmovgw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3147 { X86::CMOVLE32rr, "cmovlel", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3148 { X86::CMOVLE32rm, "cmovlel", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3149 { X86::CMOVLE64rr, "cmovleq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3150 { X86::CMOVLE64rm, "cmovleq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3151 { X86::CMOVLE16rr, "cmovlew", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3152 { X86::CMOVLE16rm, "cmovlew", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3153 { X86::CMOVL32rr, "cmovll", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3154 { X86::CMOVL32rm, "cmovll", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3155 { X86::CMOVL64rr, "cmovlq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3156 { X86::CMOVL64rm, "cmovlq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3157 { X86::CMOVL16rr, "cmovlw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3158 { X86::CMOVL16rm, "cmovlw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3159 { X86::CMOVNE32rr, "cmovnel", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3160 { X86::CMOVNE32rm, "cmovnel", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3161 { X86::CMOVNE64rr, "cmovneq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3162 { X86::CMOVNE64rm, "cmovneq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3163 { X86::CMOVNE16rr, "cmovnew", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3164 { X86::CMOVNE16rm, "cmovnew", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3165 { X86::CMOVNO32rr, "cmovnol", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3166 { X86::CMOVNO32rm, "cmovnol", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3167 { X86::CMOVNO64rr, "cmovnoq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3168 { X86::CMOVNO64rm, "cmovnoq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3169 { X86::CMOVNO16rr, "cmovnow", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3170 { X86::CMOVNO16rm, "cmovnow", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3171 { X86::CMOVNP32rr, "cmovnpl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3172 { X86::CMOVNP32rm, "cmovnpl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3173 { X86::CMOVNP64rr, "cmovnpq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3174 { X86::CMOVNP64rm, "cmovnpq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3175 { X86::CMOVNP16rr, "cmovnpw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3176 { X86::CMOVNP16rm, "cmovnpw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3177 { X86::CMOVNS32rr, "cmovnsl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3178 { X86::CMOVNS32rm, "cmovnsl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3179 { X86::CMOVNS64rr, "cmovnsq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3180 { X86::CMOVNS64rm, "cmovnsq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3181 { X86::CMOVNS16rr, "cmovnsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3182 { X86::CMOVNS16rm, "cmovnsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3183 { X86::CMOVO32rr, "cmovol", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3184 { X86::CMOVO32rm, "cmovol", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3185 { X86::CMOVO64rr, "cmovoq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3186 { X86::CMOVO64rm, "cmovoq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3187 { X86::CMOVO16rr, "cmovow", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3188 { X86::CMOVO16rm, "cmovow", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3189 { X86::CMOVP32rr, "cmovpl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3190 { X86::CMOVP32rm, "cmovpl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3191 { X86::CMOVP64rr, "cmovpq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3192 { X86::CMOVP64rm, "cmovpq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3193 { X86::CMOVP16rr, "cmovpw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3194 { X86::CMOVP16rm, "cmovpw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3195 { X86::CMOVS32rr, "cmovsl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3196 { X86::CMOVS32rm, "cmovsl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3197 { X86::CMOVS64rr, "cmovsq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3198 { X86::CMOVS64rm, "cmovsq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3199 { X86::CMOVS16rr, "cmovsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3200 { X86::CMOVS16rm, "cmovsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3201 { X86::CMPPDrri, "cmp", Convert__Reg1_3__Tie0__Reg1_2__Imm1_0, { MCK_Imm, MCK_pd, MCK_FR32, MCK_FR32 }, 0}, 3202 { X86::CMPPDrmi, "cmp", Convert__Reg1_3__Tie0__Mem5_2__Imm1_0, { MCK_Imm, MCK_pd, MCK_Mem, MCK_FR32 }, 0}, 3203 { X86::CMPPSrri, "cmp", Convert__Reg1_3__Tie0__Reg1_2__Imm1_0, { MCK_Imm, MCK_ps, MCK_FR32, MCK_FR32 }, 0}, 3204 { X86::CMPPSrmi, "cmp", Convert__Reg1_3__Tie0__Mem5_2__Imm1_0, { MCK_Imm, MCK_ps, MCK_Mem, MCK_FR32 }, 0}, 3205 { X86::CMPSDrr, "cmp", Convert__Reg1_3__Tie0__Reg1_2__Imm1_0, { MCK_Imm, MCK_sd, MCK_FR32, MCK_FR32 }, 0}, 3206 { X86::CMPSDrm, "cmp", Convert__Reg1_3__Tie0__Mem5_2__Imm1_0, { MCK_Imm, MCK_sd, MCK_Mem, MCK_FR32 }, 0}, 3207 { X86::CMPSSrr, "cmp", Convert__Reg1_3__Tie0__Reg1_2__Imm1_0, { MCK_Imm, MCK_ss, MCK_FR32, MCK_FR32 }, 0}, 3208 { X86::CMPSSrm, "cmp", Convert__Reg1_3__Tie0__Mem5_2__Imm1_0, { MCK_Imm, MCK_ss, MCK_Mem, MCK_FR32 }, 0}, 3209 { X86::CMP8rr, "cmpb", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 3210 { X86::CMP8mr, "cmpb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 3211 { X86::CMP8i8, "cmpb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 3212 { X86::CMP8ri, "cmpb", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 3213 { X86::CMP8mi, "cmpb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 3214 { X86::CMP8rm, "cmpb", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 3215 { X86::CMP32rr, "cmpl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3216 { X86::CMP32mr, "cmpl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 3217 { X86::CMP32ri8, "cmpl", Convert__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 3218 { X86::CMP32mi8, "cmpl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 3219 { X86::CMP32i32, "cmpl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 3220 { X86::CMP32ri, "cmpl", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 3221 { X86::CMP32mi, "cmpl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 3222 { X86::CMP32rm, "cmpl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3223 { X86::CMPPDrri_alt, "cmppd", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 3224 { X86::CMPPDrmi_alt, "cmppd", Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 3225 { X86::CMPPSrri_alt, "cmpps", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 3226 { X86::CMPPSrmi_alt, "cmpps", Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 3227 { X86::CMP64rr, "cmpq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3228 { X86::CMP64mr, "cmpq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 3229 { X86::CMP64ri8, "cmpq", Convert__Reg1_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 3230 { X86::CMP64mi8, "cmpq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 3231 { X86::CMP64i32, "cmpq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_RAX }, 0}, 3232 { X86::CMP64ri32, "cmpq", Convert__Reg1_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 3233 { X86::CMP64mi32, "cmpq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 3234 { X86::CMP64rm, "cmpq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3235 { X86::CMPS8, "cmpsb", Convert, { }, 0}, 3236 { X86::CMPSDrr_alt, "cmpsd", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 3237 { X86::CMPSDrm_alt, "cmpsd", Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 3238 { X86::CMPS32, "cmpsl", Convert, { }, 0}, 3239 { X86::CMPS64, "cmpsq", Convert, { }, 0}, 3240 { X86::CMPSSrr_alt, "cmpss", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 3241 { X86::CMPSSrm_alt, "cmpss", Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 3242 { X86::CMPS16, "cmpsw", Convert, { }, 0}, 3243 { X86::CMP16rr, "cmpw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3244 { X86::CMP16mr, "cmpw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 3245 { X86::CMP16ri8, "cmpw", Convert__Reg1_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 3246 { X86::CMP16mi8, "cmpw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 3247 { X86::CMP16i16, "cmpw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 3248 { X86::CMP16ri, "cmpw", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 3249 { X86::CMP16mi, "cmpw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 3250 { X86::CMP16rm, "cmpw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3251 { X86::CMPXCHG16B, "cmpxchg16b", Convert__Mem5_0, { MCK_Mem }, 0}, 3252 { X86::CMPXCHG8B, "cmpxchg8b", Convert__Mem5_0, { MCK_Mem }, 0}, 3253 { X86::CMPXCHG8rr, "cmpxchgb", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 3254 { X86::CMPXCHG8rm, "cmpxchgb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 3255 { X86::CMPXCHG32rr, "cmpxchgl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3256 { X86::CMPXCHG32rm, "cmpxchgl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 3257 { X86::CMPXCHG64rr, "cmpxchgq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3258 { X86::CMPXCHG64rm, "cmpxchgq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 3259 { X86::CMPXCHG16rr, "cmpxchgw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3260 { X86::CMPXCHG16rm, "cmpxchgw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 3261 { X86::COMISDrr, "comisd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3262 { X86::COMISDrm, "comisd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3263 { X86::COMISSrr, "comiss", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3264 { X86::COMISSrm, "comiss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3265 { X86::CPUID, "cpuid", Convert, { }, 0}, 3266 { X86::CQO, "cqto", Convert, { }, 0}, 3267 { X86::CRC32r32r8, "crc32b", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR8, MCK_GR32 }, 0}, 3268 { X86::CRC32r64r8, "crc32b", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR8, MCK_GR64 }, 0}, 3269 { X86::CRC32r32m8, "crc32b", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3270 { X86::CRC32r64m8, "crc32b", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3271 { X86::CRC32r32r32, "crc32l", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3272 { X86::CRC32r32m32, "crc32l", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3273 { X86::CRC32r64r64, "crc32q", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3274 { X86::CRC32r64m64, "crc32q", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3275 { X86::CRC32r32r16, "crc32w", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR32 }, 0}, 3276 { X86::CRC32r32m16, "crc32w", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3277 { X86::CS_PREFIX, "cs", Convert, { }, 0}, 3278 { X86::CVTDQ2PDrr, "cvtdq2pd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3279 { X86::CVTDQ2PDrm, "cvtdq2pd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3280 { X86::CVTDQ2PSrr, "cvtdq2ps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3281 { X86::CVTDQ2PSrm, "cvtdq2ps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3282 { X86::CVTPD2DQrr, "cvtpd2dq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3283 { X86::CVTPD2DQrm, "cvtpd2dq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3284 { X86::MMX_CVTPD2PIirr, "cvtpd2pi", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_VR64 }, 0}, 3285 { X86::MMX_CVTPD2PIirm, "cvtpd2pi", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 3286 { X86::CVTPD2PSrr, "cvtpd2ps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3287 { X86::CVTPD2PSrm, "cvtpd2ps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3288 { X86::MMX_CVTPI2PDirr, "cvtpi2pd", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_FR32 }, 0}, 3289 { X86::MMX_CVTPI2PDirm, "cvtpi2pd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3290 { X86::MMX_CVTPI2PSirr, "cvtpi2ps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_FR32 }, 0}, 3291 { X86::MMX_CVTPI2PSirm, "cvtpi2ps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3292 { X86::CVTPS2DQrr, "cvtps2dq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3293 { X86::CVTPS2DQrm, "cvtps2dq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3294 { X86::CVTPS2PDrr, "cvtps2pd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3295 { X86::CVTPS2PDrm, "cvtps2pd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3296 { X86::MMX_CVTPS2PIirr, "cvtps2pi", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_VR64 }, 0}, 3297 { X86::MMX_CVTPS2PIirm, "cvtps2pi", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 3298 { X86::CVTSD2SIrr, "cvtsd2sil", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 3299 { X86::CVTSD2SIrm, "cvtsd2sil", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3300 { X86::CVTSD2SI64rr, "cvtsd2siq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3301 { X86::CVTSD2SI64rm, "cvtsd2siq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3302 { X86::CVTSD2SSrr, "cvtsd2ss", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3303 { X86::CVTSD2SSrm, "cvtsd2ss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3304 { X86::CVTSI2SDrr, "cvtsi2sd", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32 }, 0}, 3305 { X86::CVTSI2SDrm, "cvtsi2sd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3306 { X86::CVTSI2SD64rr, "cvtsi2sdq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 3307 { X86::CVTSI2SD64rm, "cvtsi2sdq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3308 { X86::CVTSI2SSrr, "cvtsi2ss", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32 }, 0}, 3309 { X86::CVTSI2SSrm, "cvtsi2ss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3310 { X86::CVTSI2SS64rr, "cvtsi2ssq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 3311 { X86::CVTSI2SS64rm, "cvtsi2ssq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3312 { X86::CVTSS2SDrr, "cvtss2sd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3313 { X86::CVTSS2SDrm, "cvtss2sd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3314 { X86::CVTSS2SIrr, "cvtss2sil", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 3315 { X86::CVTSS2SIrm, "cvtss2sil", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3316 { X86::CVTSS2SI64rr, "cvtss2siq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3317 { X86::CVTSS2SI64rm, "cvtss2siq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3318 { X86::CVTTPD2DQrr, "cvttpd2dq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3319 { X86::CVTTPD2DQrm, "cvttpd2dq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3320 { X86::MMX_CVTTPD2PIirr, "cvttpd2pi", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_VR64 }, 0}, 3321 { X86::MMX_CVTTPD2PIirm, "cvttpd2pi", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 3322 { X86::CVTTPS2DQrr, "cvttps2dq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3323 { X86::CVTTPS2DQrm, "cvttps2dq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3324 { X86::MMX_CVTTPS2PIirr, "cvttps2pi", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_VR64 }, 0}, 3325 { X86::MMX_CVTTPS2PIirm, "cvttps2pi", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 3326 { X86::CVTTSD2SIrr, "cvttsd2si", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 3327 { X86::CVTTSD2SIrm, "cvttsd2si", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3328 { X86::CVTTSD2SI64rr, "cvttsd2siq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3329 { X86::CVTTSD2SI64rm, "cvttsd2siq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3330 { X86::CVTTSS2SIrr, "cvttss2si", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 3331 { X86::CVTTSS2SIrm, "cvttss2si", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3332 { X86::CVTTSS2SI64rr, "cvttss2siq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3333 { X86::CVTTSS2SI64rm, "cvttss2siq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3334 { X86::CWD, "cwtd", Convert, { }, 0}, 3335 { X86::CWDE, "cwtl", Convert, { }, 0}, 3336 { X86::DAA, "daa", Convert, { }, Feature_In32BitMode}, 3337 { X86::DAS, "das", Convert, { }, Feature_In32BitMode}, 3338 { X86::DATA16_PREFIX, "data16", Convert, { }, 0}, 3339 { X86::DEC8r, "decb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 3340 { X86::DEC8m, "decb", Convert__Mem5_0, { MCK_Mem }, 0}, 3341 { X86::DEC32r, "decl", Convert__Reg1_0__Tie0, { MCK_GR32 }, Feature_In32BitMode}, 3342 { X86::DEC64_32r, "decl", Convert__Reg1_0__Tie0, { MCK_GR32 }, Feature_In64BitMode}, 3343 { X86::DEC32m, "decl", Convert__Mem5_0, { MCK_Mem }, Feature_In32BitMode}, 3344 { X86::DEC64_32m, "decl", Convert__Mem5_0, { MCK_Mem }, Feature_In64BitMode}, 3345 { X86::DEC64r, "decq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 3346 { X86::DEC64m, "decq", Convert__Mem5_0, { MCK_Mem }, 0}, 3347 { X86::DEC16r, "decw", Convert__Reg1_0__Tie0, { MCK_GR16 }, Feature_In32BitMode}, 3348 { X86::DEC64_16r, "decw", Convert__Reg1_0__Tie0, { MCK_GR16 }, Feature_In64BitMode}, 3349 { X86::DEC16m, "decw", Convert__Mem5_0, { MCK_Mem }, Feature_In32BitMode}, 3350 { X86::DEC64_16m, "decw", Convert__Mem5_0, { MCK_Mem }, Feature_In64BitMode}, 3351 { X86::DIV8r, "divb", Convert__Reg1_0, { MCK_GR8 }, 0}, 3352 { X86::DIV8m, "divb", Convert__Mem5_0, { MCK_Mem }, 0}, 3353 { X86::DIV8r, "divb", Convert__Reg1_0, { MCK_GR8, MCK_AL }, 0}, 3354 { X86::DIV8m, "divb", Convert__Mem5_0, { MCK_Mem, MCK_AL }, 0}, 3355 { X86::DIV32r, "divl", Convert__Reg1_0, { MCK_GR32 }, 0}, 3356 { X86::DIV32m, "divl", Convert__Mem5_0, { MCK_Mem }, 0}, 3357 { X86::DIV32r, "divl", Convert__Reg1_0, { MCK_GR32, MCK_EAX }, 0}, 3358 { X86::DIV32m, "divl", Convert__Mem5_0, { MCK_Mem, MCK_EAX }, 0}, 3359 { X86::DIVPDrr, "divpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3360 { X86::DIVPDrm, "divpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3361 { X86::DIVPSrr, "divps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3362 { X86::DIVPSrm, "divps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3363 { X86::DIV64r, "divq", Convert__Reg1_0, { MCK_GR64 }, 0}, 3364 { X86::DIV64m, "divq", Convert__Mem5_0, { MCK_Mem }, 0}, 3365 { X86::DIV64r, "divq", Convert__Reg1_0, { MCK_GR64, MCK_RAX }, 0}, 3366 { X86::DIV64m, "divq", Convert__Mem5_0, { MCK_Mem, MCK_RAX }, 0}, 3367 { X86::DIVSDrr, "divsd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3368 { X86::DIVSDrm, "divsd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3369 { X86::DIVSSrr, "divss", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3370 { X86::DIVSSrm, "divss", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3371 { X86::DIV16r, "divw", Convert__Reg1_0, { MCK_GR16 }, 0}, 3372 { X86::DIV16m, "divw", Convert__Mem5_0, { MCK_Mem }, 0}, 3373 { X86::DIV16r, "divw", Convert__Reg1_0, { MCK_GR16, MCK_AX }, 0}, 3374 { X86::DIV16m, "divw", Convert__Mem5_0, { MCK_Mem, MCK_AX }, 0}, 3375 { X86::DPPDrri, "dppd", Convert__Reg1_2__Tie0__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32 }, 0}, 3376 { X86::DPPDrmi, "dppd", Convert__Reg1_2__Tie0__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32 }, 0}, 3377 { X86::DPPSrri, "dpps", Convert__Reg1_2__Tie0__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32 }, 0}, 3378 { X86::DPPSrmi, "dpps", Convert__Reg1_2__Tie0__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32 }, 0}, 3379 { X86::DS_PREFIX, "ds", Convert, { }, 0}, 3380 { X86::MMX_EMMS, "emms", Convert, { }, 0}, 3381 { X86::ENTER, "enter", Convert__Imm1_0__Imm1_1, { MCK_Imm, MCK_Imm }, 0}, 3382 { X86::ES_PREFIX, "es", Convert, { }, 0}, 3383 { X86::EXTRACTPSrr, "extractps", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR32 }, 0}, 3384 { X86::EXTRACTPSmr, "extractps", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 3385 { X86::F2XM1, "f2xm1", Convert, { }, 0}, 3386 { X86::ABS_F, "fabs", Convert, { }, 0}, 3387 { X86::ADD_FST0r, "fadd", Convert__Reg1_0, { MCK_RST }, 0}, 3388 { X86::ADD_FST0r, "fadd", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3389 { X86::ADD_FrST0, "fadd", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3390 { X86::ADD_FST0r, "fadd", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3391 { X86::ADD_F64m, "faddl", Convert__Mem5_0, { MCK_Mem }, 0}, 3392 { X86::ADD_FPrST0, "faddp", Convert__regST1, { }, 0}, 3393 { X86::ADD_FPrST0, "faddp", Convert__Reg1_0, { MCK_RST }, 0}, 3394 { X86::ADD_FPrST0, "faddp", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3395 { X86::ADD_FPrST0, "faddp", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3396 { X86::ADD_FPrST0, "faddp", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3397 { X86::ADD_F32m, "fadds", Convert__Mem5_0, { MCK_Mem }, 0}, 3398 { X86::FBLDm, "fbld", Convert__Mem5_0, { MCK_Mem }, 0}, 3399 { X86::FBSTPm, "fbstp", Convert__Mem5_0, { MCK_Mem }, 0}, 3400 { X86::CHS_F, "fchs", Convert, { }, 0}, 3401 { X86::CMOVB_F, "fcmovb", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3402 { X86::CMOVBE_F, "fcmovbe", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3403 { X86::CMOVE_F, "fcmove", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3404 { X86::CMOVNB_F, "fcmovnb", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3405 { X86::CMOVNBE_F, "fcmovnbe", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3406 { X86::CMOVNE_F, "fcmovne", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3407 { X86::CMOVNP_F, "fcmovnu", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3408 { X86::CMOVP_F, "fcmovu", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3409 { X86::COM_FST0r, "fcom", Convert__Reg1_0, { MCK_RST }, 0}, 3410 { X86::COM_FIr, "fcomi", Convert__regST1, { }, 0}, 3411 { X86::COM_FIr, "fcomi", Convert__Reg1_0, { MCK_RST }, 0}, 3412 { X86::COM_FIr, "fcomi", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3413 { X86::COM_FIr, "fcomi", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3414 { X86::FCOM64m, "fcoml", Convert__Mem5_0, { MCK_Mem }, 0}, 3415 { X86::COMP_FST0r, "fcomp", Convert__Reg1_0, { MCK_RST }, 0}, 3416 { X86::COM_FIPr, "fcompi", Convert__regST1, { }, 0}, 3417 { X86::COM_FIPr, "fcompi", Convert__Reg1_0, { MCK_RST }, 0}, 3418 { X86::COM_FIPr, "fcompi", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3419 { X86::COM_FIPr, "fcompi", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3420 { X86::FCOMP64m, "fcompl", Convert__Mem5_0, { MCK_Mem }, 0}, 3421 { X86::FCOMPP, "fcompp", Convert, { }, 0}, 3422 { X86::FCOMP32m, "fcomps", Convert__Mem5_0, { MCK_Mem }, 0}, 3423 { X86::FCOM32m, "fcoms", Convert__Mem5_0, { MCK_Mem }, 0}, 3424 { X86::COS_F, "fcos", Convert, { }, 0}, 3425 { X86::FDECSTP, "fdecstp", Convert, { }, 0}, 3426 { X86::DIV_FST0r, "fdiv", Convert__Reg1_0, { MCK_RST }, 0}, 3427 { X86::DIV_FST0r, "fdiv", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3428 { X86::DIVR_FrST0, "fdiv", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3429 { X86::DIV_FST0r, "fdiv", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3430 { X86::DIV_F64m, "fdivl", Convert__Mem5_0, { MCK_Mem }, 0}, 3431 { X86::DIVR_FPrST0, "fdivp", Convert__regST1, { }, 0}, 3432 { X86::DIVR_FPrST0, "fdivp", Convert__Reg1_0, { MCK_RST }, 0}, 3433 { X86::DIVR_FPrST0, "fdivp", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3434 { X86::DIVR_FPrST0, "fdivp", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3435 { X86::DIVR_FPrST0, "fdivp", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3436 { X86::DIVR_FST0r, "fdivr", Convert__Reg1_0, { MCK_RST }, 0}, 3437 { X86::DIVR_FST0r, "fdivr", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3438 { X86::DIV_FrST0, "fdivr", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3439 { X86::DIVR_FST0r, "fdivr", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3440 { X86::DIVR_F64m, "fdivrl", Convert__Mem5_0, { MCK_Mem }, 0}, 3441 { X86::DIV_FPrST0, "fdivrp", Convert__regST1, { }, 0}, 3442 { X86::DIV_FPrST0, "fdivrp", Convert__Reg1_0, { MCK_RST }, 0}, 3443 { X86::DIV_FPrST0, "fdivrp", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3444 { X86::DIV_FPrST0, "fdivrp", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3445 { X86::DIV_FPrST0, "fdivrp", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3446 { X86::DIVR_F32m, "fdivrs", Convert__Mem5_0, { MCK_Mem }, 0}, 3447 { X86::DIV_F32m, "fdivs", Convert__Mem5_0, { MCK_Mem }, 0}, 3448 { X86::FEMMS, "femms", Convert, { }, 0}, 3449 { X86::FFREE, "ffree", Convert__Reg1_0, { MCK_RST }, 0}, 3450 { X86::ADD_FI32m, "fiaddl", Convert__Mem5_0, { MCK_Mem }, 0}, 3451 { X86::ADD_FI16m, "fiadds", Convert__Mem5_0, { MCK_Mem }, 0}, 3452 { X86::FICOM32m, "ficoml", Convert__Mem5_0, { MCK_Mem }, 0}, 3453 { X86::FICOMP32m, "ficompl", Convert__Mem5_0, { MCK_Mem }, 0}, 3454 { X86::FICOMP16m, "ficomps", Convert__Mem5_0, { MCK_Mem }, 0}, 3455 { X86::FICOM16m, "ficoms", Convert__Mem5_0, { MCK_Mem }, 0}, 3456 { X86::DIV_FI32m, "fidivl", Convert__Mem5_0, { MCK_Mem }, 0}, 3457 { X86::DIVR_FI32m, "fidivrl", Convert__Mem5_0, { MCK_Mem }, 0}, 3458 { X86::DIVR_FI16m, "fidivrs", Convert__Mem5_0, { MCK_Mem }, 0}, 3459 { X86::DIV_FI16m, "fidivs", Convert__Mem5_0, { MCK_Mem }, 0}, 3460 { X86::ILD_F32m, "fildl", Convert__Mem5_0, { MCK_Mem }, 0}, 3461 { X86::ILD_F64m, "fildll", Convert__Mem5_0, { MCK_Mem }, 0}, 3462 { X86::ILD_F16m, "filds", Convert__Mem5_0, { MCK_Mem }, 0}, 3463 { X86::MUL_FI32m, "fimull", Convert__Mem5_0, { MCK_Mem }, 0}, 3464 { X86::MUL_FI16m, "fimuls", Convert__Mem5_0, { MCK_Mem }, 0}, 3465 { X86::FINCSTP, "fincstp", Convert, { }, 0}, 3466 { X86::IST_F32m, "fistl", Convert__Mem5_0, { MCK_Mem }, 0}, 3467 { X86::IST_FP32m, "fistpl", Convert__Mem5_0, { MCK_Mem }, 0}, 3468 { X86::IST_FP64m, "fistpll", Convert__Mem5_0, { MCK_Mem }, 0}, 3469 { X86::IST_FP16m, "fistps", Convert__Mem5_0, { MCK_Mem }, 0}, 3470 { X86::IST_F16m, "fists", Convert__Mem5_0, { MCK_Mem }, 0}, 3471 { X86::ISTT_FP32m, "fisttpl", Convert__Mem5_0, { MCK_Mem }, 0}, 3472 { X86::ISTT_FP64m, "fisttpll", Convert__Mem5_0, { MCK_Mem }, 0}, 3473 { X86::ISTT_FP16m, "fisttps", Convert__Mem5_0, { MCK_Mem }, 0}, 3474 { X86::SUB_FI32m, "fisubl", Convert__Mem5_0, { MCK_Mem }, 0}, 3475 { X86::SUBR_FI32m, "fisubrl", Convert__Mem5_0, { MCK_Mem }, 0}, 3476 { X86::SUBR_FI16m, "fisubrs", Convert__Mem5_0, { MCK_Mem }, 0}, 3477 { X86::SUB_FI16m, "fisubs", Convert__Mem5_0, { MCK_Mem }, 0}, 3478 { X86::LD_Frr, "fld", Convert__Reg1_0, { MCK_RST }, 0}, 3479 { X86::LD_F1, "fld1", Convert, { }, 0}, 3480 { X86::FLDCW16m, "fldcw", Convert__Mem5_0, { MCK_Mem }, 0}, 3481 { X86::FLDENVm, "fldenv", Convert__Mem5_0, { MCK_Mem }, 0}, 3482 { X86::LD_F64m, "fldl", Convert__Mem5_0, { MCK_Mem }, 0}, 3483 { X86::FLDL2E, "fldl2e", Convert, { }, 0}, 3484 { X86::FLDL2T, "fldl2t", Convert, { }, 0}, 3485 { X86::FLDLG2, "fldlg2", Convert, { }, 0}, 3486 { X86::FLDLN2, "fldln2", Convert, { }, 0}, 3487 { X86::FLDPI, "fldpi", Convert, { }, 0}, 3488 { X86::LD_F32m, "flds", Convert__Mem5_0, { MCK_Mem }, 0}, 3489 { X86::LD_F80m, "fldt", Convert__Mem5_0, { MCK_Mem }, 0}, 3490 { X86::LD_F0, "fldz", Convert, { }, 0}, 3491 { X86::MUL_FST0r, "fmul", Convert__Reg1_0, { MCK_RST }, 0}, 3492 { X86::MUL_FST0r, "fmul", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3493 { X86::MUL_FrST0, "fmul", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3494 { X86::MUL_FST0r, "fmul", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3495 { X86::MUL_F64m, "fmull", Convert__Mem5_0, { MCK_Mem }, 0}, 3496 { X86::MUL_FPrST0, "fmulp", Convert__regST1, { }, 0}, 3497 { X86::MUL_FPrST0, "fmulp", Convert__Reg1_0, { MCK_RST }, 0}, 3498 { X86::MUL_FPrST0, "fmulp", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3499 { X86::MUL_FPrST0, "fmulp", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3500 { X86::MUL_FPrST0, "fmulp", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3501 { X86::MUL_F32m, "fmuls", Convert__Mem5_0, { MCK_Mem }, 0}, 3502 { X86::FNCLEX, "fnclex", Convert, { }, 0}, 3503 { X86::FNINIT, "fninit", Convert, { }, 0}, 3504 { X86::FNOP, "fnop", Convert, { }, 0}, 3505 { X86::FSAVEm, "fnsave", Convert__Mem5_0, { MCK_Mem }, 0}, 3506 { X86::FNSTCW16m, "fnstcw", Convert__Mem5_0, { MCK_Mem }, 0}, 3507 { X86::FSTENVm, "fnstenv", Convert__Mem5_0, { MCK_Mem }, 0}, 3508 { X86::FNSTSW8r, "fnstsw", Convert, { }, 0}, 3509 { X86::FNSTSW8r, "fnstsw", Convert, { MCK_AL }, 0}, 3510 { X86::FNSTSW8r, "fnstsw", Convert, { MCK_AX }, 0}, 3511 { X86::FNSTSW8r, "fnstsw", Convert, { MCK_EAX }, 0}, 3512 { X86::FNSTSWm, "fnstsw", Convert__Mem5_0, { MCK_Mem }, 0}, 3513 { X86::FPATAN, "fpatan", Convert, { }, 0}, 3514 { X86::FPREM, "fprem", Convert, { }, 0}, 3515 { X86::FPREM1, "fprem1", Convert, { }, 0}, 3516 { X86::FPTAN, "fptan", Convert, { }, 0}, 3517 { X86::FRNDINT, "frndint", Convert, { }, 0}, 3518 { X86::FRSTORm, "frstor", Convert__Mem5_0, { MCK_Mem }, 0}, 3519 { X86::FS_PREFIX, "fs", Convert, { }, 0}, 3520 { X86::FSCALE, "fscale", Convert, { }, 0}, 3521 { X86::SIN_F, "fsin", Convert, { }, 0}, 3522 { X86::FSINCOS, "fsincos", Convert, { }, 0}, 3523 { X86::SQRT_F, "fsqrt", Convert, { }, 0}, 3524 { X86::ST_Frr, "fst", Convert__Reg1_0, { MCK_RST }, 0}, 3525 { X86::ST_F64m, "fstl", Convert__Mem5_0, { MCK_Mem }, 0}, 3526 { X86::ST_FPrr, "fstp", Convert__Reg1_0, { MCK_RST }, 0}, 3527 { X86::ST_FP64m, "fstpl", Convert__Mem5_0, { MCK_Mem }, 0}, 3528 { X86::ST_FP32m, "fstps", Convert__Mem5_0, { MCK_Mem }, 0}, 3529 { X86::ST_FP80m, "fstpt", Convert__Mem5_0, { MCK_Mem }, 0}, 3530 { X86::ST_F32m, "fsts", Convert__Mem5_0, { MCK_Mem }, 0}, 3531 { X86::SUB_FST0r, "fsub", Convert__Reg1_0, { MCK_RST }, 0}, 3532 { X86::SUB_FST0r, "fsub", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3533 { X86::SUBR_FrST0, "fsub", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3534 { X86::SUB_FST0r, "fsub", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3535 { X86::SUB_F64m, "fsubl", Convert__Mem5_0, { MCK_Mem }, 0}, 3536 { X86::SUBR_FPrST0, "fsubp", Convert__regST1, { }, 0}, 3537 { X86::SUBR_FPrST0, "fsubp", Convert__Reg1_0, { MCK_RST }, 0}, 3538 { X86::SUBR_FPrST0, "fsubp", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3539 { X86::SUBR_FPrST0, "fsubp", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3540 { X86::SUBR_FPrST0, "fsubp", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3541 { X86::SUBR_FST0r, "fsubr", Convert__Reg1_0, { MCK_RST }, 0}, 3542 { X86::SUBR_FST0r, "fsubr", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3543 { X86::SUB_FrST0, "fsubr", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3544 { X86::SUBR_FST0r, "fsubr", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3545 { X86::SUBR_F64m, "fsubrl", Convert__Mem5_0, { MCK_Mem }, 0}, 3546 { X86::SUB_FPrST0, "fsubrp", Convert__regST1, { }, 0}, 3547 { X86::SUB_FPrST0, "fsubrp", Convert__Reg1_0, { MCK_RST }, 0}, 3548 { X86::SUB_FPrST0, "fsubrp", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3549 { X86::SUB_FPrST0, "fsubrp", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3550 { X86::SUB_FPrST0, "fsubrp", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3551 { X86::SUBR_F32m, "fsubrs", Convert__Mem5_0, { MCK_Mem }, 0}, 3552 { X86::SUB_F32m, "fsubs", Convert__Mem5_0, { MCK_Mem }, 0}, 3553 { X86::TST_F, "ftst", Convert, { }, 0}, 3554 { X86::UCOM_Fr, "fucom", Convert__regST1, { }, 0}, 3555 { X86::UCOM_Fr, "fucom", Convert__Reg1_0, { MCK_RST }, 0}, 3556 { X86::UCOM_FIr, "fucomi", Convert__regST1, { }, 0}, 3557 { X86::UCOM_FIr, "fucomi", Convert__Reg1_0, { MCK_RST }, 0}, 3558 { X86::UCOM_FIr, "fucomi", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3559 { X86::UCOM_FIr, "fucomi", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3560 { X86::UCOM_FPr, "fucomp", Convert__regST1, { }, 0}, 3561 { X86::UCOM_FPr, "fucomp", Convert__Reg1_0, { MCK_RST }, 0}, 3562 { X86::UCOM_FIPr, "fucompi", Convert__regST1, { }, 0}, 3563 { X86::UCOM_FIPr, "fucompi", Convert__Reg1_0, { MCK_RST }, 0}, 3564 { X86::UCOM_FIPr, "fucompi", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3565 { X86::UCOM_FIPr, "fucompi", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0}, 3566 { X86::UCOM_FPPr, "fucompp", Convert, { }, 0}, 3567 { X86::FXAM, "fxam", Convert, { }, 0}, 3568 { X86::XCH_F, "fxch", Convert__regST1, { }, 0}, 3569 { X86::XCH_F, "fxch", Convert__Reg1_0, { MCK_RST }, 0}, 3570 { X86::FXRSTOR, "fxrstor", Convert__Mem5_0, { MCK_Mem }, 0}, 3571 { X86::FXRSTOR64, "fxrstorq", Convert__Mem5_0, { MCK_Mem }, Feature_In64BitMode}, 3572 { X86::FXSAVE, "fxsave", Convert__Mem5_0, { MCK_Mem }, 0}, 3573 { X86::FXSAVE64, "fxsaveq", Convert__Mem5_0, { MCK_Mem }, Feature_In64BitMode}, 3574 { X86::FXTRACT, "fxtract", Convert, { }, 0}, 3575 { X86::FYL2X, "fyl2x", Convert, { }, 0}, 3576 { X86::FYL2XP1, "fyl2xp1", Convert, { }, 0}, 3577 { X86::GS_PREFIX, "gs", Convert, { }, 0}, 3578 { X86::HADDPDrr, "haddpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3579 { X86::HADDPDrm, "haddpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3580 { X86::HADDPSrr, "haddps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3581 { X86::HADDPSrm, "haddps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3582 { X86::HLT, "hlt", Convert, { }, 0}, 3583 { X86::HSUBPDrr, "hsubpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3584 { X86::HSUBPDrm, "hsubpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3585 { X86::HSUBPSrr, "hsubps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3586 { X86::HSUBPSrm, "hsubps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3587 { X86::IDIV8r, "idivb", Convert__Reg1_0, { MCK_GR8 }, 0}, 3588 { X86::IDIV8m, "idivb", Convert__Mem5_0, { MCK_Mem }, 0}, 3589 { X86::IDIV8r, "idivb", Convert__Reg1_0, { MCK_GR8, MCK_AL }, 0}, 3590 { X86::IDIV8m, "idivb", Convert__Mem5_0, { MCK_Mem, MCK_AL }, 0}, 3591 { X86::IDIV32r, "idivl", Convert__Reg1_0, { MCK_GR32 }, 0}, 3592 { X86::IDIV32m, "idivl", Convert__Mem5_0, { MCK_Mem }, 0}, 3593 { X86::IDIV32r, "idivl", Convert__Reg1_0, { MCK_GR32, MCK_EAX }, 0}, 3594 { X86::IDIV32m, "idivl", Convert__Mem5_0, { MCK_Mem, MCK_EAX }, 0}, 3595 { X86::IDIV64r, "idivq", Convert__Reg1_0, { MCK_GR64 }, 0}, 3596 { X86::IDIV64m, "idivq", Convert__Mem5_0, { MCK_Mem }, 0}, 3597 { X86::IDIV64r, "idivq", Convert__Reg1_0, { MCK_GR64, MCK_RAX }, 0}, 3598 { X86::IDIV64m, "idivq", Convert__Mem5_0, { MCK_Mem, MCK_RAX }, 0}, 3599 { X86::IDIV16r, "idivw", Convert__Reg1_0, { MCK_GR16 }, 0}, 3600 { X86::IDIV16m, "idivw", Convert__Mem5_0, { MCK_Mem }, 0}, 3601 { X86::IDIV16r, "idivw", Convert__Reg1_0, { MCK_GR16, MCK_AX }, 0}, 3602 { X86::IDIV16m, "idivw", Convert__Mem5_0, { MCK_Mem, MCK_AX }, 0}, 3603 { X86::IMUL8r, "imulb", Convert__Reg1_0, { MCK_GR8 }, 0}, 3604 { X86::IMUL8m, "imulb", Convert__Mem5_0, { MCK_Mem }, 0}, 3605 { X86::IMUL32r, "imull", Convert__Reg1_0, { MCK_GR32 }, 0}, 3606 { X86::IMUL32m, "imull", Convert__Mem5_0, { MCK_Mem }, 0}, 3607 { X86::IMUL32rr, "imull", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3608 { X86::IMUL32rri8, "imull", Convert__Reg1_1__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 3609 { X86::IMUL32rri, "imull", Convert__Reg1_1__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 3610 { X86::IMUL32rm, "imull", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3611 { X86::IMUL32rri8, "imull", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32, MCK_GR32 }, 0}, 3612 { X86::IMUL32rmi8, "imull", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_GR32 }, 0}, 3613 { X86::IMUL32rri, "imull", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR32, MCK_GR32 }, 0}, 3614 { X86::IMUL32rmi, "imull", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_GR32 }, 0}, 3615 { X86::IMUL64r, "imulq", Convert__Reg1_0, { MCK_GR64 }, 0}, 3616 { X86::IMUL64m, "imulq", Convert__Mem5_0, { MCK_Mem }, 0}, 3617 { X86::IMUL64rr, "imulq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3618 { X86::IMUL64rri8, "imulq", Convert__Reg1_1__Reg1_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 3619 { X86::IMUL64rri32, "imulq", Convert__Reg1_1__Reg1_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 3620 { X86::IMUL64rm, "imulq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3621 { X86::IMUL64rri8, "imulq", Convert__Reg1_2__Reg1_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64, MCK_GR64 }, 0}, 3622 { X86::IMUL64rmi8, "imulq", Convert__Reg1_2__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem, MCK_GR64 }, 0}, 3623 { X86::IMUL64rri32, "imulq", Convert__Reg1_2__Reg1_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64, MCK_GR64 }, 0}, 3624 { X86::IMUL64rmi32, "imulq", Convert__Reg1_2__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem, MCK_GR64 }, 0}, 3625 { X86::IMUL16r, "imulw", Convert__Reg1_0, { MCK_GR16 }, 0}, 3626 { X86::IMUL16m, "imulw", Convert__Mem5_0, { MCK_Mem }, 0}, 3627 { X86::IMUL16rr, "imulw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3628 { X86::IMUL16rri8, "imulw", Convert__Reg1_1__Reg1_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 3629 { X86::IMUL16rri, "imulw", Convert__Reg1_1__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 3630 { X86::IMUL16rm, "imulw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3631 { X86::IMUL16rri8, "imulw", Convert__Reg1_2__Reg1_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16, MCK_GR16 }, 0}, 3632 { X86::IMUL16rmi8, "imulw", Convert__Reg1_2__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem, MCK_GR16 }, 0}, 3633 { X86::IMUL16rri, "imulw", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR16, MCK_GR16 }, 0}, 3634 { X86::IMUL16rmi, "imulw", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_GR16 }, 0}, 3635 { X86::IN8rr, "inb", Convert, { MCK_DX }, 0}, 3636 { X86::IN8ri, "inb", Convert__Imm1_0, { MCK_Imm }, 0}, 3637 { X86::IN8rr, "inb", Convert, { MCK_DX, MCK_AL }, 0}, 3638 { X86::IN8ri, "inb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 3639 { X86::INC8r, "incb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 3640 { X86::INC8m, "incb", Convert__Mem5_0, { MCK_Mem }, 0}, 3641 { X86::INC32r, "incl", Convert__Reg1_0__Tie0, { MCK_GR32 }, Feature_In32BitMode}, 3642 { X86::INC64_32r, "incl", Convert__Reg1_0__Tie0, { MCK_GR32 }, Feature_In64BitMode}, 3643 { X86::INC32m, "incl", Convert__Mem5_0, { MCK_Mem }, Feature_In32BitMode}, 3644 { X86::INC64_32m, "incl", Convert__Mem5_0, { MCK_Mem }, Feature_In64BitMode}, 3645 { X86::INC64r, "incq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 3646 { X86::INC64m, "incq", Convert__Mem5_0, { MCK_Mem }, 0}, 3647 { X86::INC16r, "incw", Convert__Reg1_0__Tie0, { MCK_GR16 }, Feature_In32BitMode}, 3648 { X86::INC64_16r, "incw", Convert__Reg1_0__Tie0, { MCK_GR16 }, Feature_In64BitMode}, 3649 { X86::INC16m, "incw", Convert__Mem5_0, { MCK_Mem }, Feature_In32BitMode}, 3650 { X86::INC64_16m, "incw", Convert__Mem5_0, { MCK_Mem }, Feature_In64BitMode}, 3651 { X86::IN32rr, "inl", Convert, { MCK_DX }, 0}, 3652 { X86::IN32ri, "inl", Convert__Imm1_0, { MCK_Imm }, 0}, 3653 { X86::IN32rr, "inl", Convert, { MCK_DX, MCK_EAX }, 0}, 3654 { X86::IN32ri, "inl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 3655 { X86::IN8, "insb", Convert, { }, 0}, 3656 { X86::INSERTPSrr, "insertps", Convert__Reg1_2__Tie0__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32 }, 0}, 3657 { X86::INSERTPSrm, "insertps", Convert__Reg1_2__Tie0__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32 }, 0}, 3658 { X86::IN32, "insl", Convert, { }, 0}, 3659 { X86::IN16, "insw", Convert, { }, 0}, 3660 { X86::INT, "int", Convert__Imm1_0, { MCK_Imm }, 0}, 3661 { X86::INT3, "int3", Convert, { }, 0}, 3662 { X86::INTO, "into", Convert, { }, 0}, 3663 { X86::INVD, "invd", Convert, { }, 0}, 3664 { X86::INVEPT32, "invept", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3665 { X86::INVEPT64, "invept", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3666 { X86::INVLPG, "invlpg", Convert__Mem5_0, { MCK_Mem }, 0}, 3667 { X86::INVVPID32, "invvpid", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3668 { X86::INVVPID64, "invvpid", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3669 { X86::IN16rr, "inw", Convert, { MCK_DX }, 0}, 3670 { X86::IN16ri, "inw", Convert__Imm1_0, { MCK_Imm }, 0}, 3671 { X86::IN16rr, "inw", Convert, { MCK_DX, MCK_AX }, 0}, 3672 { X86::IN16ri, "inw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 3673 { X86::IRET32, "iretl", Convert, { }, 0}, 3674 { X86::IRET64, "iretq", Convert, { }, Feature_In64BitMode}, 3675 { X86::IRET16, "iretw", Convert, { }, 0}, 3676 { X86::JA_1, "ja", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3677 { X86::JA_4, "ja", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3678 { X86::JAE_1, "jae", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3679 { X86::JAE_4, "jae", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3680 { X86::JB_1, "jb", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3681 { X86::JB_4, "jb", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3682 { X86::JBE_1, "jbe", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3683 { X86::JBE_4, "jbe", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3684 { X86::JCXZ, "jcxz", Convert__AbsMem1_0, { MCK_AbsMem }, Feature_In32BitMode}, 3685 { X86::JE_1, "je", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3686 { X86::JE_4, "je", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3687 { X86::JECXZ_32, "jecxz", Convert__AbsMem1_0, { MCK_AbsMem }, Feature_In32BitMode}, 3688 { X86::JECXZ_64, "jecxz", Convert__AbsMem1_0, { MCK_AbsMem }, Feature_In64BitMode}, 3689 { X86::JG_1, "jg", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3690 { X86::JG_4, "jg", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3691 { X86::JGE_1, "jge", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3692 { X86::JGE_4, "jge", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3693 { X86::JL_1, "jl", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3694 { X86::JL_4, "jl", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3695 { X86::JLE_1, "jle", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3696 { X86::JLE_4, "jle", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3697 { X86::JMP_1, "jmp", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3698 { X86::JMP_4, "jmp", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3699 { X86::FARJMP32i, "jmp", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3700 { X86::JMP32r, "jmpl", Convert__Reg1_1, { MCK__STAR_, MCK_GR32 }, Feature_In32BitMode}, 3701 { X86::JMP32m, "jmpl", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, Feature_In32BitMode}, 3702 { X86::FARJMP32i, "jmpl", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3703 { X86::JMP64pcrel32, "jmpq", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3704 { X86::JMP64r, "jmpq", Convert__Reg1_1, { MCK__STAR_, MCK_GR64 }, Feature_In64BitMode}, 3705 { X86::JMP64m, "jmpq", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, Feature_In64BitMode}, 3706 { X86::FARJMP16i, "jmpw", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3707 { X86::JNE_1, "jne", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3708 { X86::JNE_4, "jne", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3709 { X86::JNO_1, "jno", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3710 { X86::JNO_4, "jno", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3711 { X86::JNP_1, "jnp", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3712 { X86::JNP_4, "jnp", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3713 { X86::JNS_1, "jns", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3714 { X86::JNS_4, "jns", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3715 { X86::JO_1, "jo", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3716 { X86::JO_4, "jo", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3717 { X86::JP_1, "jp", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3718 { X86::JP_4, "jp", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3719 { X86::JRCXZ, "jrcxz", Convert__AbsMem1_0, { MCK_AbsMem }, Feature_In64BitMode}, 3720 { X86::JS_1, "js", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3721 { X86::JS_4, "js", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3722 { X86::LAHF, "lahf", Convert, { }, 0}, 3723 { X86::LAR32rr, "larl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3724 { X86::LAR32rm, "larl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3725 { X86::LAR64rr, "larq", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR64 }, 0}, 3726 { X86::LAR64rm, "larq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3727 { X86::LAR16rr, "larw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3728 { X86::LAR16rm, "larw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3729 { X86::FARCALL32m, "lcall", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, 0}, 3730 { X86::FARCALL32i, "lcall", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3731 { X86::FARCALL32m, "lcalll", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, 0}, 3732 { X86::FARCALL32i, "lcalll", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3733 { X86::FARCALL64, "lcallq", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, 0}, 3734 { X86::FARCALL16m, "lcallw", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, 0}, 3735 { X86::FARCALL16i, "lcallw", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3736 { X86::LDDQUrm, "lddqu", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3737 { X86::LDMXCSR, "ldmxcsr", Convert__Mem5_0, { MCK_Mem }, 0}, 3738 { X86::LDS32rm, "ldsl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3739 { X86::LDS16rm, "ldsw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3740 { X86::LEA32r, "leal", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, Feature_In32BitMode}, 3741 { X86::LEA64_32r, "leal", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, Feature_In64BitMode}, 3742 { X86::LEA64r, "leaq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3743 { X86::LEAVE, "leave", Convert, { }, Feature_In32BitMode}, 3744 { X86::LEAVE64, "leave", Convert, { }, Feature_In64BitMode}, 3745 { X86::LEA16r, "leaw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3746 { X86::LES32rm, "lesl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3747 { X86::LES16rm, "lesw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3748 { X86::LFENCE, "lfence", Convert, { }, 0}, 3749 { X86::LFS32rm, "lfsl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3750 { X86::LFS64rm, "lfsq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3751 { X86::LFS16rm, "lfsw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3752 { X86::LGDTm, "lgdt", Convert__Mem5_0, { MCK_Mem }, 0}, 3753 { X86::LGDT16m, "lgdtw", Convert__Mem5_0, { MCK_Mem }, Feature_In32BitMode}, 3754 { X86::LGS32rm, "lgsl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3755 { X86::LGS64rm, "lgsq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3756 { X86::LGS16rm, "lgsw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3757 { X86::LIDTm, "lidt", Convert__Mem5_0, { MCK_Mem }, 0}, 3758 { X86::LIDT16m, "lidtw", Convert__Mem5_0, { MCK_Mem }, Feature_In32BitMode}, 3759 { X86::FARJMP32m, "ljmp", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, 0}, 3760 { X86::FARJMP32i, "ljmp", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3761 { X86::FARJMP32m, "ljmpl", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, 0}, 3762 { X86::FARJMP32i, "ljmpl", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3763 { X86::FARJMP64, "ljmpq", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, 0}, 3764 { X86::FARJMP16m, "ljmpw", Convert__Mem5_1, { MCK__STAR_, MCK_Mem }, 0}, 3765 { X86::FARJMP16i, "ljmpw", Convert__Imm1_1__Imm1_0, { MCK_Imm, MCK_Imm }, 0}, 3766 { X86::LLDT16r, "lldtw", Convert__Reg1_0, { MCK_GR16 }, 0}, 3767 { X86::LLDT16m, "lldtw", Convert__Mem5_0, { MCK_Mem }, 0}, 3768 { X86::LMSW16r, "lmsww", Convert__Reg1_0, { MCK_GR16 }, 0}, 3769 { X86::LMSW16m, "lmsww", Convert__Mem5_0, { MCK_Mem }, 0}, 3770 { X86::LOCK_PREFIX, "lock", Convert, { }, 0}, 3771 { X86::LODSB, "lodsb", Convert, { }, 0}, 3772 { X86::LODSD, "lodsl", Convert, { }, 0}, 3773 { X86::LODSQ, "lodsq", Convert, { }, 0}, 3774 { X86::LODSW, "lodsw", Convert, { }, 0}, 3775 { X86::LOOP, "loop", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3776 { X86::LOOPE, "loope", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3777 { X86::LOOPNE, "loopne", Convert__AbsMem1_0, { MCK_AbsMem }, 0}, 3778 { X86::LRETI, "lret", Convert__Imm1_0, { MCK_Imm }, 0}, 3779 { X86::LRETL, "lretl", Convert, { }, 0}, 3780 { X86::LRETQ, "lretq", Convert, { }, 0}, 3781 { X86::LRETIW, "lretw", Convert__Imm1_0, { MCK_Imm }, 0}, 3782 { X86::LSL32rr, "lsll", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3783 { X86::LSL32rm, "lsll", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3784 { X86::LSL64rr, "lslq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3785 { X86::LSL64rm, "lslq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3786 { X86::LSL16rr, "lslw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3787 { X86::LSL16rm, "lslw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3788 { X86::LSS32rm, "lssl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3789 { X86::LSS64rm, "lssq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3790 { X86::LSS16rm, "lssw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3791 { X86::LTRr, "ltrw", Convert__Reg1_0, { MCK_GR16 }, 0}, 3792 { X86::LTRm, "ltrw", Convert__Mem5_0, { MCK_Mem }, 0}, 3793 { X86::LZCNT32rr, "lzcntl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3794 { X86::LZCNT32rm, "lzcntl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3795 { X86::LZCNT64rr, "lzcntq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3796 { X86::LZCNT64rm, "lzcntq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3797 { X86::LZCNT16rr, "lzcntw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 3798 { X86::LZCNT16rm, "lzcntw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3799 { X86::MASKMOVDQU, "maskmovdqu", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3800 { X86::MASKMOVDQU64, "maskmovdqu", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3801 { X86::MMX_MASKMOVQ, "maskmovq", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 3802 { X86::MMX_MASKMOVQ64, "maskmovq", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, Feature_In64BitMode}, 3803 { X86::MAXPDrr, "maxpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3804 { X86::MAXPDrm, "maxpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3805 { X86::MAXPSrr, "maxps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3806 { X86::MAXPSrm, "maxps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3807 { X86::MAXSDrr, "maxsd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3808 { X86::MAXSDrm, "maxsd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3809 { X86::MAXSSrr, "maxss", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3810 { X86::MAXSSrm, "maxss", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3811 { X86::MFENCE, "mfence", Convert, { }, 0}, 3812 { X86::MINPDrr, "minpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3813 { X86::MINPDrm, "minpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3814 { X86::MINPSrr, "minps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3815 { X86::MINPSrm, "minps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3816 { X86::MINSDrr, "minsd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3817 { X86::MINSDrm, "minsd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3818 { X86::MINSSrr, "minss", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3819 { X86::MINSSrm, "minss", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3820 { X86::MONITORrrr, "monitor", Convert, { }, 0}, 3821 { X86::MONITORrrr, "monitor", Convert, { MCK_EAX, MCK_ECX, MCK_EDX }, Feature_In32BitMode}, 3822 { X86::MONITORrrr, "monitor", Convert, { MCK_RAX, MCK_RCX, MCK_RDX }, Feature_In64BitMode}, 3823 { X86::MONTMUL, "montmul", Convert, { }, 0}, 3824 { X86::MOV32ms, "mov", Convert__Mem5_1__Reg1_0, { MCK_SEGMENT_REG, MCK_Mem }, 0}, 3825 { X86::MOV32sm, "mov", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_SEGMENT_REG }, 0}, 3826 { X86::MOV64ri, "movabsq", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR64 }, 0}, 3827 { X86::FsMOVAPDrr, "movapd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3828 { X86::MOVAPDrr, "movapd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3829 { X86::MOVAPDmr, "movapd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3830 { X86::FsMOVAPDrm, "movapd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3831 { X86::MOVAPDrm, "movapd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3832 { X86::FsMOVAPSrr, "movaps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3833 { X86::MOVAPSrr, "movaps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3834 { X86::MOVAPSmr, "movaps", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3835 { X86::FsMOVAPSrm, "movaps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3836 { X86::MOVAPSrm, "movaps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3837 { X86::MOV8ao8, "movb", Convert__AbsMem1_1, { MCK_AL, MCK_AbsMem }, Feature_In32BitMode}, 3838 { X86::MOV8rr, "movb", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 3839 { X86::MOV8mr, "movb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 3840 { X86::MOV8ri, "movb", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 3841 { X86::MOV8mi, "movb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 3842 { X86::MOV8o8a, "movb", Convert__AbsMem1_0, { MCK_AbsMem, MCK_AL }, Feature_In32BitMode}, 3843 { X86::MOV8rm, "movb", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 3844 { X86::MOVBE32mr, "movbel", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 3845 { X86::MOVBE32rm, "movbel", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3846 { X86::MOVBE64mr, "movbeq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 3847 { X86::MOVBE64rm, "movbeq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3848 { X86::MOVBE16mr, "movbew", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 3849 { X86::MOVBE16rm, "movbew", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3850 { X86::MMX_MOVD64rr, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_VR64 }, 0}, 3851 { X86::MMX_MOVZDI2PDIrr, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_VR64 }, 0}, 3852 { X86::MOVDI2PDIrr, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32 }, 0}, 3853 { X86::MOVDI2SSrr, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32 }, 0}, 3854 { X86::MOVZDI2PDIrr, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32 }, 0}, 3855 { X86::MMX_MOVD64rrv164, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_VR64 }, 0}, 3856 { X86::MMX_MOVD64to64rr, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_VR64 }, 0}, 3857 { X86::MOV64toPQIrr, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 3858 { X86::MOV64toSDrr, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 3859 { X86::MOVZQI2PQIrr, "movd", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 3860 { X86::MMX_MOVD64grr, "movd", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_GR32 }, 0}, 3861 { X86::MMX_MOVD64from64rr, "movd", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_GR64 }, 0}, 3862 { X86::MMX_MOVD64mr, "movd", Convert__Mem5_1__Reg1_0, { MCK_VR64, MCK_Mem }, 0}, 3863 { X86::MOVPDI2DIrr, "movd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 3864 { X86::MOVSS2DIrr, "movd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 3865 { X86::MOVPQIto64rr, "movd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3866 { X86::MOVSDto64rr, "movd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3867 { X86::VMOVPQIto64rr, "movd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, Feature_In64BitMode}, 3868 { X86::MOVPDI2DImr, "movd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3869 { X86::MOVSS2DImr, "movd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3870 { X86::MMX_MOVD64rm, "movd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 3871 { X86::MMX_MOVZDI2PDIrm, "movd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 3872 { X86::MOVDI2PDIrm, "movd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3873 { X86::MOVDI2SSrm, "movd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3874 { X86::MOVZDI2PDIrm, "movd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3875 { X86::MOVDDUPrr, "movddup", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3876 { X86::MOVDDUPrm, "movddup", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3877 { X86::MMX_MOVDQ2Qrr, "movdq2q", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_VR64 }, 0}, 3878 { X86::MMX_MOVFR642Qrr, "movdq2q", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_VR64 }, 0}, 3879 { X86::MOVDQArr, "movdqa", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3880 { X86::MOVDQAmr, "movdqa", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3881 { X86::MOVDQArm, "movdqa", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3882 { X86::MOVDQUrr, "movdqu", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3883 { X86::MOVDQUmr, "movdqu", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3884 { X86::MOVDQUrm, "movdqu", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3885 { X86::MOVHLPSrr, "movhlps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3886 { X86::MOVHPDmr, "movhpd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3887 { X86::MOVHPDrm, "movhpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3888 { X86::MOVHPSmr, "movhps", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3889 { X86::MOVHPSrm, "movhps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3890 { X86::MOV32ao32, "movl", Convert__AbsMem1_1, { MCK_EAX, MCK_AbsMem }, Feature_In32BitMode}, 3891 { X86::MOV32rr, "movl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 3892 { X86::MOV32sr, "movl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_SEGMENT_REG }, 0}, 3893 { X86::MOV32dr, "movl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_DEBUG_REG }, 0}, 3894 { X86::MOV32cr, "movl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_CONTROL_REG }, 0}, 3895 { X86::MOV32mr, "movl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 3896 { X86::MOV32rs, "movl", Convert__Reg1_1__Reg1_0, { MCK_SEGMENT_REG, MCK_GR32 }, 0}, 3897 { X86::MOV32ms, "movl", Convert__Mem5_1__Reg1_0, { MCK_SEGMENT_REG, MCK_Mem }, 0}, 3898 { X86::MOV32rd, "movl", Convert__Reg1_1__Reg1_0, { MCK_DEBUG_REG, MCK_GR32 }, 0}, 3899 { X86::MOV32rc, "movl", Convert__Reg1_1__Reg1_0, { MCK_CONTROL_REG, MCK_GR32 }, 0}, 3900 { X86::MOV32ri, "movl", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 3901 { X86::MOV32mi, "movl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 3902 { X86::MOV32o32a, "movl", Convert__AbsMem1_0, { MCK_AbsMem, MCK_EAX }, Feature_In32BitMode}, 3903 { X86::MOV32rm, "movl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3904 { X86::MOV32sm, "movl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_SEGMENT_REG }, 0}, 3905 { X86::MOVLHPSrr, "movlhps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3906 { X86::MOVLPDmr, "movlpd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3907 { X86::MOVLPDrm, "movlpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3908 { X86::MOVLPSmr, "movlps", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3909 { X86::MOVLPSrm, "movlps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3910 { X86::MOVMSKPDrr32, "movmskpd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 3911 { X86::MOVMSKPDrr64, "movmskpd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3912 { X86::MOVMSKPSrr32, "movmskps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 3913 { X86::MOVMSKPSrr64, "movmskps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3914 { X86::MOVNTDQ_64mr, "movntdq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3915 { X86::MOVNTDQmr, "movntdq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3916 { X86::MOVNTDQArm, "movntdqa", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3917 { X86::MOVNTImr, "movntil", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 3918 { X86::MOVNTI_64mr, "movntiq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 3919 { X86::MOVNTPDmr, "movntpd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3920 { X86::MOVNTPSmr, "movntps", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3921 { X86::MMX_MOVNTQmr, "movntq", Convert__Mem5_1__Reg1_0, { MCK_VR64, MCK_Mem }, 0}, 3922 { X86::MOV64rr, "movq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 3923 { X86::MMX_MOVD64to64rr, "movq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_VR64 }, 0}, 3924 { X86::MOV64toPQIrr, "movq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 3925 { X86::MOV64toSDrr, "movq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 3926 { X86::VMOVZQI2PQIrr, "movq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 3927 { X86::MOVZQI2PQIrr, "movq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 3928 { X86::MOV64sr, "movq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_SEGMENT_REG }, 0}, 3929 { X86::MOV64dr, "movq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_DEBUG_REG }, 0}, 3930 { X86::MOV64cr, "movq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_CONTROL_REG }, 0}, 3931 { X86::MOV64mr, "movq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 3932 { X86::MMX_MOVD64from64rr, "movq", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_GR64 }, 0}, 3933 { X86::MMX_MOVQ64rr, "movq", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 3934 { X86::MMX_MOVQ64mr, "movq", Convert__Mem5_1__Reg1_0, { MCK_VR64, MCK_Mem }, 0}, 3935 { X86::MOVPQIto64rr, "movq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3936 { X86::MOVSDto64rr, "movq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 3937 { X86::MOVQxrxr, "movq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3938 { X86::MOVZPQILo2PQIrr, "movq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3939 { X86::MOVLQ128mr, "movq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3940 { X86::MOVPQI2QImr, "movq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3941 { X86::MOVSDto64mr, "movq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3942 { X86::MOV64rs, "movq", Convert__Reg1_1__Reg1_0, { MCK_SEGMENT_REG, MCK_GR64 }, 0}, 3943 { X86::MOV64ms, "movq", Convert__Mem5_1__Reg1_0, { MCK_SEGMENT_REG, MCK_Mem }, 0}, 3944 { X86::MOV64rd, "movq", Convert__Reg1_1__Reg1_0, { MCK_DEBUG_REG, MCK_GR64 }, 0}, 3945 { X86::MOV64rc, "movq", Convert__Reg1_1__Reg1_0, { MCK_CONTROL_REG, MCK_GR64 }, 0}, 3946 { X86::MOV64ri32, "movq", Convert__Reg1_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 3947 { X86::MOV64mi32, "movq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 3948 { X86::MOV64ri, "movq", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR64 }, 0}, 3949 { X86::MOV64rm, "movq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3950 { X86::MMX_MOVQ64rm, "movq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 3951 { X86::MOV64toSDrm, "movq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3952 { X86::MOVQI2PQIrm, "movq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3953 { X86::MOVZPQILo2PQIrm, "movq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3954 { X86::MOVZQI2PQIrm, "movq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3955 { X86::MOV64sm, "movq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_SEGMENT_REG }, 0}, 3956 { X86::MMX_MOVQ2DQrr, "movq2dq", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_FR32 }, 0}, 3957 { X86::MMX_MOVQ2FR64rr, "movq2dq", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_FR32 }, 0}, 3958 { X86::MOVSB, "movsb", Convert, { }, 0}, 3959 { X86::MOVSX32rr8, "movsbl", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR32 }, 0}, 3960 { X86::MOVSX32rm8, "movsbl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3961 { X86::MOVSX64rr8, "movsbq", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR64 }, 0}, 3962 { X86::MOVSX64rm8, "movsbq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3963 { X86::MOVSX16rr8, "movsbw", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR16 }, 0}, 3964 { X86::MOVSX16rm8, "movsbw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3965 { X86::MOVSD, "movsd", Convert, { }, 0}, 3966 { X86::MOVSDrr, "movsd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3967 { X86::MOVSDmr, "movsd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3968 { X86::MOVSDrm, "movsd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3969 { X86::MOVSHDUPrr, "movshdup", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3970 { X86::MOVSHDUPrm, "movshdup", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3971 { X86::MOVSD, "movsl", Convert, { }, 0}, 3972 { X86::MOVSLDUPrr, "movsldup", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3973 { X86::MOVSLDUPrm, "movsldup", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3974 { X86::MOVSX64rr32, "movslq", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR64 }, 0}, 3975 { X86::MOVSX64rm32, "movslq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3976 { X86::MOVSQ, "movsq", Convert, { }, 0}, 3977 { X86::MOVSSrr, "movss", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3978 { X86::MOVSSmr, "movss", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3979 { X86::MOVSSrm, "movss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3980 { X86::MOVSW, "movsw", Convert, { }, 0}, 3981 { X86::MOVSX32rr16, "movswl", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR32 }, 0}, 3982 { X86::MOVSX32rm16, "movswl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 3983 { X86::MOVSX64rr16, "movswq", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR64 }, 0}, 3984 { X86::MOVSX64rm16, "movswq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 3985 { X86::MOVSX16rr8, "movsx", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR16 }, 0}, 3986 { X86::MOVSX32rr8, "movsx", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR32 }, 0}, 3987 { X86::MOVSX64rr8, "movsx", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR64 }, 0}, 3988 { X86::MOVSX32rr16, "movsx", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR32 }, 0}, 3989 { X86::MOVSX64rr16, "movsx", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR64 }, 0}, 3990 { X86::MOVSX64rr32, "movsx", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR64 }, 0}, 3991 { X86::MOVSX16rm8, "movsx", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 3992 { X86::MOVUPDrr, "movupd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3993 { X86::MOVUPDmr, "movupd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3994 { X86::MOVUPDrm, "movupd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3995 { X86::MOVUPSrr, "movups", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 3996 { X86::MOVUPSmr, "movups", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 3997 { X86::MOVUPSrm, "movups", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 3998 { X86::MOV16ao16, "movw", Convert__AbsMem1_1, { MCK_AX, MCK_AbsMem }, Feature_In32BitMode}, 3999 { X86::MOV16rr, "movw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 4000 { X86::MOV16sr, "movw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_SEGMENT_REG }, 0}, 4001 { X86::MOV16mr, "movw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 4002 { X86::MOV16rs, "movw", Convert__Reg1_1__Reg1_0, { MCK_SEGMENT_REG, MCK_GR16 }, 0}, 4003 { X86::MOV16ms, "movw", Convert__Mem5_1__Reg1_0, { MCK_SEGMENT_REG, MCK_Mem }, 0}, 4004 { X86::MOV16ri, "movw", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4005 { X86::MOV16mi, "movw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4006 { X86::MOV16o16a, "movw", Convert__AbsMem1_0, { MCK_AbsMem, MCK_AX }, Feature_In32BitMode}, 4007 { X86::MOV16rm, "movw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 4008 { X86::MOV16sm, "movw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_SEGMENT_REG }, 0}, 4009 { X86::MOVZX32_NOREXrr8, "movzbl", Convert__Reg1_1__Reg1_0, { MCK_GR8_NOREX, MCK_GR32_NOREX }, 0}, 4010 { X86::MOVZX32rr8, "movzbl", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR32 }, 0}, 4011 { X86::MOVZX32_NOREXrm8, "movzbl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32_NOREX }, 0}, 4012 { X86::MOVZX32rm8, "movzbl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 4013 { X86::MOVZX64rr8_Q, "movzbq", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR64 }, 0}, 4014 { X86::MOVZX64rm8_Q, "movzbq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 4015 { X86::MOVZX16rr8, "movzbw", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR16 }, 0}, 4016 { X86::MOVZX16rm8, "movzbw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 4017 { X86::MOVZX32rr16, "movzwl", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR32 }, 0}, 4018 { X86::MOVZX32rm16, "movzwl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 4019 { X86::MOVZX64rr16_Q, "movzwq", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR64 }, 0}, 4020 { X86::MOVZX64rm16_Q, "movzwq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 4021 { X86::MOVZX16rr8, "movzx", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR16 }, 0}, 4022 { X86::MOVZX32rr8, "movzx", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR32 }, 0}, 4023 { X86::MOVZX64rr8_Q, "movzx", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR64 }, 0}, 4024 { X86::MOVZX32rr16, "movzx", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR32 }, 0}, 4025 { X86::MOVZX64rr16_Q, "movzx", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR64 }, 0}, 4026 { X86::MOVZX16rm8, "movzx", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 4027 { X86::MPSADBWrri, "mpsadbw", Convert__Reg1_2__Tie0__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32 }, 0}, 4028 { X86::MPSADBWrmi, "mpsadbw", Convert__Reg1_2__Tie0__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32 }, 0}, 4029 { X86::MUL8r, "mulb", Convert__Reg1_0, { MCK_GR8 }, 0}, 4030 { X86::MUL8m, "mulb", Convert__Mem5_0, { MCK_Mem }, 0}, 4031 { X86::MUL32r, "mull", Convert__Reg1_0, { MCK_GR32 }, 0}, 4032 { X86::MUL32m, "mull", Convert__Mem5_0, { MCK_Mem }, 0}, 4033 { X86::MULPDrr, "mulpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4034 { X86::MULPDrm, "mulpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4035 { X86::MULPSrr, "mulps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4036 { X86::MULPSrm, "mulps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4037 { X86::MUL64r, "mulq", Convert__Reg1_0, { MCK_GR64 }, 0}, 4038 { X86::MUL64m, "mulq", Convert__Mem5_0, { MCK_Mem }, 0}, 4039 { X86::MULSDrr, "mulsd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4040 { X86::MULSDrm, "mulsd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4041 { X86::MULSSrr, "mulss", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4042 { X86::MULSSrm, "mulss", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4043 { X86::MUL16r, "mulw", Convert__Reg1_0, { MCK_GR16 }, 0}, 4044 { X86::MUL16m, "mulw", Convert__Mem5_0, { MCK_Mem }, 0}, 4045 { X86::MWAITrr, "mwait", Convert, { }, 0}, 4046 { X86::MWAITrr, "mwait", Convert, { MCK_EAX, MCK_ECX }, Feature_In32BitMode}, 4047 { X86::MWAITrr, "mwait", Convert, { MCK_RAX, MCK_RCX }, Feature_In64BitMode}, 4048 { X86::NEG8r, "negb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 4049 { X86::NEG8m, "negb", Convert__Mem5_0, { MCK_Mem }, 0}, 4050 { X86::NEG32r, "negl", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 4051 { X86::NEG32m, "negl", Convert__Mem5_0, { MCK_Mem }, 0}, 4052 { X86::NEG64r, "negq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 4053 { X86::NEG64m, "negq", Convert__Mem5_0, { MCK_Mem }, 0}, 4054 { X86::NEG16r, "negw", Convert__Reg1_0__Tie0, { MCK_GR16 }, 0}, 4055 { X86::NEG16m, "negw", Convert__Mem5_0, { MCK_Mem }, 0}, 4056 { X86::NOOP, "nop", Convert, { }, 0}, 4057 { X86::NOOPL, "nopl", Convert__Mem5_0, { MCK_Mem }, 0}, 4058 { X86::NOOPW, "nopw", Convert__Mem5_0, { MCK_Mem }, 0}, 4059 { X86::NOT8r, "notb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 4060 { X86::NOT8m, "notb", Convert__Mem5_0, { MCK_Mem }, 0}, 4061 { X86::NOT32r, "notl", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 4062 { X86::NOT32m, "notl", Convert__Mem5_0, { MCK_Mem }, 0}, 4063 { X86::NOT64r, "notq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 4064 { X86::NOT64m, "notq", Convert__Mem5_0, { MCK_Mem }, 0}, 4065 { X86::NOT16r, "notw", Convert__Reg1_0__Tie0, { MCK_GR16 }, 0}, 4066 { X86::NOT16m, "notw", Convert__Mem5_0, { MCK_Mem }, 0}, 4067 { X86::OR8rr, "orb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 4068 { X86::OR8mr, "orb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 4069 { X86::OR8i8, "orb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 4070 { X86::OR8ri, "orb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 4071 { X86::OR8mi, "orb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4072 { X86::OR8rm, "orb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 4073 { X86::OR32rr, "orl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 4074 { X86::OR32mr, "orl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 4075 { X86::OR32ri8, "orl", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 4076 { X86::OR32mi8, "orl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 4077 { X86::OR32i32, "orl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 4078 { X86::OR32ri, "orl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 4079 { X86::OR32mi, "orl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4080 { X86::OR32rm, "orl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 4081 { X86::FsORPDrr, "orpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4082 { X86::ORPDrr, "orpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4083 { X86::FsORPDrm, "orpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4084 { X86::ORPDrm, "orpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4085 { X86::FsORPSrr, "orps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4086 { X86::ORPSrr, "orps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4087 { X86::FsORPSrm, "orps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4088 { X86::ORPSrm, "orps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4089 { X86::OR64rr, "orq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 4090 { X86::OR64mr, "orq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 4091 { X86::OR64ri8, "orq", Convert__Reg1_1__Tie0__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 4092 { X86::OR64mi8, "orq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 4093 { X86::OR64i32, "orq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_RAX }, 0}, 4094 { X86::OR64ri32, "orq", Convert__Reg1_1__Tie0__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 4095 { X86::OR64mi32, "orq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 4096 { X86::OR64rm, "orq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 4097 { X86::OR16rr, "orw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 4098 { X86::OR16mr, "orw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 4099 { X86::OR16ri8, "orw", Convert__Reg1_1__Tie0__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 4100 { X86::OR16mi8, "orw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 4101 { X86::OR16i16, "orw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 4102 { X86::OR16ri, "orw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4103 { X86::OR16mi, "orw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4104 { X86::OR16rm, "orw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 4105 { X86::OUT8rr, "outb", Convert, { MCK_DX }, 0}, 4106 { X86::OUT8ir, "outb", Convert__Imm1_0, { MCK_Imm }, 0}, 4107 { X86::OUT8rr, "outb", Convert, { MCK_AL, MCK_DX }, 0}, 4108 { X86::OUT8ir, "outb", Convert__Imm1_1, { MCK_AL, MCK_Imm }, 0}, 4109 { X86::OUT32rr, "outl", Convert, { MCK_DX }, 0}, 4110 { X86::OUT32ir, "outl", Convert__Imm1_0, { MCK_Imm }, 0}, 4111 { X86::OUT32rr, "outl", Convert, { MCK_EAX, MCK_DX }, 0}, 4112 { X86::OUT32ir, "outl", Convert__Imm1_1, { MCK_EAX, MCK_Imm }, 0}, 4113 { X86::OUTSB, "outsb", Convert, { }, 0}, 4114 { X86::OUTSD, "outsl", Convert, { }, 0}, 4115 { X86::OUTSW, "outsw", Convert, { }, 0}, 4116 { X86::OUT16rr, "outw", Convert, { MCK_DX }, 0}, 4117 { X86::OUT16ir, "outw", Convert__Imm1_0, { MCK_Imm }, 0}, 4118 { X86::OUT16rr, "outw", Convert, { MCK_AX, MCK_DX }, 0}, 4119 { X86::OUT16ir, "outw", Convert__Imm1_1, { MCK_AX, MCK_Imm }, 0}, 4120 { X86::MMX_PABSBrr64, "pabsb", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4121 { X86::PABSBrr128, "pabsb", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4122 { X86::MMX_PABSBrm64, "pabsb", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4123 { X86::PABSBrm128, "pabsb", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4124 { X86::MMX_PABSDrr64, "pabsd", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4125 { X86::PABSDrr128, "pabsd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4126 { X86::MMX_PABSDrm64, "pabsd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4127 { X86::PABSDrm128, "pabsd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4128 { X86::MMX_PABSWrr64, "pabsw", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4129 { X86::PABSWrr128, "pabsw", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4130 { X86::MMX_PABSWrm64, "pabsw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4131 { X86::PABSWrm128, "pabsw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4132 { X86::MMX_PACKSSDWirr, "packssdw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4133 { X86::PACKSSDWrr, "packssdw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4134 { X86::MMX_PACKSSDWirm, "packssdw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4135 { X86::PACKSSDWrm, "packssdw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4136 { X86::MMX_PACKSSWBirr, "packsswb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4137 { X86::PACKSSWBrr, "packsswb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4138 { X86::MMX_PACKSSWBirm, "packsswb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4139 { X86::PACKSSWBrm, "packsswb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4140 { X86::PACKUSDWrr, "packusdw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4141 { X86::PACKUSDWrm, "packusdw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4142 { X86::MMX_PACKUSWBirr, "packuswb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4143 { X86::PACKUSWBrr, "packuswb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4144 { X86::MMX_PACKUSWBirm, "packuswb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4145 { X86::PACKUSWBrm, "packuswb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4146 { X86::MMX_PADDBirr, "paddb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4147 { X86::PADDBrr, "paddb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4148 { X86::MMX_PADDBirm, "paddb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4149 { X86::PADDBrm, "paddb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4150 { X86::MMX_PADDDirr, "paddd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4151 { X86::PADDDrr, "paddd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4152 { X86::MMX_PADDDirm, "paddd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4153 { X86::PADDDrm, "paddd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4154 { X86::MMX_PADDQirr, "paddq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4155 { X86::PADDQrr, "paddq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4156 { X86::MMX_PADDQirm, "paddq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4157 { X86::PADDQrm, "paddq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4158 { X86::MMX_PADDSBirr, "paddsb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4159 { X86::PADDSBrr, "paddsb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4160 { X86::MMX_PADDSBirm, "paddsb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4161 { X86::PADDSBrm, "paddsb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4162 { X86::MMX_PADDSWirr, "paddsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4163 { X86::PADDSWrr, "paddsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4164 { X86::MMX_PADDSWirm, "paddsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4165 { X86::PADDSWrm, "paddsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4166 { X86::MMX_PADDUSBirr, "paddusb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4167 { X86::PADDUSBrr, "paddusb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4168 { X86::MMX_PADDUSBirm, "paddusb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4169 { X86::PADDUSBrm, "paddusb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4170 { X86::MMX_PADDUSWirr, "paddusw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4171 { X86::PADDUSWrr, "paddusw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4172 { X86::MMX_PADDUSWirm, "paddusw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4173 { X86::PADDUSWrm, "paddusw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4174 { X86::MMX_PADDWirr, "paddw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4175 { X86::PADDWrr, "paddw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4176 { X86::MMX_PADDWirm, "paddw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4177 { X86::PADDWrm, "paddw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4178 { X86::MMX_PALIGNR64irr, "palignr", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR64, MCK_VR64 }, 0}, 4179 { X86::PALIGNR128rr, "palignr", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4180 { X86::MMX_PALIGNR64irm, "palignr", Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR64 }, 0}, 4181 { X86::PALIGNR128rm, "palignr", Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4182 { X86::MMX_PANDirr, "pand", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4183 { X86::PANDrr, "pand", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4184 { X86::MMX_PANDirm, "pand", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4185 { X86::PANDrm, "pand", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4186 { X86::MMX_PANDNirr, "pandn", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4187 { X86::PANDNrr, "pandn", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4188 { X86::MMX_PANDNirm, "pandn", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4189 { X86::PANDNrm, "pandn", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4190 { X86::PAUSE, "pause", Convert, { }, 0}, 4191 { X86::MMX_PAVGBirr, "pavgb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4192 { X86::PAVGBrr, "pavgb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4193 { X86::MMX_PAVGBirm, "pavgb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4194 { X86::PAVGBrm, "pavgb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4195 { X86::PAVGUSBrr, "pavgusb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4196 { X86::PAVGUSBrm, "pavgusb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4197 { X86::MMX_PAVGWirr, "pavgw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4198 { X86::PAVGWrr, "pavgw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4199 { X86::MMX_PAVGWirm, "pavgw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4200 { X86::PAVGWrm, "pavgw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4201 { X86::PBLENDVBrr0, "pblendvb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4202 { X86::PBLENDVBrm0, "pblendvb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4203 { X86::PBLENDWrri, "pblendw", Convert__Reg1_2__Tie0__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32 }, 0}, 4204 { X86::PBLENDWrmi, "pblendw", Convert__Reg1_2__Tie0__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32 }, 0}, 4205 { X86::PCLMULQDQrr, "pclmulhqhqdq", Convert__Reg1_1__Tie0__Reg1_0__imm17, { MCK_FR32, MCK_FR32 }, 0}, 4206 { X86::PCLMULQDQrm, "pclmulhqhqdq", Convert__Reg1_1__Tie0__Mem5_0__imm17, { MCK_Mem, MCK_FR32 }, 0}, 4207 { X86::PCLMULQDQrr, "pclmulhqlqdq", Convert__Reg1_1__Tie0__Reg1_0__imm1, { MCK_FR32, MCK_FR32 }, 0}, 4208 { X86::PCLMULQDQrm, "pclmulhqlqdq", Convert__Reg1_1__Tie0__Mem5_0__imm1, { MCK_Mem, MCK_FR32 }, 0}, 4209 { X86::PCLMULQDQrr, "pclmullqhqdq", Convert__Reg1_1__Tie0__Reg1_0__imm16, { MCK_FR32, MCK_FR32 }, 0}, 4210 { X86::PCLMULQDQrm, "pclmullqhqdq", Convert__Reg1_1__Tie0__Mem5_0__imm16, { MCK_Mem, MCK_FR32 }, 0}, 4211 { X86::PCLMULQDQrr, "pclmullqlqdq", Convert__Reg1_1__Tie0__Reg1_0__imm0, { MCK_FR32, MCK_FR32 }, 0}, 4212 { X86::PCLMULQDQrm, "pclmullqlqdq", Convert__Reg1_1__Tie0__Mem5_0__imm0, { MCK_Mem, MCK_FR32 }, 0}, 4213 { X86::PCLMULQDQrr, "pclmulqdq", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4214 { X86::PCLMULQDQrm, "pclmulqdq", Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4215 { X86::MMX_PCMPEQBirr, "pcmpeqb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4216 { X86::PCMPEQBrr, "pcmpeqb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4217 { X86::MMX_PCMPEQBirm, "pcmpeqb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4218 { X86::PCMPEQBrm, "pcmpeqb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4219 { X86::MMX_PCMPEQDirr, "pcmpeqd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4220 { X86::PCMPEQDrr, "pcmpeqd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4221 { X86::MMX_PCMPEQDirm, "pcmpeqd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4222 { X86::PCMPEQDrm, "pcmpeqd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4223 { X86::PCMPEQQrr, "pcmpeqq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4224 { X86::PCMPEQQrm, "pcmpeqq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4225 { X86::MMX_PCMPEQWirr, "pcmpeqw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4226 { X86::PCMPEQWrr, "pcmpeqw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4227 { X86::MMX_PCMPEQWirm, "pcmpeqw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4228 { X86::PCMPEQWrm, "pcmpeqw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4229 { X86::PCMPESTRIArr, "pcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4230 { X86::PCMPESTRICrr, "pcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4231 { X86::PCMPESTRIOrr, "pcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4232 { X86::PCMPESTRISrr, "pcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4233 { X86::PCMPESTRIZrr, "pcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4234 { X86::PCMPESTRIrr, "pcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4235 { X86::PCMPESTRIArm, "pcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4236 { X86::PCMPESTRICrm, "pcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4237 { X86::PCMPESTRIOrm, "pcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4238 { X86::PCMPESTRISrm, "pcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4239 { X86::PCMPESTRIZrm, "pcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4240 { X86::PCMPESTRIrm, "pcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4241 { X86::PCMPESTRM128rr, "pcmpestrm", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4242 { X86::PCMPESTRM128rm, "pcmpestrm", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4243 { X86::MMX_PCMPGTBirr, "pcmpgtb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4244 { X86::PCMPGTBrr, "pcmpgtb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4245 { X86::MMX_PCMPGTBirm, "pcmpgtb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4246 { X86::PCMPGTBrm, "pcmpgtb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4247 { X86::MMX_PCMPGTDirr, "pcmpgtd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4248 { X86::PCMPGTDrr, "pcmpgtd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4249 { X86::MMX_PCMPGTDirm, "pcmpgtd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4250 { X86::PCMPGTDrm, "pcmpgtd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4251 { X86::PCMPGTQrr, "pcmpgtq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4252 { X86::PCMPGTQrm, "pcmpgtq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4253 { X86::MMX_PCMPGTWirr, "pcmpgtw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4254 { X86::PCMPGTWrr, "pcmpgtw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4255 { X86::MMX_PCMPGTWirm, "pcmpgtw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4256 { X86::PCMPGTWrm, "pcmpgtw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4257 { X86::PCMPISTRIArr, "pcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4258 { X86::PCMPISTRICrr, "pcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4259 { X86::PCMPISTRIOrr, "pcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4260 { X86::PCMPISTRISrr, "pcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4261 { X86::PCMPISTRIZrr, "pcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4262 { X86::PCMPISTRIrr, "pcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4263 { X86::PCMPISTRIArm, "pcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4264 { X86::PCMPISTRICrm, "pcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4265 { X86::PCMPISTRIOrm, "pcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4266 { X86::PCMPISTRISrm, "pcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4267 { X86::PCMPISTRIZrm, "pcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4268 { X86::PCMPISTRIrm, "pcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4269 { X86::PCMPISTRM128rr, "pcmpistrm", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4270 { X86::PCMPISTRM128rm, "pcmpistrm", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4271 { X86::PEXTRBrr, "pextrb", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR32 }, 0}, 4272 { X86::PEXTRBmr, "pextrb", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 4273 { X86::PEXTRDrr, "pextrd", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR32 }, 0}, 4274 { X86::PEXTRDmr, "pextrd", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 4275 { X86::PEXTRQrr, "pextrq", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR64 }, 0}, 4276 { X86::PEXTRQmr, "pextrq", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 4277 { X86::MMX_PEXTRWirri, "pextrw", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR64, MCK_GR32 }, 0}, 4278 { X86::PEXTRWri, "pextrw", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR32 }, 0}, 4279 { X86::PEXTRWmr, "pextrw", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 4280 { X86::PF2IDrr, "pf2id", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4281 { X86::PF2IDrm, "pf2id", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4282 { X86::PF2IWrr, "pf2iw", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4283 { X86::PF2IWrm, "pf2iw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4284 { X86::PFACCrr, "pfacc", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4285 { X86::PFACCrm, "pfacc", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4286 { X86::PFADDrr, "pfadd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4287 { X86::PFADDrm, "pfadd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4288 { X86::PFCMPEQrr, "pfcmpeq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4289 { X86::PFCMPEQrm, "pfcmpeq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4290 { X86::PFCMPGErr, "pfcmpge", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4291 { X86::PFCMPGErm, "pfcmpge", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4292 { X86::PFCMPGTrr, "pfcmpgt", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4293 { X86::PFCMPGTrm, "pfcmpgt", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4294 { X86::PFMAXrr, "pfmax", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4295 { X86::PFMAXrm, "pfmax", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4296 { X86::PFMINrr, "pfmin", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4297 { X86::PFMINrm, "pfmin", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4298 { X86::PFMULrr, "pfmul", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4299 { X86::PFMULrm, "pfmul", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4300 { X86::PFNACCrr, "pfnacc", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4301 { X86::PFNACCrm, "pfnacc", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4302 { X86::PFPNACCrr, "pfpnacc", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4303 { X86::PFPNACCrm, "pfpnacc", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4304 { X86::PFRCPrr, "pfrcp", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4305 { X86::PFRCPrm, "pfrcp", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4306 { X86::PFRCPIT1rr, "pfrcpit1", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4307 { X86::PFRCPIT1rm, "pfrcpit1", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4308 { X86::PFRCPIT2rr, "pfrcpit2", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4309 { X86::PFRCPIT2rm, "pfrcpit2", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4310 { X86::PFRSQIT1rr, "pfrsqit1", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4311 { X86::PFRSQIT1rm, "pfrsqit1", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4312 { X86::PFRSQRTrr, "pfrsqrt", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4313 { X86::PFRSQRTrm, "pfrsqrt", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4314 { X86::PFSUBrr, "pfsub", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4315 { X86::PFSUBrm, "pfsub", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4316 { X86::PFSUBRrr, "pfsubr", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4317 { X86::PFSUBRrm, "pfsubr", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4318 { X86::MMX_PHADDrr64, "phaddd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4319 { X86::PHADDDrr128, "phaddd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4320 { X86::MMX_PHADDrm64, "phaddd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4321 { X86::PHADDDrm128, "phaddd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4322 { X86::MMX_PHADDSWrr64, "phaddsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4323 { X86::PHADDSWrr128, "phaddsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4324 { X86::MMX_PHADDSWrm64, "phaddsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4325 { X86::PHADDSWrm128, "phaddsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4326 { X86::MMX_PHADDWrr64, "phaddw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4327 { X86::PHADDWrr128, "phaddw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4328 { X86::MMX_PHADDWrm64, "phaddw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4329 { X86::PHADDWrm128, "phaddw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4330 { X86::PHMINPOSUWrr128, "phminposuw", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4331 { X86::PHMINPOSUWrm128, "phminposuw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4332 { X86::MMX_PHSUBDrr64, "phsubd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4333 { X86::PHSUBDrr128, "phsubd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4334 { X86::MMX_PHSUBDrm64, "phsubd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4335 { X86::PHSUBDrm128, "phsubd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4336 { X86::MMX_PHSUBSWrr64, "phsubsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4337 { X86::PHSUBSWrr128, "phsubsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4338 { X86::MMX_PHSUBSWrm64, "phsubsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4339 { X86::PHSUBSWrm128, "phsubsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4340 { X86::MMX_PHSUBWrr64, "phsubw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4341 { X86::PHSUBWrr128, "phsubw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4342 { X86::MMX_PHSUBWrm64, "phsubw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4343 { X86::PHSUBWrm128, "phsubw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4344 { X86::PI2FDrr, "pi2fd", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4345 { X86::PI2FDrm, "pi2fd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4346 { X86::PI2FWrr, "pi2fw", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4347 { X86::PI2FWrm, "pi2fw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4348 { X86::PINSRBrr, "pinsrb", Convert__Reg1_2__Tie0__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32, MCK_FR32 }, 0}, 4349 { X86::PINSRBrm, "pinsrb", Convert__Reg1_2__Tie0__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 4350 { X86::PINSRDrr, "pinsrd", Convert__Reg1_2__Tie0__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32, MCK_FR32 }, 0}, 4351 { X86::PINSRDrm, "pinsrd", Convert__Reg1_2__Tie0__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 4352 { X86::PINSRQrr, "pinsrq", Convert__Reg1_2__Tie0__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR64, MCK_FR32 }, 0}, 4353 { X86::PINSRQrm, "pinsrq", Convert__Reg1_2__Tie0__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 4354 { X86::MMX_PINSRWirri, "pinsrw", Convert__Reg1_2__Tie0__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32, MCK_VR64 }, 0}, 4355 { X86::PINSRWrri, "pinsrw", Convert__Reg1_2__Tie0__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32, MCK_FR32 }, 0}, 4356 { X86::MMX_PINSRWirmi, "pinsrw", Convert__Reg1_2__Tie0__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_VR64 }, 0}, 4357 { X86::PINSRWrmi, "pinsrw", Convert__Reg1_2__Tie0__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 4358 { X86::MMX_PMADDUBSWrr64, "pmaddubsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4359 { X86::PMADDUBSWrr128, "pmaddubsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4360 { X86::MMX_PMADDUBSWrm64, "pmaddubsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4361 { X86::PMADDUBSWrm128, "pmaddubsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4362 { X86::MMX_PMADDWDirr, "pmaddwd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4363 { X86::PMADDWDrr, "pmaddwd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4364 { X86::MMX_PMADDWDirm, "pmaddwd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4365 { X86::PMADDWDrm, "pmaddwd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4366 { X86::PMAXSBrr, "pmaxsb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4367 { X86::PMAXSBrm, "pmaxsb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4368 { X86::PMAXSDrr, "pmaxsd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4369 { X86::PMAXSDrm, "pmaxsd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4370 { X86::MMX_PMAXSWirr, "pmaxsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4371 { X86::PMAXSWrr, "pmaxsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4372 { X86::MMX_PMAXSWirm, "pmaxsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4373 { X86::PMAXSWrm, "pmaxsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4374 { X86::MMX_PMAXUBirr, "pmaxub", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4375 { X86::PMAXUBrr, "pmaxub", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4376 { X86::MMX_PMAXUBirm, "pmaxub", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4377 { X86::PMAXUBrm, "pmaxub", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4378 { X86::PMAXUDrr, "pmaxud", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4379 { X86::PMAXUDrm, "pmaxud", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4380 { X86::PMAXUWrr, "pmaxuw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4381 { X86::PMAXUWrm, "pmaxuw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4382 { X86::PMINSBrr, "pminsb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4383 { X86::PMINSBrm, "pminsb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4384 { X86::PMINSDrr, "pminsd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4385 { X86::PMINSDrm, "pminsd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4386 { X86::MMX_PMINSWirr, "pminsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4387 { X86::PMINSWrr, "pminsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4388 { X86::MMX_PMINSWirm, "pminsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4389 { X86::PMINSWrm, "pminsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4390 { X86::MMX_PMINUBirr, "pminub", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4391 { X86::PMINUBrr, "pminub", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4392 { X86::MMX_PMINUBirm, "pminub", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4393 { X86::PMINUBrm, "pminub", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4394 { X86::PMINUDrr, "pminud", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4395 { X86::PMINUDrm, "pminud", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4396 { X86::PMINUWrr, "pminuw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4397 { X86::PMINUWrm, "pminuw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4398 { X86::MMX_PMOVMSKBrr, "pmovmskb", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_GR32 }, 0}, 4399 { X86::PMOVMSKBrr, "pmovmskb", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 4400 { X86::PMOVSXBDrr, "pmovsxbd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4401 { X86::PMOVSXBDrm, "pmovsxbd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4402 { X86::PMOVSXBQrr, "pmovsxbq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4403 { X86::PMOVSXBQrm, "pmovsxbq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4404 { X86::PMOVSXBWrr, "pmovsxbw", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4405 { X86::PMOVSXBWrm, "pmovsxbw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4406 { X86::PMOVSXDQrr, "pmovsxdq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4407 { X86::PMOVSXDQrm, "pmovsxdq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4408 { X86::PMOVSXWDrr, "pmovsxwd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4409 { X86::PMOVSXWDrm, "pmovsxwd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4410 { X86::PMOVSXWQrr, "pmovsxwq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4411 { X86::PMOVSXWQrm, "pmovsxwq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4412 { X86::PMOVZXBDrr, "pmovzxbd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4413 { X86::PMOVZXBDrm, "pmovzxbd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4414 { X86::PMOVZXBQrr, "pmovzxbq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4415 { X86::PMOVZXBQrm, "pmovzxbq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4416 { X86::PMOVZXBWrr, "pmovzxbw", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4417 { X86::PMOVZXBWrm, "pmovzxbw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4418 { X86::PMOVZXDQrr, "pmovzxdq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4419 { X86::PMOVZXDQrm, "pmovzxdq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4420 { X86::PMOVZXWDrr, "pmovzxwd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4421 { X86::PMOVZXWDrm, "pmovzxwd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4422 { X86::PMOVZXWQrr, "pmovzxwq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4423 { X86::PMOVZXWQrm, "pmovzxwq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4424 { X86::PMULDQrr, "pmuldq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4425 { X86::PMULDQrm, "pmuldq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4426 { X86::MMX_PMULHRSWrr64, "pmulhrsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4427 { X86::PMULHRSWrr128, "pmulhrsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4428 { X86::MMX_PMULHRSWrm64, "pmulhrsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4429 { X86::PMULHRSWrm128, "pmulhrsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4430 { X86::PMULHRWrr, "pmulhrw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4431 { X86::PMULHRWrm, "pmulhrw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4432 { X86::MMX_PMULHUWirr, "pmulhuw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4433 { X86::PMULHUWrr, "pmulhuw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4434 { X86::MMX_PMULHUWirm, "pmulhuw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4435 { X86::PMULHUWrm, "pmulhuw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4436 { X86::MMX_PMULHWirr, "pmulhw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4437 { X86::PMULHWrr, "pmulhw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4438 { X86::MMX_PMULHWirm, "pmulhw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4439 { X86::PMULHWrm, "pmulhw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4440 { X86::PMULLDrr, "pmulld", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4441 { X86::PMULLDrm, "pmulld", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4442 { X86::MMX_PMULLWirr, "pmullw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4443 { X86::PMULLWrr, "pmullw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4444 { X86::MMX_PMULLWirm, "pmullw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4445 { X86::PMULLWrm, "pmullw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4446 { X86::MMX_PMULUDQirr, "pmuludq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4447 { X86::PMULUDQrr, "pmuludq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4448 { X86::MMX_PMULUDQirm, "pmuludq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4449 { X86::PMULUDQrm, "pmuludq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4450 { X86::POPA32, "popal", Convert, { }, Feature_In32BitMode}, 4451 { X86::POPCNT32rr, "popcntl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 4452 { X86::POPCNT32rm, "popcntl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 4453 { X86::POPCNT64rr, "popcntq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 4454 { X86::POPCNT64rm, "popcntq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 4455 { X86::POPCNT16rr, "popcntw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 4456 { X86::POPCNT16rm, "popcntw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 4457 { X86::POPF32, "popfl", Convert, { }, Feature_In32BitMode}, 4458 { X86::POPF64, "popfq", Convert, { }, Feature_In64BitMode}, 4459 { X86::POPF16, "popfw", Convert, { }, 0}, 4460 { X86::POP32r, "popl", Convert__Reg1_0, { MCK_GR32 }, 0}, 4461 { X86::POP32rmr, "popl", Convert__Reg1_0, { MCK_GR32 }, 0}, 4462 { X86::POPDS32, "popl", Convert, { MCK_DS }, Feature_In32BitMode}, 4463 { X86::POPSS32, "popl", Convert, { MCK_SS }, Feature_In32BitMode}, 4464 { X86::POPES32, "popl", Convert, { MCK_ES }, Feature_In32BitMode}, 4465 { X86::POPFS32, "popl", Convert, { MCK_FS }, Feature_In32BitMode}, 4466 { X86::POPGS32, "popl", Convert, { MCK_GS }, Feature_In32BitMode}, 4467 { X86::POP32rmm, "popl", Convert__Mem5_0, { MCK_Mem }, 0}, 4468 { X86::POP64r, "popq", Convert__Reg1_0, { MCK_GR64 }, 0}, 4469 { X86::POP64rmr, "popq", Convert__Reg1_0, { MCK_GR64 }, 0}, 4470 { X86::POPFS64, "popq", Convert, { MCK_FS }, 0}, 4471 { X86::POPGS64, "popq", Convert, { MCK_GS }, 0}, 4472 { X86::POP64rmm, "popq", Convert__Mem5_0, { MCK_Mem }, 0}, 4473 { X86::POP16r, "popw", Convert__Reg1_0, { MCK_GR16 }, 0}, 4474 { X86::POP16rmr, "popw", Convert__Reg1_0, { MCK_GR16 }, 0}, 4475 { X86::POPDS16, "popw", Convert, { MCK_DS }, Feature_In32BitMode}, 4476 { X86::POPSS16, "popw", Convert, { MCK_SS }, Feature_In32BitMode}, 4477 { X86::POPES16, "popw", Convert, { MCK_ES }, Feature_In32BitMode}, 4478 { X86::POPFS16, "popw", Convert, { MCK_FS }, 0}, 4479 { X86::POPGS16, "popw", Convert, { MCK_GS }, 0}, 4480 { X86::POP16rmm, "popw", Convert__Mem5_0, { MCK_Mem }, 0}, 4481 { X86::MMX_PORirr, "por", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4482 { X86::PORrr, "por", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4483 { X86::MMX_PORirm, "por", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4484 { X86::PORrm, "por", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4485 { X86::PREFETCH, "prefetch", Convert__Mem5_0, { MCK_Mem }, 0}, 4486 { X86::PREFETCHNTA, "prefetchnta", Convert__Mem5_0, { MCK_Mem }, 0}, 4487 { X86::PREFETCHT0, "prefetcht0", Convert__Mem5_0, { MCK_Mem }, 0}, 4488 { X86::PREFETCHT1, "prefetcht1", Convert__Mem5_0, { MCK_Mem }, 0}, 4489 { X86::PREFETCHT2, "prefetcht2", Convert__Mem5_0, { MCK_Mem }, 0}, 4490 { X86::PREFETCHW, "prefetchw", Convert__Mem5_0, { MCK_Mem }, 0}, 4491 { X86::MMX_PSADBWirr, "psadbw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4492 { X86::PSADBWrr, "psadbw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4493 { X86::MMX_PSADBWirm, "psadbw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4494 { X86::PSADBWrm, "psadbw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4495 { X86::MMX_PSHUFBrr64, "pshufb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4496 { X86::PSHUFBrr128, "pshufb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4497 { X86::MMX_PSHUFBrm64, "pshufb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4498 { X86::PSHUFBrm128, "pshufb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4499 { X86::PSHUFDri, "pshufd", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4500 { X86::PSHUFDmi, "pshufd", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4501 { X86::PSHUFHWri, "pshufhw", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4502 { X86::PSHUFHWmi, "pshufhw", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4503 { X86::PSHUFLWri, "pshuflw", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4504 { X86::PSHUFLWmi, "pshuflw", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4505 { X86::MMX_PSHUFWri, "pshufw", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR64, MCK_VR64 }, 0}, 4506 { X86::MMX_PSHUFWmi, "pshufw", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR64 }, 0}, 4507 { X86::MMX_PSIGNBrr64, "psignb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4508 { X86::PSIGNBrr128, "psignb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4509 { X86::MMX_PSIGNBrm64, "psignb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4510 { X86::PSIGNBrm128, "psignb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4511 { X86::MMX_PSIGNDrr64, "psignd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4512 { X86::PSIGNDrr128, "psignd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4513 { X86::MMX_PSIGNDrm64, "psignd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4514 { X86::PSIGNDrm128, "psignd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4515 { X86::MMX_PSIGNWrr64, "psignw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4516 { X86::PSIGNWrr128, "psignw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4517 { X86::MMX_PSIGNWrm64, "psignw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4518 { X86::PSIGNWrm128, "psignw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4519 { X86::MMX_PSLLDrr, "pslld", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4520 { X86::PSLLDrr, "pslld", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4521 { X86::MMX_PSLLDri, "pslld", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR64 }, 0}, 4522 { X86::PSLLDri, "pslld", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4523 { X86::MMX_PSLLDrm, "pslld", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4524 { X86::PSLLDrm, "pslld", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4525 { X86::PSLLDQri, "pslldq", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4526 { X86::MMX_PSLLQrr, "psllq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4527 { X86::PSLLQrr, "psllq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4528 { X86::MMX_PSLLQri, "psllq", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR64 }, 0}, 4529 { X86::PSLLQri, "psllq", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4530 { X86::MMX_PSLLQrm, "psllq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4531 { X86::PSLLQrm, "psllq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4532 { X86::MMX_PSLLWrr, "psllw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4533 { X86::PSLLWrr, "psllw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4534 { X86::MMX_PSLLWri, "psllw", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR64 }, 0}, 4535 { X86::PSLLWri, "psllw", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4536 { X86::MMX_PSLLWrm, "psllw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4537 { X86::PSLLWrm, "psllw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4538 { X86::MMX_PSRADrr, "psrad", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4539 { X86::PSRADrr, "psrad", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4540 { X86::MMX_PSRADri, "psrad", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR64 }, 0}, 4541 { X86::PSRADri, "psrad", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4542 { X86::MMX_PSRADrm, "psrad", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4543 { X86::PSRADrm, "psrad", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4544 { X86::MMX_PSRAWrr, "psraw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4545 { X86::PSRAWrr, "psraw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4546 { X86::MMX_PSRAWri, "psraw", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR64 }, 0}, 4547 { X86::PSRAWri, "psraw", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4548 { X86::MMX_PSRAWrm, "psraw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4549 { X86::PSRAWrm, "psraw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4550 { X86::MMX_PSRLDrr, "psrld", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4551 { X86::PSRLDrr, "psrld", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4552 { X86::MMX_PSRLDri, "psrld", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR64 }, 0}, 4553 { X86::PSRLDri, "psrld", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4554 { X86::MMX_PSRLDrm, "psrld", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4555 { X86::PSRLDrm, "psrld", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4556 { X86::PSRLDQri, "psrldq", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4557 { X86::MMX_PSRLQrr, "psrlq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4558 { X86::PSRLQrr, "psrlq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4559 { X86::MMX_PSRLQri, "psrlq", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR64 }, 0}, 4560 { X86::PSRLQri, "psrlq", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4561 { X86::MMX_PSRLQrm, "psrlq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4562 { X86::PSRLQrm, "psrlq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4563 { X86::MMX_PSRLWrr, "psrlw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4564 { X86::PSRLWrr, "psrlw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4565 { X86::MMX_PSRLWri, "psrlw", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR64 }, 0}, 4566 { X86::PSRLWri, "psrlw", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32 }, 0}, 4567 { X86::MMX_PSRLWrm, "psrlw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4568 { X86::PSRLWrm, "psrlw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4569 { X86::MMX_PSUBBirr, "psubb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4570 { X86::PSUBBrr, "psubb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4571 { X86::MMX_PSUBBirm, "psubb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4572 { X86::PSUBBrm, "psubb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4573 { X86::MMX_PSUBDirr, "psubd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4574 { X86::PSUBDrr, "psubd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4575 { X86::MMX_PSUBDirm, "psubd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4576 { X86::PSUBDrm, "psubd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4577 { X86::MMX_PSUBQirr, "psubq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4578 { X86::PSUBQrr, "psubq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4579 { X86::MMX_PSUBQirm, "psubq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4580 { X86::PSUBQrm, "psubq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4581 { X86::MMX_PSUBSBirr, "psubsb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4582 { X86::PSUBSBrr, "psubsb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4583 { X86::MMX_PSUBSBirm, "psubsb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4584 { X86::PSUBSBrm, "psubsb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4585 { X86::MMX_PSUBSWirr, "psubsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4586 { X86::PSUBSWrr, "psubsw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4587 { X86::MMX_PSUBSWirm, "psubsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4588 { X86::PSUBSWrm, "psubsw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4589 { X86::MMX_PSUBUSBirr, "psubusb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4590 { X86::PSUBUSBrr, "psubusb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4591 { X86::MMX_PSUBUSBirm, "psubusb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4592 { X86::PSUBUSBrm, "psubusb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4593 { X86::MMX_PSUBUSWirr, "psubusw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4594 { X86::PSUBUSWrr, "psubusw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4595 { X86::MMX_PSUBUSWirm, "psubusw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4596 { X86::PSUBUSWrm, "psubusw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4597 { X86::MMX_PSUBWirr, "psubw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4598 { X86::PSUBWrr, "psubw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4599 { X86::MMX_PSUBWirm, "psubw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4600 { X86::PSUBWrm, "psubw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4601 { X86::PSWAPDrr, "pswapd", Convert__Reg1_1__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4602 { X86::PSWAPDrm, "pswapd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4603 { X86::PTESTrr, "ptest", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4604 { X86::PTESTrm, "ptest", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4605 { X86::MMX_PUNPCKHBWirr, "punpckhbw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4606 { X86::PUNPCKHBWrr, "punpckhbw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4607 { X86::MMX_PUNPCKHBWirm, "punpckhbw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4608 { X86::PUNPCKHBWrm, "punpckhbw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4609 { X86::MMX_PUNPCKHDQirr, "punpckhdq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4610 { X86::PUNPCKHDQrr, "punpckhdq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4611 { X86::MMX_PUNPCKHDQirm, "punpckhdq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4612 { X86::PUNPCKHDQrm, "punpckhdq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4613 { X86::PUNPCKHQDQrr, "punpckhqdq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4614 { X86::PUNPCKHQDQrm, "punpckhqdq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4615 { X86::MMX_PUNPCKHWDirr, "punpckhwd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4616 { X86::PUNPCKHWDrr, "punpckhwd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4617 { X86::MMX_PUNPCKHWDirm, "punpckhwd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4618 { X86::PUNPCKHWDrm, "punpckhwd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4619 { X86::MMX_PUNPCKLBWirr, "punpcklbw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4620 { X86::PUNPCKLBWrr, "punpcklbw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4621 { X86::MMX_PUNPCKLBWirm, "punpcklbw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4622 { X86::PUNPCKLBWrm, "punpcklbw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4623 { X86::MMX_PUNPCKLDQirr, "punpckldq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4624 { X86::PUNPCKLDQrr, "punpckldq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4625 { X86::MMX_PUNPCKLDQirm, "punpckldq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4626 { X86::PUNPCKLDQrm, "punpckldq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4627 { X86::PUNPCKLQDQrr, "punpcklqdq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4628 { X86::PUNPCKLQDQrm, "punpcklqdq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4629 { X86::MMX_PUNPCKLWDirr, "punpcklwd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4630 { X86::PUNPCKLWDrr, "punpcklwd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4631 { X86::MMX_PUNPCKLWDirm, "punpcklwd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4632 { X86::PUNPCKLWDrm, "punpcklwd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4633 { X86::PUSHA32, "pushal", Convert, { }, Feature_In32BitMode}, 4634 { X86::PUSHF32, "pushfl", Convert, { }, Feature_In32BitMode}, 4635 { X86::PUSHF64, "pushfq", Convert, { }, Feature_In64BitMode}, 4636 { X86::PUSHF16, "pushfw", Convert, { }, 0}, 4637 { X86::PUSH32r, "pushl", Convert__Reg1_0, { MCK_GR32 }, 0}, 4638 { X86::PUSH32rmr, "pushl", Convert__Reg1_0, { MCK_GR32 }, 0}, 4639 { X86::PUSHCS32, "pushl", Convert, { MCK_CS }, Feature_In32BitMode}, 4640 { X86::PUSHDS32, "pushl", Convert, { MCK_DS }, Feature_In32BitMode}, 4641 { X86::PUSHSS32, "pushl", Convert, { MCK_SS }, Feature_In32BitMode}, 4642 { X86::PUSHES32, "pushl", Convert, { MCK_ES }, Feature_In32BitMode}, 4643 { X86::PUSHFS32, "pushl", Convert, { MCK_FS }, Feature_In32BitMode}, 4644 { X86::PUSHGS32, "pushl", Convert, { MCK_GS }, Feature_In32BitMode}, 4645 { X86::PUSHi8, "pushl", Convert__ImmSExti32i81_0, { MCK_ImmSExti32i8 }, 0}, 4646 { X86::PUSHi32, "pushl", Convert__Imm1_0, { MCK_Imm }, 0}, 4647 { X86::PUSH32rmm, "pushl", Convert__Mem5_0, { MCK_Mem }, 0}, 4648 { X86::PUSH64r, "pushq", Convert__Reg1_0, { MCK_GR64 }, 0}, 4649 { X86::PUSH64rmr, "pushq", Convert__Reg1_0, { MCK_GR64 }, 0}, 4650 { X86::PUSHFS64, "pushq", Convert, { MCK_FS }, 0}, 4651 { X86::PUSHGS64, "pushq", Convert, { MCK_GS }, 0}, 4652 { X86::PUSH64i8, "pushq", Convert__ImmSExti64i81_0, { MCK_ImmSExti64i8 }, 0}, 4653 { X86::PUSH64i32, "pushq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32 }, 0}, 4654 { X86::PUSH64i16, "pushq", Convert__Imm1_0, { MCK_Imm }, 0}, 4655 { X86::PUSH64rmm, "pushq", Convert__Mem5_0, { MCK_Mem }, 0}, 4656 { X86::PUSH16r, "pushw", Convert__Reg1_0, { MCK_GR16 }, 0}, 4657 { X86::PUSH16rmr, "pushw", Convert__Reg1_0, { MCK_GR16 }, 0}, 4658 { X86::PUSHCS16, "pushw", Convert, { MCK_CS }, Feature_In32BitMode}, 4659 { X86::PUSHDS16, "pushw", Convert, { MCK_DS }, Feature_In32BitMode}, 4660 { X86::PUSHSS16, "pushw", Convert, { MCK_SS }, Feature_In32BitMode}, 4661 { X86::PUSHES16, "pushw", Convert, { MCK_ES }, Feature_In32BitMode}, 4662 { X86::PUSHFS16, "pushw", Convert, { MCK_FS }, 0}, 4663 { X86::PUSHGS16, "pushw", Convert, { MCK_GS }, 0}, 4664 { X86::PUSHi16, "pushw", Convert__Imm1_0, { MCK_Imm }, 0}, 4665 { X86::PUSH16rmm, "pushw", Convert__Mem5_0, { MCK_Mem }, 0}, 4666 { X86::MMX_PXORirr, "pxor", Convert__Reg1_1__Tie0__Reg1_0, { MCK_VR64, MCK_VR64 }, 0}, 4667 { X86::PXORrr, "pxor", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4668 { X86::MMX_PXORirm, "pxor", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_VR64 }, 0}, 4669 { X86::PXORrm, "pxor", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4670 { X86::RCL8r1, "rclb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 4671 { X86::RCL8m1, "rclb", Convert__Mem5_0, { MCK_Mem }, 0}, 4672 { X86::RCL8rCL, "rclb", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR8 }, 0}, 4673 { X86::RCL8mCL, "rclb", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4674 { X86::RCL8ri, "rclb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 4675 { X86::RCL8mi, "rclb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4676 { X86::RCL32r1, "rcll", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 4677 { X86::RCL32m1, "rcll", Convert__Mem5_0, { MCK_Mem }, 0}, 4678 { X86::RCL32rCL, "rcll", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR32 }, 0}, 4679 { X86::RCL32mCL, "rcll", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4680 { X86::RCL32ri, "rcll", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 4681 { X86::RCL32mi, "rcll", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4682 { X86::RCL64r1, "rclq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 4683 { X86::RCL64m1, "rclq", Convert__Mem5_0, { MCK_Mem }, 0}, 4684 { X86::RCL64rCL, "rclq", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR64 }, 0}, 4685 { X86::RCL64mCL, "rclq", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4686 { X86::RCL64ri, "rclq", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR64 }, 0}, 4687 { X86::RCL64mi, "rclq", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4688 { X86::RCL16r1, "rclw", Convert__Reg1_0__Tie0, { MCK_GR16 }, 0}, 4689 { X86::RCL16m1, "rclw", Convert__Mem5_0, { MCK_Mem }, 0}, 4690 { X86::RCL16rCL, "rclw", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR16 }, 0}, 4691 { X86::RCL16mCL, "rclw", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4692 { X86::RCL16ri, "rclw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4693 { X86::RCL16mi, "rclw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4694 { X86::RCPPSr, "rcpps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4695 { X86::RCPPSm, "rcpps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4696 { X86::RCPSSr, "rcpss", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4697 { X86::RCPSSm, "rcpss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4698 { X86::RCR8r1, "rcrb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 4699 { X86::RCR8m1, "rcrb", Convert__Mem5_0, { MCK_Mem }, 0}, 4700 { X86::RCR8rCL, "rcrb", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR8 }, 0}, 4701 { X86::RCR8mCL, "rcrb", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4702 { X86::RCR8ri, "rcrb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 4703 { X86::RCR8mi, "rcrb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4704 { X86::RCR32r1, "rcrl", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 4705 { X86::RCR32m1, "rcrl", Convert__Mem5_0, { MCK_Mem }, 0}, 4706 { X86::RCR32rCL, "rcrl", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR32 }, 0}, 4707 { X86::RCR32mCL, "rcrl", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4708 { X86::RCR32ri, "rcrl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 4709 { X86::RCR32mi, "rcrl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4710 { X86::RCR64r1, "rcrq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 4711 { X86::RCR64m1, "rcrq", Convert__Mem5_0, { MCK_Mem }, 0}, 4712 { X86::RCR64rCL, "rcrq", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR64 }, 0}, 4713 { X86::RCR64mCL, "rcrq", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4714 { X86::RCR64ri, "rcrq", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR64 }, 0}, 4715 { X86::RCR64mi, "rcrq", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4716 { X86::RCR16r1, "rcrw", Convert__Reg1_0__Tie0, { MCK_GR16 }, 0}, 4717 { X86::RCR16m1, "rcrw", Convert__Mem5_0, { MCK_Mem }, 0}, 4718 { X86::RCR16rCL, "rcrw", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR16 }, 0}, 4719 { X86::RCR16mCL, "rcrw", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4720 { X86::RCR16ri, "rcrw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4721 { X86::RCR16mi, "rcrw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4722 { X86::RDFSBASE, "rdfsbasel", Convert__Reg1_0, { MCK_GR32 }, Feature_In64BitMode}, 4723 { X86::RDFSBASE64, "rdfsbaseq", Convert__Reg1_0, { MCK_GR64 }, Feature_In64BitMode}, 4724 { X86::RDGSBASE, "rdgsbasel", Convert__Reg1_0, { MCK_GR32 }, Feature_In64BitMode}, 4725 { X86::RDGSBASE64, "rdgsbaseq", Convert__Reg1_0, { MCK_GR64 }, Feature_In64BitMode}, 4726 { X86::RDMSR, "rdmsr", Convert, { }, 0}, 4727 { X86::RDPMC, "rdpmc", Convert, { }, 0}, 4728 { X86::RDRAND32r, "rdrandl", Convert__Reg1_0, { MCK_GR32 }, 0}, 4729 { X86::RDRAND64r, "rdrandq", Convert__Reg1_0, { MCK_GR64 }, 0}, 4730 { X86::RDRAND16r, "rdrandw", Convert__Reg1_0, { MCK_GR16 }, 0}, 4731 { X86::RDTSC, "rdtsc", Convert, { }, 0}, 4732 { X86::RDTSCP, "rdtscp", Convert, { }, 0}, 4733 { X86::REP_PREFIX, "rep", Convert, { }, 0}, 4734 { X86::REPNE_PREFIX, "repne", Convert, { }, 0}, 4735 { X86::RET, "ret", Convert, { }, 0}, 4736 { X86::RETI, "ret", Convert__Imm1_0, { MCK_Imm }, 0}, 4737 { X86::RETIW, "retw", Convert__Imm1_0, { MCK_Imm }, 0}, 4738 { X86::REX64_PREFIX, "rex64", Convert, { }, 0}, 4739 { X86::ROL8r1, "rolb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 4740 { X86::ROL8m1, "rolb", Convert__Mem5_0, { MCK_Mem }, 0}, 4741 { X86::ROL8rCL, "rolb", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR8 }, 0}, 4742 { X86::ROL8mCL, "rolb", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4743 { X86::ROL8ri, "rolb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 4744 { X86::ROL8mi, "rolb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4745 { X86::ROL32r1, "roll", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 4746 { X86::ROL32m1, "roll", Convert__Mem5_0, { MCK_Mem }, 0}, 4747 { X86::ROL32rCL, "roll", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR32 }, 0}, 4748 { X86::ROL32mCL, "roll", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4749 { X86::ROL32ri, "roll", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 4750 { X86::ROL32mi, "roll", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4751 { X86::ROL64r1, "rolq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 4752 { X86::ROL64m1, "rolq", Convert__Mem5_0, { MCK_Mem }, 0}, 4753 { X86::ROL64rCL, "rolq", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR64 }, 0}, 4754 { X86::ROL64mCL, "rolq", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4755 { X86::ROL64ri, "rolq", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR64 }, 0}, 4756 { X86::ROL64mi, "rolq", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4757 { X86::ROL16r1, "rolw", Convert__Reg1_0__Tie0, { MCK_GR16 }, 0}, 4758 { X86::ROL16m1, "rolw", Convert__Mem5_0, { MCK_Mem }, 0}, 4759 { X86::ROL16rCL, "rolw", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR16 }, 0}, 4760 { X86::ROL16mCL, "rolw", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4761 { X86::ROL16ri, "rolw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4762 { X86::ROL16mi, "rolw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4763 { X86::ROR8r1, "rorb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 4764 { X86::ROR8m1, "rorb", Convert__Mem5_0, { MCK_Mem }, 0}, 4765 { X86::ROR8rCL, "rorb", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR8 }, 0}, 4766 { X86::ROR8mCL, "rorb", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4767 { X86::ROR8ri, "rorb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 4768 { X86::ROR8mi, "rorb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4769 { X86::ROR32r1, "rorl", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 4770 { X86::ROR32m1, "rorl", Convert__Mem5_0, { MCK_Mem }, 0}, 4771 { X86::ROR32rCL, "rorl", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR32 }, 0}, 4772 { X86::ROR32mCL, "rorl", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4773 { X86::ROR32ri, "rorl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 4774 { X86::ROR32mi, "rorl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4775 { X86::ROR64r1, "rorq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 4776 { X86::ROR64m1, "rorq", Convert__Mem5_0, { MCK_Mem }, 0}, 4777 { X86::ROR64rCL, "rorq", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR64 }, 0}, 4778 { X86::ROR64mCL, "rorq", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4779 { X86::ROR64ri, "rorq", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR64 }, 0}, 4780 { X86::ROR64mi, "rorq", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4781 { X86::ROR16r1, "rorw", Convert__Reg1_0__Tie0, { MCK_GR16 }, 0}, 4782 { X86::ROR16m1, "rorw", Convert__Mem5_0, { MCK_Mem }, 0}, 4783 { X86::ROR16rCL, "rorw", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR16 }, 0}, 4784 { X86::ROR16mCL, "rorw", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4785 { X86::ROR16ri, "rorw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4786 { X86::ROR16mi, "rorw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4787 { X86::ROUNDPDr, "roundpd", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 4788 { X86::ROUNDPDm, "roundpd", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 4789 { X86::ROUNDPSr, "roundps", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 4790 { X86::ROUNDPSm, "roundps", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 4791 { X86::ROUNDSDr, "roundsd", Convert__Reg1_2__Tie0__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 4792 { X86::ROUNDSDm, "roundsd", Convert__Reg1_2__Tie0__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 4793 { X86::ROUNDSSr, "roundss", Convert__Reg1_2__Tie0__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 4794 { X86::ROUNDSSm, "roundss", Convert__Reg1_2__Tie0__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 4795 { X86::RSM, "rsm", Convert, { }, 0}, 4796 { X86::RSQRTPSr, "rsqrtps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4797 { X86::RSQRTPSm, "rsqrtps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4798 { X86::RSQRTSSr, "rsqrtss", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4799 { X86::RSQRTSSm, "rsqrtss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4800 { X86::SAHF, "sahf", Convert, { }, 0}, 4801 { X86::SAR8r1, "sarb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 4802 { X86::SAR8m1, "sarb", Convert__Mem5_0, { MCK_Mem }, 0}, 4803 { X86::SAR8rCL, "sarb", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR8 }, 0}, 4804 { X86::SAR8mCL, "sarb", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4805 { X86::SAR8ri, "sarb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 4806 { X86::SAR8mi, "sarb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4807 { X86::SAR32r1, "sarl", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 4808 { X86::SAR32m1, "sarl", Convert__Mem5_0, { MCK_Mem }, 0}, 4809 { X86::SAR32rCL, "sarl", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR32 }, 0}, 4810 { X86::SAR32mCL, "sarl", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4811 { X86::SAR32ri, "sarl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 4812 { X86::SAR32mi, "sarl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4813 { X86::SAR64r1, "sarq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 4814 { X86::SAR64m1, "sarq", Convert__Mem5_0, { MCK_Mem }, 0}, 4815 { X86::SAR64rCL, "sarq", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR64 }, 0}, 4816 { X86::SAR64mCL, "sarq", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4817 { X86::SAR64ri, "sarq", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR64 }, 0}, 4818 { X86::SAR64mi, "sarq", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4819 { X86::SAR16r1, "sarw", Convert__Reg1_0__Tie0, { MCK_GR16 }, 0}, 4820 { X86::SAR16m1, "sarw", Convert__Mem5_0, { MCK_Mem }, 0}, 4821 { X86::SAR16rCL, "sarw", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR16 }, 0}, 4822 { X86::SAR16mCL, "sarw", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4823 { X86::SAR16ri, "sarw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4824 { X86::SAR16mi, "sarw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4825 { X86::SBB8rr, "sbbb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 4826 { X86::SBB8mr, "sbbb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 4827 { X86::SBB8i8, "sbbb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 4828 { X86::SBB8ri, "sbbb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 4829 { X86::SBB8mi, "sbbb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4830 { X86::SBB8rm, "sbbb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 4831 { X86::SBB32rr, "sbbl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 4832 { X86::SBB32mr, "sbbl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 4833 { X86::SBB32ri8, "sbbl", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 4834 { X86::SBB32mi8, "sbbl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 4835 { X86::SBB32i32, "sbbl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 4836 { X86::SBB32ri, "sbbl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 4837 { X86::SBB32mi, "sbbl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4838 { X86::SBB32rm, "sbbl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 4839 { X86::SBB64rr, "sbbq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 4840 { X86::SBB64mr, "sbbq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 4841 { X86::SBB64ri8, "sbbq", Convert__Reg1_1__Tie0__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 4842 { X86::SBB64mi8, "sbbq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 4843 { X86::SBB64i32, "sbbq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_RAX }, 0}, 4844 { X86::SBB64ri32, "sbbq", Convert__Reg1_1__Tie0__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 4845 { X86::SBB64mi32, "sbbq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 4846 { X86::SBB64rm, "sbbq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 4847 { X86::SBB16rr, "sbbw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 4848 { X86::SBB16mr, "sbbw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 4849 { X86::SBB16ri8, "sbbw", Convert__Reg1_1__Tie0__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 4850 { X86::SBB16mi8, "sbbw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 4851 { X86::SBB16i16, "sbbw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 4852 { X86::SBB16ri, "sbbw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4853 { X86::SBB16mi, "sbbw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4854 { X86::SBB16rm, "sbbw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 4855 { X86::SCAS8, "scasb", Convert, { }, 0}, 4856 { X86::SCAS32, "scasl", Convert, { }, 0}, 4857 { X86::SCAS64, "scasq", Convert, { }, 0}, 4858 { X86::SCAS16, "scasw", Convert, { }, 0}, 4859 { X86::SETAr, "seta", Convert__Reg1_0, { MCK_GR8 }, 0}, 4860 { X86::SETAm, "seta", Convert__Mem5_0, { MCK_Mem }, 0}, 4861 { X86::SETAEr, "setae", Convert__Reg1_0, { MCK_GR8 }, 0}, 4862 { X86::SETAEm, "setae", Convert__Mem5_0, { MCK_Mem }, 0}, 4863 { X86::SETBr, "setb", Convert__Reg1_0, { MCK_GR8 }, 0}, 4864 { X86::SETBm, "setb", Convert__Mem5_0, { MCK_Mem }, 0}, 4865 { X86::SETBEr, "setbe", Convert__Reg1_0, { MCK_GR8 }, 0}, 4866 { X86::SETBEm, "setbe", Convert__Mem5_0, { MCK_Mem }, 0}, 4867 { X86::SETEr, "sete", Convert__Reg1_0, { MCK_GR8 }, 0}, 4868 { X86::SETEm, "sete", Convert__Mem5_0, { MCK_Mem }, 0}, 4869 { X86::SETGr, "setg", Convert__Reg1_0, { MCK_GR8 }, 0}, 4870 { X86::SETGm, "setg", Convert__Mem5_0, { MCK_Mem }, 0}, 4871 { X86::SETGEr, "setge", Convert__Reg1_0, { MCK_GR8 }, 0}, 4872 { X86::SETGEm, "setge", Convert__Mem5_0, { MCK_Mem }, 0}, 4873 { X86::SETLr, "setl", Convert__Reg1_0, { MCK_GR8 }, 0}, 4874 { X86::SETLm, "setl", Convert__Mem5_0, { MCK_Mem }, 0}, 4875 { X86::SETLEr, "setle", Convert__Reg1_0, { MCK_GR8 }, 0}, 4876 { X86::SETLEm, "setle", Convert__Mem5_0, { MCK_Mem }, 0}, 4877 { X86::SETNEr, "setne", Convert__Reg1_0, { MCK_GR8 }, 0}, 4878 { X86::SETNEm, "setne", Convert__Mem5_0, { MCK_Mem }, 0}, 4879 { X86::SETNOr, "setno", Convert__Reg1_0, { MCK_GR8 }, 0}, 4880 { X86::SETNOm, "setno", Convert__Mem5_0, { MCK_Mem }, 0}, 4881 { X86::SETNPr, "setnp", Convert__Reg1_0, { MCK_GR8 }, 0}, 4882 { X86::SETNPm, "setnp", Convert__Mem5_0, { MCK_Mem }, 0}, 4883 { X86::SETNSr, "setns", Convert__Reg1_0, { MCK_GR8 }, 0}, 4884 { X86::SETNSm, "setns", Convert__Mem5_0, { MCK_Mem }, 0}, 4885 { X86::SETOr, "seto", Convert__Reg1_0, { MCK_GR8 }, 0}, 4886 { X86::SETOm, "seto", Convert__Mem5_0, { MCK_Mem }, 0}, 4887 { X86::SETPr, "setp", Convert__Reg1_0, { MCK_GR8 }, 0}, 4888 { X86::SETPm, "setp", Convert__Mem5_0, { MCK_Mem }, 0}, 4889 { X86::SETSr, "sets", Convert__Reg1_0, { MCK_GR8 }, 0}, 4890 { X86::SETSm, "sets", Convert__Mem5_0, { MCK_Mem }, 0}, 4891 { X86::SFENCE, "sfence", Convert, { }, 0}, 4892 { X86::SGDTm, "sgdt", Convert__Mem5_0, { MCK_Mem }, 0}, 4893 { X86::SGDT16m, "sgdtw", Convert__Mem5_0, { MCK_Mem }, Feature_In32BitMode}, 4894 { X86::SHL8r1, "shlb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 4895 { X86::SHL8m1, "shlb", Convert__Mem5_0, { MCK_Mem }, 0}, 4896 { X86::SHL8rCL, "shlb", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR8 }, 0}, 4897 { X86::SHL8mCL, "shlb", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4898 { X86::SHL8ri, "shlb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 4899 { X86::SHL8mi, "shlb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4900 { X86::SHLD32rri8, "shldl", Convert__Reg1_0__Tie0__Reg1_1__imm1, { MCK_GR32, MCK_GR32 }, 0}, 4901 { X86::SHLD32mri8, "shldl", Convert__Mem5_0__Reg1_1__imm1, { MCK_Mem, MCK_GR32 }, 0}, 4902 { X86::SHLD32rrCL, "shldl", Convert__Reg1_2__Tie0__Reg1_1, { MCK_CL, MCK_GR32, MCK_GR32 }, 0}, 4903 { X86::SHLD32mrCL, "shldl", Convert__Mem5_2__Reg1_1, { MCK_CL, MCK_GR32, MCK_Mem }, 0}, 4904 { X86::SHLD32rri8, "shldl", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR32, MCK_GR32 }, 0}, 4905 { X86::SHLD32mri8, "shldl", Convert__Mem5_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR32, MCK_Mem }, 0}, 4906 { X86::SHLD64rri8, "shldq", Convert__Reg1_0__Tie0__Reg1_1__imm1, { MCK_GR64, MCK_GR64 }, 0}, 4907 { X86::SHLD64mri8, "shldq", Convert__Mem5_0__Reg1_1__imm1, { MCK_Mem, MCK_GR64 }, 0}, 4908 { X86::SHLD64rrCL, "shldq", Convert__Reg1_2__Tie0__Reg1_1, { MCK_CL, MCK_GR64, MCK_GR64 }, 0}, 4909 { X86::SHLD64mrCL, "shldq", Convert__Mem5_2__Reg1_1, { MCK_CL, MCK_GR64, MCK_Mem }, 0}, 4910 { X86::SHLD64rri8, "shldq", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR64, MCK_GR64 }, 0}, 4911 { X86::SHLD64mri8, "shldq", Convert__Mem5_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR64, MCK_Mem }, 0}, 4912 { X86::SHLD16rri8, "shldw", Convert__Reg1_0__Tie0__Reg1_1__imm1, { MCK_GR16, MCK_GR16 }, 0}, 4913 { X86::SHLD16mri8, "shldw", Convert__Mem5_0__Reg1_1__imm1, { MCK_Mem, MCK_GR16 }, 0}, 4914 { X86::SHLD16rrCL, "shldw", Convert__Reg1_2__Tie0__Reg1_1, { MCK_CL, MCK_GR16, MCK_GR16 }, 0}, 4915 { X86::SHLD16mrCL, "shldw", Convert__Mem5_2__Reg1_1, { MCK_CL, MCK_GR16, MCK_Mem }, 0}, 4916 { X86::SHLD16rri8, "shldw", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR16, MCK_GR16 }, 0}, 4917 { X86::SHLD16mri8, "shldw", Convert__Mem5_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR16, MCK_Mem }, 0}, 4918 { X86::SHL32r1, "shll", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 4919 { X86::SHL32m1, "shll", Convert__Mem5_0, { MCK_Mem }, 0}, 4920 { X86::SHL32rCL, "shll", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR32 }, 0}, 4921 { X86::SHL32mCL, "shll", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4922 { X86::SHL32ri, "shll", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 4923 { X86::SHL32mi, "shll", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4924 { X86::SHL64r1, "shlq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 4925 { X86::SHL64m1, "shlq", Convert__Mem5_0, { MCK_Mem }, 0}, 4926 { X86::SHL64rCL, "shlq", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR64 }, 0}, 4927 { X86::SHL64mCL, "shlq", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4928 { X86::SHL64ri, "shlq", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR64 }, 0}, 4929 { X86::SHL64mi, "shlq", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4930 { X86::SHL16r1, "shlw", Convert__Reg1_0__Tie0, { MCK_GR16 }, 0}, 4931 { X86::SHL16m1, "shlw", Convert__Mem5_0, { MCK_Mem }, 0}, 4932 { X86::SHL16rCL, "shlw", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR16 }, 0}, 4933 { X86::SHL16mCL, "shlw", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4934 { X86::SHL16ri, "shlw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4935 { X86::SHL16mi, "shlw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4936 { X86::SHR8r1, "shrb", Convert__Reg1_0__Tie0, { MCK_GR8 }, 0}, 4937 { X86::SHR8m1, "shrb", Convert__Mem5_0, { MCK_Mem }, 0}, 4938 { X86::SHR8rCL, "shrb", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR8 }, 0}, 4939 { X86::SHR8mCL, "shrb", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4940 { X86::SHR8ri, "shrb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 4941 { X86::SHR8mi, "shrb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4942 { X86::SHRD32rri8, "shrdl", Convert__Reg1_0__Tie0__Reg1_1__imm1, { MCK_GR32, MCK_GR32 }, 0}, 4943 { X86::SHRD32mri8, "shrdl", Convert__Mem5_0__Reg1_1__imm1, { MCK_Mem, MCK_GR32 }, 0}, 4944 { X86::SHRD32rrCL, "shrdl", Convert__Reg1_2__Tie0__Reg1_1, { MCK_CL, MCK_GR32, MCK_GR32 }, 0}, 4945 { X86::SHRD32mrCL, "shrdl", Convert__Mem5_2__Reg1_1, { MCK_CL, MCK_GR32, MCK_Mem }, 0}, 4946 { X86::SHRD32rri8, "shrdl", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR32, MCK_GR32 }, 0}, 4947 { X86::SHRD32mri8, "shrdl", Convert__Mem5_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR32, MCK_Mem }, 0}, 4948 { X86::SHRD64rri8, "shrdq", Convert__Reg1_0__Tie0__Reg1_1__imm1, { MCK_GR64, MCK_GR64 }, 0}, 4949 { X86::SHRD64mri8, "shrdq", Convert__Mem5_0__Reg1_1__imm1, { MCK_Mem, MCK_GR64 }, 0}, 4950 { X86::SHRD64rrCL, "shrdq", Convert__Reg1_2__Tie0__Reg1_1, { MCK_CL, MCK_GR64, MCK_GR64 }, 0}, 4951 { X86::SHRD64mrCL, "shrdq", Convert__Mem5_2__Reg1_1, { MCK_CL, MCK_GR64, MCK_Mem }, 0}, 4952 { X86::SHRD64rri8, "shrdq", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR64, MCK_GR64 }, 0}, 4953 { X86::SHRD64mri8, "shrdq", Convert__Mem5_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR64, MCK_Mem }, 0}, 4954 { X86::SHRD16rri8, "shrdw", Convert__Reg1_0__Tie0__Reg1_1__imm1, { MCK_GR16, MCK_GR16 }, 0}, 4955 { X86::SHRD16mri8, "shrdw", Convert__Mem5_0__Reg1_1__imm1, { MCK_Mem, MCK_GR16 }, 0}, 4956 { X86::SHRD16rrCL, "shrdw", Convert__Reg1_2__Tie0__Reg1_1, { MCK_CL, MCK_GR16, MCK_GR16 }, 0}, 4957 { X86::SHRD16mrCL, "shrdw", Convert__Mem5_2__Reg1_1, { MCK_CL, MCK_GR16, MCK_Mem }, 0}, 4958 { X86::SHRD16rri8, "shrdw", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR16, MCK_GR16 }, 0}, 4959 { X86::SHRD16mri8, "shrdw", Convert__Mem5_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR16, MCK_Mem }, 0}, 4960 { X86::SHR32r1, "shrl", Convert__Reg1_0__Tie0, { MCK_GR32 }, 0}, 4961 { X86::SHR32m1, "shrl", Convert__Mem5_0, { MCK_Mem }, 0}, 4962 { X86::SHR32rCL, "shrl", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR32 }, 0}, 4963 { X86::SHR32mCL, "shrl", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4964 { X86::SHR32ri, "shrl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 4965 { X86::SHR32mi, "shrl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4966 { X86::SHR64r1, "shrq", Convert__Reg1_0__Tie0, { MCK_GR64 }, 0}, 4967 { X86::SHR64m1, "shrq", Convert__Mem5_0, { MCK_Mem }, 0}, 4968 { X86::SHR64rCL, "shrq", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR64 }, 0}, 4969 { X86::SHR64mCL, "shrq", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4970 { X86::SHR64ri, "shrq", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR64 }, 0}, 4971 { X86::SHR64mi, "shrq", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4972 { X86::SHR16r1, "shrw", Convert__Reg1_0__Tie0, { MCK_GR16 }, 0}, 4973 { X86::SHR16m1, "shrw", Convert__Mem5_0, { MCK_Mem }, 0}, 4974 { X86::SHR16rCL, "shrw", Convert__Reg1_1__Tie0, { MCK_CL, MCK_GR16 }, 0}, 4975 { X86::SHR16mCL, "shrw", Convert__Mem5_1, { MCK_CL, MCK_Mem }, 0}, 4976 { X86::SHR16ri, "shrw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 4977 { X86::SHR16mi, "shrw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 4978 { X86::SHUFPDrri, "shufpd", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4979 { X86::SHUFPDrmi, "shufpd", Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4980 { X86::SHUFPSrri, "shufps", Convert__Reg1_2__Tie0__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 4981 { X86::SHUFPSrmi, "shufps", Convert__Reg1_2__Tie0__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 4982 { X86::SIDTm, "sidt", Convert__Mem5_0, { MCK_Mem }, 0}, 4983 { X86::SIDT16m, "sidtw", Convert__Mem5_0, { MCK_Mem }, Feature_In32BitMode}, 4984 { X86::SLDT16m, "sldt", Convert__Mem5_0, { MCK_Mem }, 0}, 4985 { X86::SLDT32r, "sldtl", Convert__Reg1_0, { MCK_GR32 }, 0}, 4986 { X86::SLDT64r, "sldtq", Convert__Reg1_0, { MCK_GR64 }, 0}, 4987 { X86::SLDT64m, "sldtq", Convert__Mem5_0, { MCK_Mem }, 0}, 4988 { X86::SLDT16r, "sldtw", Convert__Reg1_0, { MCK_GR16 }, 0}, 4989 { X86::SLDT16m, "sldtw", Convert__Mem5_0, { MCK_Mem }, 0}, 4990 { X86::SMSW32r, "smswl", Convert__Reg1_0, { MCK_GR32 }, 0}, 4991 { X86::SMSW64r, "smswq", Convert__Reg1_0, { MCK_GR64 }, 0}, 4992 { X86::SMSW16r, "smsww", Convert__Reg1_0, { MCK_GR16 }, 0}, 4993 { X86::SMSW16m, "smsww", Convert__Mem5_0, { MCK_Mem }, 0}, 4994 { X86::SQRTPDr, "sqrtpd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4995 { X86::SQRTPDm, "sqrtpd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4996 { X86::SQRTPSr, "sqrtps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4997 { X86::SQRTPSm, "sqrtps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 4998 { X86::SQRTSDr, "sqrtsd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 4999 { X86::SQRTSDm, "sqrtsd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5000 { X86::SQRTSSr, "sqrtss", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5001 { X86::SQRTSSm, "sqrtss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5002 { X86::SS_PREFIX, "ss", Convert, { }, 0}, 5003 { X86::STC, "stc", Convert, { }, 0}, 5004 { X86::STD, "std", Convert, { }, 0}, 5005 { X86::STI, "sti", Convert, { }, 0}, 5006 { X86::STMXCSR, "stmxcsr", Convert__Mem5_0, { MCK_Mem }, 0}, 5007 { X86::STOSB, "stosb", Convert, { }, 0}, 5008 { X86::STOSD, "stosl", Convert, { }, 0}, 5009 { X86::STOSQ, "stosq", Convert, { }, 0}, 5010 { X86::STOSW, "stosw", Convert, { }, 0}, 5011 { X86::STR32r, "strl", Convert__Reg1_0, { MCK_GR32 }, 0}, 5012 { X86::STR64r, "strq", Convert__Reg1_0, { MCK_GR64 }, 0}, 5013 { X86::STR16r, "strw", Convert__Reg1_0, { MCK_GR16 }, 0}, 5014 { X86::STRm, "strw", Convert__Mem5_0, { MCK_Mem }, 0}, 5015 { X86::SUB8rr, "subb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 5016 { X86::SUB8mr, "subb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 5017 { X86::SUB8i8, "subb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 5018 { X86::SUB8ri, "subb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 5019 { X86::SUB8mi, "subb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 5020 { X86::SUB8rm, "subb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 5021 { X86::SUB32rr, "subl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 5022 { X86::SUB32mr, "subl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 5023 { X86::SUB32ri8, "subl", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 5024 { X86::SUB32mi8, "subl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 5025 { X86::SUB32i32, "subl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 5026 { X86::SUB32ri, "subl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 5027 { X86::SUB32mi, "subl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 5028 { X86::SUB32rm, "subl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 5029 { X86::SUBPDrr, "subpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5030 { X86::SUBPDrm, "subpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5031 { X86::SUBPSrr, "subps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5032 { X86::SUBPSrm, "subps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5033 { X86::SUB64rr, "subq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 5034 { X86::SUB64mr, "subq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 5035 { X86::SUB64ri8, "subq", Convert__Reg1_1__Tie0__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 5036 { X86::SUB64mi8, "subq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 5037 { X86::SUB64i32, "subq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_RAX }, 0}, 5038 { X86::SUB64ri32, "subq", Convert__Reg1_1__Tie0__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 5039 { X86::SUB64mi32, "subq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 5040 { X86::SUB64rm, "subq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 5041 { X86::SUBSDrr, "subsd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5042 { X86::SUBSDrm, "subsd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5043 { X86::SUBSSrr, "subss", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5044 { X86::SUBSSrm, "subss", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5045 { X86::SUB16rr, "subw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 5046 { X86::SUB16mr, "subw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 5047 { X86::SUB16ri8, "subw", Convert__Reg1_1__Tie0__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 5048 { X86::SUB16mi8, "subw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 5049 { X86::SUB16i16, "subw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 5050 { X86::SUB16ri, "subw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 5051 { X86::SUB16mi, "subw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 5052 { X86::SUB16rm, "subw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 5053 { X86::SWAPGS, "swapgs", Convert, { }, 0}, 5054 { X86::SYSCALL, "syscall", Convert, { }, 0}, 5055 { X86::SYSENTER, "sysenter", Convert, { }, 0}, 5056 { X86::SYSEXIT, "sysexit", Convert, { }, Feature_In32BitMode}, 5057 { X86::SYSEXIT64, "sysexit", Convert, { }, Feature_In64BitMode}, 5058 { X86::SYSRETL, "sysretl", Convert, { }, 0}, 5059 { X86::SYSRETQ, "sysretq", Convert, { }, Feature_In64BitMode}, 5060 { X86::TEST8rr, "testb", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 5061 { X86::TEST8rm, "testb", Convert__Reg1_0__Mem5_1, { MCK_GR8, MCK_Mem }, 0}, 5062 { X86::TEST8i8, "testb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 5063 { X86::TEST8ri, "testb", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 5064 { X86::TEST8mi, "testb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 5065 { X86::TEST8rm, "testb", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 5066 { X86::TEST32rr, "testl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 5067 { X86::TEST32rm, "testl", Convert__Reg1_0__Mem5_1, { MCK_GR32, MCK_Mem }, 0}, 5068 { X86::TEST32i32, "testl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 5069 { X86::TEST32ri, "testl", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 5070 { X86::TEST32mi, "testl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 5071 { X86::TEST32rm, "testl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 5072 { X86::TEST64rr, "testq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 5073 { X86::TEST64rm, "testq", Convert__Reg1_0__Mem5_1, { MCK_GR64, MCK_Mem }, 0}, 5074 { X86::TEST64i32, "testq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_RAX }, 0}, 5075 { X86::TEST64ri32, "testq", Convert__Reg1_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 5076 { X86::TEST64mi32, "testq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 5077 { X86::TEST64rm, "testq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 5078 { X86::TEST16rr, "testw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 5079 { X86::TEST16rm, "testw", Convert__Reg1_0__Mem5_1, { MCK_GR16, MCK_Mem }, 0}, 5080 { X86::TEST16i16, "testw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 5081 { X86::TEST16ri, "testw", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 5082 { X86::TEST16mi, "testw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 5083 { X86::TEST16rm, "testw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 5084 { X86::TZCNT32rr, "tzcntl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 5085 { X86::TZCNT32rm, "tzcntl", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 5086 { X86::TZCNT64rr, "tzcntq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 5087 { X86::TZCNT64rm, "tzcntq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 5088 { X86::TZCNT16rr, "tzcntw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 5089 { X86::TZCNT16rm, "tzcntw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 5090 { X86::UCOMISDrr, "ucomisd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5091 { X86::UCOMISDrm, "ucomisd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5092 { X86::UCOMISSrr, "ucomiss", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5093 { X86::UCOMISSrm, "ucomiss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5094 { X86::TRAP, "ud2", Convert, { }, 0}, 5095 { X86::UD2B, "ud2b", Convert, { }, 0}, 5096 { X86::UNPCKHPDrr, "unpckhpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5097 { X86::UNPCKHPDrm, "unpckhpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5098 { X86::UNPCKHPSrr, "unpckhps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5099 { X86::UNPCKHPSrm, "unpckhps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5100 { X86::UNPCKLPDrr, "unpcklpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5101 { X86::UNPCKLPDrm, "unpcklpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5102 { X86::UNPCKLPSrr, "unpcklps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5103 { X86::UNPCKLPSrm, "unpcklps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5104 { X86::VADDPDrr, "vaddpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5105 { X86::VADDPDYrr, "vaddpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5106 { X86::VADDPDrm, "vaddpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5107 { X86::VADDPDYrm, "vaddpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5108 { X86::VADDPSrr, "vaddps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5109 { X86::VADDPSYrr, "vaddps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5110 { X86::VADDPSrm, "vaddps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5111 { X86::VADDPSYrm, "vaddps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5112 { X86::VADDSDrr, "vaddsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5113 { X86::VADDSDrm, "vaddsd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5114 { X86::VADDSSrr, "vaddss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5115 { X86::VADDSSrm, "vaddss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5116 { X86::VADDSUBPDrr, "vaddsubpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5117 { X86::VADDSUBPDYrr, "vaddsubpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5118 { X86::VADDSUBPDrm, "vaddsubpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5119 { X86::VADDSUBPDYrm, "vaddsubpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5120 { X86::VADDSUBPSrr, "vaddsubps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5121 { X86::VADDSUBPSYrr, "vaddsubps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5122 { X86::VADDSUBPSrm, "vaddsubps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5123 { X86::VADDSUBPSYrm, "vaddsubps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5124 { X86::VAESDECrr, "vaesdec", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5125 { X86::VAESDECrm, "vaesdec", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5126 { X86::VAESDECLASTrr, "vaesdeclast", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5127 { X86::VAESDECLASTrm, "vaesdeclast", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5128 { X86::VAESENCrr, "vaesenc", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5129 { X86::VAESENCrm, "vaesenc", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5130 { X86::VAESENCLASTrr, "vaesenclast", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5131 { X86::VAESENCLASTrm, "vaesenclast", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5132 { X86::VAESIMCrr, "vaesimc", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5133 { X86::VAESIMCrm, "vaesimc", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5134 { X86::VAESKEYGENASSIST128rr, "vaeskeygenassist", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5135 { X86::VAESKEYGENASSIST128rm, "vaeskeygenassist", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5136 { X86::VANDNPDrr, "vandnpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5137 { X86::VFsANDNPDrr, "vandnpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5138 { X86::VANDNPDYrr, "vandnpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5139 { X86::VANDNPDrm, "vandnpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5140 { X86::VFsANDNPDrm, "vandnpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5141 { X86::VANDNPDYrm, "vandnpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5142 { X86::VANDNPSrr, "vandnps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5143 { X86::VFsANDNPSrr, "vandnps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5144 { X86::VANDNPSYrr, "vandnps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5145 { X86::VANDNPSrm, "vandnps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5146 { X86::VFsANDNPSrm, "vandnps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5147 { X86::VANDNPSYrm, "vandnps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5148 { X86::VANDPDrr, "vandpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5149 { X86::VFsANDPDrr, "vandpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5150 { X86::VANDPDYrr, "vandpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5151 { X86::VANDPDrm, "vandpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5152 { X86::VFsANDPDrm, "vandpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5153 { X86::VANDPDYrm, "vandpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5154 { X86::VANDPSrr, "vandps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5155 { X86::VFsANDPSrr, "vandps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5156 { X86::VANDPSYrr, "vandps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5157 { X86::VANDPSrm, "vandps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5158 { X86::VFsANDPSrm, "vandps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5159 { X86::VANDPSYrm, "vandps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5160 { X86::VBLENDPDrri, "vblendpd", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5161 { X86::VBLENDPDYrri, "vblendpd", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5162 { X86::VBLENDPDrmi, "vblendpd", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5163 { X86::VBLENDPDYrmi, "vblendpd", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5164 { X86::VBLENDPSrri, "vblendps", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5165 { X86::VBLENDPSYrri, "vblendps", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5166 { X86::VBLENDPSrmi, "vblendps", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5167 { X86::VBLENDPSYrmi, "vblendps", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5168 { X86::VBLENDVPDrr, "vblendvpd", Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5169 { X86::VBLENDVPDrm, "vblendvpd", Convert__Reg1_3__Reg1_2__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5170 { X86::VBLENDVPDYrr, "vblendvpd", Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5171 { X86::VBLENDVPDYrm, "vblendvpd", Convert__Reg1_3__Reg1_2__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5172 { X86::VBLENDVPSrr, "vblendvps", Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5173 { X86::VBLENDVPSrm, "vblendvps", Convert__Reg1_3__Reg1_2__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5174 { X86::VBLENDVPSYrr, "vblendvps", Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5175 { X86::VBLENDVPSYrm, "vblendvps", Convert__Reg1_3__Reg1_2__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5176 { X86::VBROADCASTF128, "vbroadcastf128", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5177 { X86::VBROADCASTSD, "vbroadcastsd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5178 { X86::VBROADCASTSS, "vbroadcastss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5179 { X86::VBROADCASTSSY, "vbroadcastss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5180 { X86::VCMPPDrri, "vcmp", Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0, { MCK_Imm, MCK_pd, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5181 { X86::VCMPPDYrri, "vcmp", Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0, { MCK_Imm, MCK_pd, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5182 { X86::VCMPPDrmi, "vcmp", Convert__Reg1_4__Reg1_3__Mem5_2__Imm1_0, { MCK_Imm, MCK_pd, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5183 { X86::VCMPPDYrmi, "vcmp", Convert__Reg1_4__Reg1_3__Mem5_2__Imm1_0, { MCK_Imm, MCK_pd, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5184 { X86::VCMPPSrri, "vcmp", Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0, { MCK_Imm, MCK_ps, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5185 { X86::VCMPPSYrri, "vcmp", Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0, { MCK_Imm, MCK_ps, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5186 { X86::VCMPPSrmi, "vcmp", Convert__Reg1_4__Reg1_3__Mem5_2__Imm1_0, { MCK_Imm, MCK_ps, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5187 { X86::VCMPPSYrmi, "vcmp", Convert__Reg1_4__Reg1_3__Mem5_2__Imm1_0, { MCK_Imm, MCK_ps, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5188 { X86::VCMPSDrr, "vcmp", Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0, { MCK_Imm, MCK_sd, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5189 { X86::VCMPSDrm, "vcmp", Convert__Reg1_4__Reg1_3__Mem5_2__Imm1_0, { MCK_Imm, MCK_sd, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5190 { X86::VCMPSSrr, "vcmp", Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0, { MCK_Imm, MCK_ss, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5191 { X86::VCMPSSrm, "vcmp", Convert__Reg1_4__Reg1_3__Mem5_2__Imm1_0, { MCK_Imm, MCK_ss, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5192 { X86::VCMPPDrri_alt, "vcmppd", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5193 { X86::VCMPPDYrri_alt, "vcmppd", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5194 { X86::VCMPPDrmi_alt, "vcmppd", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5195 { X86::VCMPPDYrmi_alt, "vcmppd", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5196 { X86::VCMPPSrri_alt, "vcmpps", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5197 { X86::VCMPPSYrri_alt, "vcmpps", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5198 { X86::VCMPPSrmi_alt, "vcmpps", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5199 { X86::VCMPPSYrmi_alt, "vcmpps", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5200 { X86::VCMPSDrr_alt, "vcmpsd", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5201 { X86::VCMPSDrm_alt, "vcmpsd", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5202 { X86::VCMPSSrr_alt, "vcmpss", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5203 { X86::VCMPSSrm_alt, "vcmpss", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5204 { X86::VCOMISDrr, "vcomisd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5205 { X86::VCOMISDrm, "vcomisd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5206 { X86::VCOMISSrr, "vcomiss", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5207 { X86::VCOMISSrm, "vcomiss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5208 { X86::VCVTDQ2PDrr, "vcvtdq2pd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5209 { X86::VCVTDQ2PDYrr, "vcvtdq2pd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_VR256 }, 0}, 5210 { X86::VCVTDQ2PDrm, "vcvtdq2pd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5211 { X86::VCVTDQ2PDYrm, "vcvtdq2pd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5212 { X86::VCVTDQ2PSrr, "vcvtdq2ps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5213 { X86::VCVTDQ2PSYrr, "vcvtdq2ps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5214 { X86::VCVTDQ2PSrm, "vcvtdq2ps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5215 { X86::VCVTDQ2PSYrm, "vcvtdq2ps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5216 { X86::VCVTPD2DQrr, "vcvtpd2dq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5217 { X86::VCVTPD2DQXrYr, "vcvtpd2dq", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_FR32 }, 0}, 5218 { X86::VCVTPD2DQXrr, "vcvtpd2dqx", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5219 { X86::VCVTPD2DQXrm, "vcvtpd2dqx", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5220 { X86::VCVTPD2DQYrr, "vcvtpd2dqy", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_FR32 }, 0}, 5221 { X86::VCVTPD2DQYrm, "vcvtpd2dqy", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5222 { X86::VCVTPD2PSrr, "vcvtpd2ps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5223 { X86::VCVTPD2PSXrYr, "vcvtpd2ps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_FR32 }, 0}, 5224 { X86::VCVTPD2PSXrr, "vcvtpd2psx", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5225 { X86::VCVTPD2PSXrm, "vcvtpd2psx", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5226 { X86::VCVTPD2PSYrr, "vcvtpd2psy", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_FR32 }, 0}, 5227 { X86::VCVTPD2PSYrm, "vcvtpd2psy", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5228 { X86::VCVTPH2PSrr, "vcvtph2ps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5229 { X86::VCVTPH2PSYrr, "vcvtph2ps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_VR256 }, 0}, 5230 { X86::VCVTPH2PSrm, "vcvtph2ps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5231 { X86::VCVTPH2PSYrm, "vcvtph2ps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5232 { X86::VCVTPS2DQrr, "vcvtps2dq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5233 { X86::VCVTPS2DQYrr, "vcvtps2dq", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5234 { X86::VCVTPS2DQrm, "vcvtps2dq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5235 { X86::VCVTPS2DQYrm, "vcvtps2dq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5236 { X86::VCVTPS2PDrr, "vcvtps2pd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5237 { X86::VCVTPS2PDYrr, "vcvtps2pd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_VR256 }, 0}, 5238 { X86::VCVTPS2PDrm, "vcvtps2pd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5239 { X86::VCVTPS2PDYrm, "vcvtps2pd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5240 { X86::VCVTPS2PHrr, "vcvtps2ph", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5241 { X86::VCVTPS2PHmr, "vcvtps2ph", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 5242 { X86::VCVTPS2PHYrr, "vcvtps2ph", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR256, MCK_FR32 }, 0}, 5243 { X86::VCVTPS2PHYmr, "vcvtps2ph", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR256, MCK_Mem }, 0}, 5244 { X86::VCVTSD2SIrr, "vcvtsd2si", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 5245 { X86::VCVTSD2SI64rr, "vcvtsd2si", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5246 { X86::VCVTSD2SIrm, "vcvtsd2si", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 5247 { X86::VCVTSD2SI64rm, "vcvtsd2si", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 5248 { X86::VCVTSD2SSrr, "vcvtsd2ss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5249 { X86::VCVTSD2SSrm, "vcvtsd2ss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5250 { X86::VCVTSI2SDrr, "vcvtsi2sd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32, MCK_FR32 }, 0}, 5251 { X86::VCVTSI2SDrm, "vcvtsi2sd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5252 { X86::VCVTSI2SDLrr, "vcvtsi2sdl", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32, MCK_FR32 }, 0}, 5253 { X86::VCVTSI2SDLrm, "vcvtsi2sdl", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5254 { X86::VCVTSI2SD64rr, "vcvtsi2sdq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32, MCK_FR32 }, 0}, 5255 { X86::VCVTSI2SD64rm, "vcvtsi2sdq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5256 { X86::VCVTSI2SSrr, "vcvtsi2ss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32, MCK_FR32 }, 0}, 5257 { X86::VCVTSI2SSrm, "vcvtsi2ss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5258 { X86::VCVTSI2SS64rr, "vcvtsi2ssq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32, MCK_FR32 }, 0}, 5259 { X86::VCVTSI2SS64rm, "vcvtsi2ssq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5260 { X86::VCVTSS2SDrr, "vcvtss2sd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5261 { X86::VCVTSS2SDrm, "vcvtss2sd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5262 { X86::VCVTSS2SI64rr, "vcvtss2si", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5263 { X86::VCVTSS2SI64rm, "vcvtss2si", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 5264 { X86::VCVTSS2SIrr, "vcvtss2sil", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 5265 { X86::VCVTSS2SIrm, "vcvtss2sil", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 5266 { X86::VCVTTPD2DQrr, "vcvttpd2dq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5267 { X86::VCVTTPD2DQXrYr, "vcvttpd2dq", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_FR32 }, 0}, 5268 { X86::VCVTTPD2DQXrr, "vcvttpd2dqx", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5269 { X86::VCVTTPD2DQXrm, "vcvttpd2dqx", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5270 { X86::VCVTTPD2DQYrr, "vcvttpd2dqy", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_FR32 }, 0}, 5271 { X86::VCVTTPD2DQYrm, "vcvttpd2dqy", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5272 { X86::VCVTTPS2DQrr, "vcvttps2dq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5273 { X86::VCVTTPS2DQYrr, "vcvttps2dq", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5274 { X86::VCVTTPS2DQrm, "vcvttps2dq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5275 { X86::VCVTTPS2DQYrm, "vcvttps2dq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5276 { X86::VCVTTSD2SIrr, "vcvttsd2si", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 5277 { X86::VCVTTSD2SI64rr, "vcvttsd2si", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5278 { X86::VCVTTSD2SIrm, "vcvttsd2si", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 5279 { X86::VCVTTSD2SI64rm, "vcvttsd2si", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 5280 { X86::VCVTTSS2SIrr, "vcvttss2si", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 5281 { X86::VCVTTSS2SI64rr, "vcvttss2si", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5282 { X86::VCVTTSS2SIrm, "vcvttss2si", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 5283 { X86::VCVTTSS2SI64rm, "vcvttss2si", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 5284 { X86::VDIVPDrr, "vdivpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5285 { X86::VDIVPDYrr, "vdivpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5286 { X86::VDIVPDrm, "vdivpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5287 { X86::VDIVPDYrm, "vdivpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5288 { X86::VDIVPSrr, "vdivps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5289 { X86::VDIVPSYrr, "vdivps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5290 { X86::VDIVPSrm, "vdivps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5291 { X86::VDIVPSYrm, "vdivps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5292 { X86::VDIVSDrr, "vdivsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5293 { X86::VDIVSDrm, "vdivsd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5294 { X86::VDIVSSrr, "vdivss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5295 { X86::VDIVSSrm, "vdivss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5296 { X86::VDPPDrri, "vdppd", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5297 { X86::VDPPDrmi, "vdppd", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5298 { X86::VDPPSrri, "vdpps", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5299 { X86::VDPPSYrri, "vdpps", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5300 { X86::VDPPSrmi, "vdpps", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5301 { X86::VDPPSYrmi, "vdpps", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5302 { X86::VERRr, "verr", Convert__Reg1_0, { MCK_GR16 }, 0}, 5303 { X86::VERRm, "verr", Convert__Mem5_0, { MCK_Mem }, 0}, 5304 { X86::VERWr, "verw", Convert__Reg1_0, { MCK_GR16 }, 0}, 5305 { X86::VERWm, "verw", Convert__Mem5_0, { MCK_Mem }, 0}, 5306 { X86::VEXTRACTF128rr, "vextractf128", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR256, MCK_FR32 }, 0}, 5307 { X86::VEXTRACTF128mr, "vextractf128", Convert__Mem5_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR256, MCK_Mem }, 0}, 5308 { X86::VEXTRACTPSrr, "vextractps", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR32 }, 0}, 5309 { X86::VEXTRACTPSrr64, "vextractps", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR64 }, 0}, 5310 { X86::VEXTRACTPSmr, "vextractps", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 5311 { X86::VFMADDPDr132r, "vfmadd132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5312 { X86::VFMADDPDr132rY, "vfmadd132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5313 { X86::VFMADDPDr132m, "vfmadd132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5314 { X86::VFMADDPDr132mY, "vfmadd132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5315 { X86::VFMADDPSr132r, "vfmadd132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5316 { X86::VFMADDPSr132rY, "vfmadd132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5317 { X86::VFMADDPSr132m, "vfmadd132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5318 { X86::VFMADDPSr132mY, "vfmadd132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5319 { X86::VFMADDPDr213r, "vfmadd213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5320 { X86::VFMADDPDr213rY, "vfmadd213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5321 { X86::VFMADDPDr213m, "vfmadd213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5322 { X86::VFMADDPDr213mY, "vfmadd213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5323 { X86::VFMADDPSr213r, "vfmadd213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5324 { X86::VFMADDPSr213rY, "vfmadd213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5325 { X86::VFMADDPSr213m, "vfmadd213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5326 { X86::VFMADDPSr213mY, "vfmadd213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5327 { X86::VFMADDPDr231r, "vfmadd231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5328 { X86::VFMADDPDr231rY, "vfmadd231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5329 { X86::VFMADDPDr231m, "vfmadd231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5330 { X86::VFMADDPDr231mY, "vfmadd231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5331 { X86::VFMADDPSr231r, "vfmadd231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5332 { X86::VFMADDPSr231rY, "vfmadd231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5333 { X86::VFMADDPSr231m, "vfmadd231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5334 { X86::VFMADDPSr231mY, "vfmadd231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5335 { X86::VFMADDSUBPDr132r, "vfmaddsub132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5336 { X86::VFMADDSUBPDr132rY, "vfmaddsub132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5337 { X86::VFMADDSUBPDr132m, "vfmaddsub132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5338 { X86::VFMADDSUBPDr132mY, "vfmaddsub132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5339 { X86::VFMADDSUBPSr132r, "vfmaddsub132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5340 { X86::VFMADDSUBPSr132rY, "vfmaddsub132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5341 { X86::VFMADDSUBPSr132m, "vfmaddsub132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5342 { X86::VFMADDSUBPSr132mY, "vfmaddsub132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5343 { X86::VFMADDSUBPDr213r, "vfmaddsub213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5344 { X86::VFMADDSUBPDr213rY, "vfmaddsub213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5345 { X86::VFMADDSUBPDr213m, "vfmaddsub213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5346 { X86::VFMADDSUBPDr213mY, "vfmaddsub213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5347 { X86::VFMADDSUBPSr213r, "vfmaddsub213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5348 { X86::VFMADDSUBPSr213rY, "vfmaddsub213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5349 { X86::VFMADDSUBPSr213m, "vfmaddsub213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5350 { X86::VFMADDSUBPSr213mY, "vfmaddsub213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5351 { X86::VFMADDSUBPDr231r, "vfmaddsub231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5352 { X86::VFMADDSUBPDr231rY, "vfmaddsub231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5353 { X86::VFMADDSUBPDr231m, "vfmaddsub231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5354 { X86::VFMADDSUBPDr231mY, "vfmaddsub231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5355 { X86::VFMADDSUBPSr231r, "vfmaddsub231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5356 { X86::VFMADDSUBPSr231rY, "vfmaddsub231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5357 { X86::VFMADDSUBPSr231m, "vfmaddsub231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5358 { X86::VFMADDSUBPSr231mY, "vfmaddsub231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5359 { X86::VFMSUBPDr132r, "vfmsub132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5360 { X86::VFMSUBPDr132rY, "vfmsub132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5361 { X86::VFMSUBPDr132m, "vfmsub132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5362 { X86::VFMSUBPDr132mY, "vfmsub132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5363 { X86::VFMSUBPSr132r, "vfmsub132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5364 { X86::VFMSUBPSr132rY, "vfmsub132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5365 { X86::VFMSUBPSr132m, "vfmsub132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5366 { X86::VFMSUBPSr132mY, "vfmsub132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5367 { X86::VFMSUBPDr213r, "vfmsub213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5368 { X86::VFMSUBPDr213rY, "vfmsub213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5369 { X86::VFMSUBPDr213m, "vfmsub213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5370 { X86::VFMSUBPDr213mY, "vfmsub213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5371 { X86::VFMSUBPSr213r, "vfmsub213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5372 { X86::VFMSUBPSr213rY, "vfmsub213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5373 { X86::VFMSUBPSr213m, "vfmsub213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5374 { X86::VFMSUBPSr213mY, "vfmsub213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5375 { X86::VFMSUBPDr231r, "vfmsub231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5376 { X86::VFMSUBPDr231rY, "vfmsub231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5377 { X86::VFMSUBPDr231m, "vfmsub231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5378 { X86::VFMSUBPDr231mY, "vfmsub231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5379 { X86::VFMSUBPSr231r, "vfmsub231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5380 { X86::VFMSUBPSr231rY, "vfmsub231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5381 { X86::VFMSUBPSr231m, "vfmsub231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5382 { X86::VFMSUBPSr231mY, "vfmsub231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5383 { X86::VFMSUBADDPDr132r, "vfmsubadd132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5384 { X86::VFMSUBADDPDr132rY, "vfmsubadd132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5385 { X86::VFMSUBADDPDr132m, "vfmsubadd132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5386 { X86::VFMSUBADDPDr132mY, "vfmsubadd132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5387 { X86::VFMSUBADDPSr132r, "vfmsubadd132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5388 { X86::VFMSUBADDPSr132rY, "vfmsubadd132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5389 { X86::VFMSUBADDPSr132m, "vfmsubadd132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5390 { X86::VFMSUBADDPSr132mY, "vfmsubadd132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5391 { X86::VFMSUBADDPDr213r, "vfmsubadd213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5392 { X86::VFMSUBADDPDr213rY, "vfmsubadd213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5393 { X86::VFMSUBADDPDr213m, "vfmsubadd213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5394 { X86::VFMSUBADDPDr213mY, "vfmsubadd213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5395 { X86::VFMSUBADDPSr213r, "vfmsubadd213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5396 { X86::VFMSUBADDPSr213rY, "vfmsubadd213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5397 { X86::VFMSUBADDPSr213m, "vfmsubadd213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5398 { X86::VFMSUBADDPSr213mY, "vfmsubadd213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5399 { X86::VFMSUBADDPDr231r, "vfmsubadd231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5400 { X86::VFMSUBADDPDr231rY, "vfmsubadd231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5401 { X86::VFMSUBADDPDr231m, "vfmsubadd231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5402 { X86::VFMSUBADDPDr231mY, "vfmsubadd231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5403 { X86::VFMSUBADDPSr231r, "vfmsubadd231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5404 { X86::VFMSUBADDPSr231rY, "vfmsubadd231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5405 { X86::VFMSUBADDPSr231m, "vfmsubadd231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5406 { X86::VFMSUBADDPSr231mY, "vfmsubadd231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5407 { X86::VFNMADDPDr132r, "vfnmadd132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5408 { X86::VFNMADDPDr132rY, "vfnmadd132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5409 { X86::VFNMADDPDr132m, "vfnmadd132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5410 { X86::VFNMADDPDr132mY, "vfnmadd132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5411 { X86::VFNMADDPSr132r, "vfnmadd132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5412 { X86::VFNMADDPSr132rY, "vfnmadd132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5413 { X86::VFNMADDPSr132m, "vfnmadd132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5414 { X86::VFNMADDPSr132mY, "vfnmadd132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5415 { X86::VFNMADDPDr213r, "vfnmadd213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5416 { X86::VFNMADDPDr213rY, "vfnmadd213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5417 { X86::VFNMADDPDr213m, "vfnmadd213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5418 { X86::VFNMADDPDr213mY, "vfnmadd213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5419 { X86::VFNMADDPSr213r, "vfnmadd213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5420 { X86::VFNMADDPSr213rY, "vfnmadd213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5421 { X86::VFNMADDPSr213m, "vfnmadd213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5422 { X86::VFNMADDPSr213mY, "vfnmadd213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5423 { X86::VFNMADDPDr231r, "vfnmadd231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5424 { X86::VFNMADDPDr231rY, "vfnmadd231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5425 { X86::VFNMADDPDr231m, "vfnmadd231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5426 { X86::VFNMADDPDr231mY, "vfnmadd231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5427 { X86::VFNMADDPSr231r, "vfnmadd231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5428 { X86::VFNMADDPSr231rY, "vfnmadd231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5429 { X86::VFNMADDPSr231m, "vfnmadd231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5430 { X86::VFNMADDPSr231mY, "vfnmadd231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5431 { X86::VFNMSUBPDr132r, "vfnmsub132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5432 { X86::VFNMSUBPDr132rY, "vfnmsub132pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5433 { X86::VFNMSUBPDr132m, "vfnmsub132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5434 { X86::VFNMSUBPDr132mY, "vfnmsub132pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5435 { X86::VFNMSUBPSr132r, "vfnmsub132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5436 { X86::VFNMSUBPSr132rY, "vfnmsub132ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5437 { X86::VFNMSUBPSr132m, "vfnmsub132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5438 { X86::VFNMSUBPSr132mY, "vfnmsub132ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5439 { X86::VFNMSUBPDr213r, "vfnmsub213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5440 { X86::VFNMSUBPDr213rY, "vfnmsub213pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5441 { X86::VFNMSUBPDr213m, "vfnmsub213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5442 { X86::VFNMSUBPDr213mY, "vfnmsub213pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5443 { X86::VFNMSUBPSr213r, "vfnmsub213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5444 { X86::VFNMSUBPSr213rY, "vfnmsub213ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5445 { X86::VFNMSUBPSr213m, "vfnmsub213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5446 { X86::VFNMSUBPSr213mY, "vfnmsub213ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5447 { X86::VFNMSUBPDr231r, "vfnmsub231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5448 { X86::VFNMSUBPDr231rY, "vfnmsub231pd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5449 { X86::VFNMSUBPDr231m, "vfnmsub231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5450 { X86::VFNMSUBPDr231mY, "vfnmsub231pd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5451 { X86::VFNMSUBPSr231r, "vfnmsub231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5452 { X86::VFNMSUBPSr231rY, "vfnmsub231ps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5453 { X86::VFNMSUBPSr231m, "vfnmsub231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5454 { X86::VFNMSUBPSr231mY, "vfnmsub231ps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5455 { X86::VHADDPDrr, "vhaddpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5456 { X86::VHADDPDYrr, "vhaddpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5457 { X86::VHADDPDrm, "vhaddpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5458 { X86::VHADDPDYrm, "vhaddpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5459 { X86::VHADDPSrr, "vhaddps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5460 { X86::VHADDPSYrr, "vhaddps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5461 { X86::VHADDPSrm, "vhaddps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5462 { X86::VHADDPSYrm, "vhaddps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5463 { X86::VHSUBPDrr, "vhsubpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5464 { X86::VHSUBPDYrr, "vhsubpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5465 { X86::VHSUBPDrm, "vhsubpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5466 { X86::VHSUBPDYrm, "vhsubpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5467 { X86::VHSUBPSrr, "vhsubps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5468 { X86::VHSUBPSYrr, "vhsubps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5469 { X86::VHSUBPSrm, "vhsubps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5470 { X86::VHSUBPSYrm, "vhsubps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5471 { X86::VINSERTF128rr, "vinsertf128", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_VR256, MCK_VR256 }, 0}, 5472 { X86::VINSERTF128rm, "vinsertf128", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5473 { X86::VINSERTPSrr, "vinsertps", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5474 { X86::VINSERTPSrm, "vinsertps", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5475 { X86::VLDDQUrm, "vlddqu", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5476 { X86::VLDDQUYrm, "vlddqu", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5477 { X86::VLDMXCSR, "vldmxcsr", Convert__Mem5_0, { MCK_Mem }, 0}, 5478 { X86::VMASKMOVDQU, "vmaskmovdqu", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5479 { X86::VMASKMOVDQU64, "vmaskmovdqu", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5480 { X86::VMASKMOVPDmr, "vmaskmovpd", Convert__Mem5_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_Mem }, 0}, 5481 { X86::VMASKMOVPDYmr, "vmaskmovpd", Convert__Mem5_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_Mem }, 0}, 5482 { X86::VMASKMOVPDrm, "vmaskmovpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5483 { X86::VMASKMOVPDYrm, "vmaskmovpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5484 { X86::VMASKMOVPSmr, "vmaskmovps", Convert__Mem5_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_Mem }, 0}, 5485 { X86::VMASKMOVPSYmr, "vmaskmovps", Convert__Mem5_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_Mem }, 0}, 5486 { X86::VMASKMOVPSrm, "vmaskmovps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5487 { X86::VMASKMOVPSYrm, "vmaskmovps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5488 { X86::VMAXPDrr, "vmaxpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5489 { X86::VMAXPDYrr, "vmaxpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5490 { X86::VMAXPDrm, "vmaxpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5491 { X86::VMAXPDYrm, "vmaxpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5492 { X86::VMAXPSrr, "vmaxps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5493 { X86::VMAXPSYrr, "vmaxps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5494 { X86::VMAXPSrm, "vmaxps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5495 { X86::VMAXPSYrm, "vmaxps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5496 { X86::VMAXSDrr, "vmaxsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5497 { X86::VMAXSDrm, "vmaxsd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5498 { X86::VMAXSSrr, "vmaxss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5499 { X86::VMAXSSrm, "vmaxss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5500 { X86::VMCALL, "vmcall", Convert, { }, 0}, 5501 { X86::VMCLEARm, "vmclear", Convert__Mem5_0, { MCK_Mem }, 0}, 5502 { X86::VMINPDrr, "vminpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5503 { X86::VMINPDYrr, "vminpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5504 { X86::VMINPDrm, "vminpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5505 { X86::VMINPDYrm, "vminpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5506 { X86::VMINPSrr, "vminps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5507 { X86::VMINPSYrr, "vminps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5508 { X86::VMINPSrm, "vminps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5509 { X86::VMINPSYrm, "vminps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5510 { X86::VMINSDrr, "vminsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5511 { X86::VMINSDrm, "vminsd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5512 { X86::VMINSSrr, "vminss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5513 { X86::VMINSSrm, "vminss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5514 { X86::VMLAUNCH, "vmlaunch", Convert, { }, 0}, 5515 { X86::FsVMOVAPDrr, "vmovapd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5516 { X86::VMOVAPDrr, "vmovapd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5517 { X86::VMOVAPDmr, "vmovapd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5518 { X86::VMOVAPDYrr, "vmovapd", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5519 { X86::VMOVAPDYmr, "vmovapd", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5520 { X86::VMOVAPDrm, "vmovapd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5521 { X86::VMOVAPDYrm, "vmovapd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5522 { X86::FsVMOVAPSrr, "vmovaps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5523 { X86::VMOVAPSrr, "vmovaps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5524 { X86::VMOVAPSmr, "vmovaps", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5525 { X86::VMOVAPSYrr, "vmovaps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5526 { X86::VMOVAPSYmr, "vmovaps", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5527 { X86::VMOVAPSrm, "vmovaps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5528 { X86::VMOVAPSYrm, "vmovaps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5529 { X86::VMOVDI2PDIrr, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32 }, 0}, 5530 { X86::VMOVDI2SSrr, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32 }, 0}, 5531 { X86::VMOVZDI2PDIrr, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_FR32 }, 0}, 5532 { X86::VMOV64toPQIrr, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 5533 { X86::VMOV64toSDrr, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 5534 { X86::VMOVZQI2PQIrr, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 5535 { X86::VMOVPDI2DIrr, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 5536 { X86::VMOVSS2DIrr, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 5537 { X86::VMOVQd64rr_alt, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5538 { X86::VMOVSDto64rr, "vmovd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5539 { X86::VMOVPDI2DImr, "vmovd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5540 { X86::VMOVSS2DImr, "vmovd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5541 { X86::VMOVDI2PDIrm, "vmovd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5542 { X86::VMOVDI2SSrm, "vmovd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5543 { X86::VMOVZDI2PDIrm, "vmovd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5544 { X86::VMOVDDUPrr, "vmovddup", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5545 { X86::VMOVDDUPYrr, "vmovddup", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5546 { X86::VMOVDDUPrm, "vmovddup", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5547 { X86::VMOVDDUPYrm, "vmovddup", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5548 { X86::VMOVDQArr, "vmovdqa", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5549 { X86::VMOVDQAmr, "vmovdqa", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5550 { X86::VMOVDQAYrr, "vmovdqa", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5551 { X86::VMOVDQAYmr, "vmovdqa", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5552 { X86::VMOVDQArm, "vmovdqa", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5553 { X86::VMOVDQAYrm, "vmovdqa", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5554 { X86::VMOVDQUrr, "vmovdqu", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5555 { X86::VMOVDQUmr, "vmovdqu", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5556 { X86::VMOVDQUYrr, "vmovdqu", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5557 { X86::VMOVDQUYmr, "vmovdqu", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5558 { X86::VMOVDQUrm, "vmovdqu", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5559 { X86::VMOVDQUYrm, "vmovdqu", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5560 { X86::VMOVHLPSrr, "vmovhlps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5561 { X86::VMOVHPDmr, "vmovhpd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5562 { X86::VMOVHPDrm, "vmovhpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5563 { X86::VMOVHPSmr, "vmovhps", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5564 { X86::VMOVHPSrm, "vmovhps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5565 { X86::VMOVLHPSrr, "vmovlhps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5566 { X86::VMOVLPDmr, "vmovlpd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5567 { X86::VMOVLPDrm, "vmovlpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5568 { X86::VMOVLPSmr, "vmovlps", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5569 { X86::VMOVLPSrm, "vmovlps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5570 { X86::VMOVMSKPDrr32, "vmovmskpd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 5571 { X86::VMOVMSKPDr64r, "vmovmskpd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5572 { X86::VMOVMSKPDrr64, "vmovmskpd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5573 { X86::VMOVMSKPDYrr32, "vmovmskpd", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_GR32 }, 0}, 5574 { X86::VMOVMSKPDYr64r, "vmovmskpd", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_GR64 }, 0}, 5575 { X86::VMOVMSKPDYrr64, "vmovmskpd", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_GR64 }, 0}, 5576 { X86::VMOVMSKPSrr32, "vmovmskps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 5577 { X86::VMOVMSKPSr64r, "vmovmskps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5578 { X86::VMOVMSKPSrr64, "vmovmskps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5579 { X86::VMOVMSKPSYrr32, "vmovmskps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_GR32 }, 0}, 5580 { X86::VMOVMSKPSYr64r, "vmovmskps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_GR64 }, 0}, 5581 { X86::VMOVMSKPSYrr64, "vmovmskps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_GR64 }, 0}, 5582 { X86::VMOVNTDQ_64mr, "vmovntdq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5583 { X86::VMOVNTDQmr, "vmovntdq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5584 { X86::VMOVNTDQY_64mr, "vmovntdq", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5585 { X86::VMOVNTDQYmr, "vmovntdq", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5586 { X86::VMOVNTDQArm, "vmovntdqa", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5587 { X86::VMOVNTPDmr, "vmovntpd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5588 { X86::VMOVNTPDYmr, "vmovntpd", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5589 { X86::VMOVNTPSmr, "vmovntps", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5590 { X86::VMOVNTPSYmr, "vmovntps", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5591 { X86::VMOVQs64rr, "vmovq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_FR32 }, 0}, 5592 { X86::VMOVQd64rr, "vmovq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5593 { X86::VMOVQxrxr, "vmovq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5594 { X86::VMOVZPQILo2PQIrr, "vmovq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5595 { X86::VMOVLQ128mr, "vmovq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5596 { X86::VMOVPQI2QImr, "vmovq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5597 { X86::VMOVSDto64mr, "vmovq", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5598 { X86::VMOV64toSDrm, "vmovq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5599 { X86::VMOVQI2PQIrm, "vmovq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5600 { X86::VMOVZPQILo2PQIrm, "vmovq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5601 { X86::VMOVZQI2PQIrm, "vmovq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5602 { X86::VMOVSDmr, "vmovsd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5603 { X86::VMOVSDrm, "vmovsd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5604 { X86::VMOVSDrr, "vmovsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5605 { X86::VMOVSHDUPrr, "vmovshdup", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5606 { X86::VMOVSHDUPYrr, "vmovshdup", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5607 { X86::VMOVSHDUPrm, "vmovshdup", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5608 { X86::VMOVSHDUPYrm, "vmovshdup", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5609 { X86::VMOVSLDUPrr, "vmovsldup", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5610 { X86::VMOVSLDUPYrr, "vmovsldup", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5611 { X86::VMOVSLDUPrm, "vmovsldup", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5612 { X86::VMOVSLDUPYrm, "vmovsldup", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5613 { X86::VMOVSSmr, "vmovss", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5614 { X86::VMOVSSrm, "vmovss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5615 { X86::VMOVSSrr, "vmovss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5616 { X86::VMOVUPDrr, "vmovupd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5617 { X86::VMOVUPDmr, "vmovupd", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5618 { X86::VMOVUPDYrr, "vmovupd", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5619 { X86::VMOVUPDYmr, "vmovupd", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5620 { X86::VMOVUPDrm, "vmovupd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5621 { X86::VMOVUPDYrm, "vmovupd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5622 { X86::VMOVUPSrr, "vmovups", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5623 { X86::VMOVUPSmr, "vmovups", Convert__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem }, 0}, 5624 { X86::VMOVUPSYrr, "vmovups", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5625 { X86::VMOVUPSYmr, "vmovups", Convert__Mem5_1__Reg1_0, { MCK_VR256, MCK_Mem }, 0}, 5626 { X86::VMOVUPSrm, "vmovups", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5627 { X86::VMOVUPSYrm, "vmovups", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5628 { X86::VMPSADBWrri, "vmpsadbw", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5629 { X86::VMPSADBWrmi, "vmpsadbw", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5630 { X86::VMPTRLDm, "vmptrld", Convert__Mem5_0, { MCK_Mem }, 0}, 5631 { X86::VMPTRSTm, "vmptrst", Convert__Mem5_0, { MCK_Mem }, 0}, 5632 { X86::VMREAD32rr, "vmreadl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 5633 { X86::VMREAD32rm, "vmreadl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 5634 { X86::VMREAD64rr, "vmreadq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 5635 { X86::VMREAD64rm, "vmreadq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 5636 { X86::VMRESUME, "vmresume", Convert, { }, 0}, 5637 { X86::VMULPDrr, "vmulpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5638 { X86::VMULPDYrr, "vmulpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5639 { X86::VMULPDrm, "vmulpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5640 { X86::VMULPDYrm, "vmulpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5641 { X86::VMULPSrr, "vmulps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5642 { X86::VMULPSYrr, "vmulps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5643 { X86::VMULPSrm, "vmulps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5644 { X86::VMULPSYrm, "vmulps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5645 { X86::VMULSDrr, "vmulsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5646 { X86::VMULSDrm, "vmulsd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5647 { X86::VMULSSrr, "vmulss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5648 { X86::VMULSSrm, "vmulss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5649 { X86::VMWRITE32rr, "vmwritel", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 5650 { X86::VMWRITE32rm, "vmwritel", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 5651 { X86::VMWRITE64rr, "vmwriteq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 5652 { X86::VMWRITE64rm, "vmwriteq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 5653 { X86::VMXOFF, "vmxoff", Convert, { }, 0}, 5654 { X86::VMXON, "vmxon", Convert__Mem5_0, { MCK_Mem }, 0}, 5655 { X86::VFsORPDrr, "vorpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5656 { X86::VORPDrr, "vorpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5657 { X86::VORPDYrr, "vorpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5658 { X86::VFsORPDrm, "vorpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5659 { X86::VORPDrm, "vorpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5660 { X86::VORPDYrm, "vorpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5661 { X86::VFsORPSrr, "vorps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5662 { X86::VORPSrr, "vorps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5663 { X86::VORPSYrr, "vorps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5664 { X86::VFsORPSrm, "vorps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5665 { X86::VORPSrm, "vorps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5666 { X86::VORPSYrm, "vorps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5667 { X86::VPABSBrr128, "vpabsb", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5668 { X86::VPABSBrm128, "vpabsb", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5669 { X86::VPABSDrr128, "vpabsd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5670 { X86::VPABSDrm128, "vpabsd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5671 { X86::VPABSWrr128, "vpabsw", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5672 { X86::VPABSWrm128, "vpabsw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5673 { X86::VPACKSSDWrr, "vpackssdw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5674 { X86::VPACKSSDWrm, "vpackssdw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5675 { X86::VPACKSSWBrr, "vpacksswb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5676 { X86::VPACKSSWBrm, "vpacksswb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5677 { X86::VPACKUSDWrr, "vpackusdw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5678 { X86::VPACKUSDWrm, "vpackusdw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5679 { X86::VPACKUSWBrr, "vpackuswb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5680 { X86::VPACKUSWBrm, "vpackuswb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5681 { X86::VPADDBrr, "vpaddb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5682 { X86::VPADDBrm, "vpaddb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5683 { X86::VPADDDrr, "vpaddd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5684 { X86::VPADDDrm, "vpaddd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5685 { X86::VPADDQrr, "vpaddq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5686 { X86::VPADDQrm, "vpaddq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5687 { X86::VPADDSBrr, "vpaddsb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5688 { X86::VPADDSBrm, "vpaddsb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5689 { X86::VPADDSWrr, "vpaddsw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5690 { X86::VPADDSWrm, "vpaddsw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5691 { X86::VPADDUSBrr, "vpaddusb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5692 { X86::VPADDUSBrm, "vpaddusb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5693 { X86::VPADDUSWrr, "vpaddusw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5694 { X86::VPADDUSWrm, "vpaddusw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5695 { X86::VPADDWrr, "vpaddw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5696 { X86::VPADDWrm, "vpaddw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5697 { X86::VPALIGNR128rr, "vpalignr", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5698 { X86::VPALIGNR128rm, "vpalignr", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5699 { X86::VPANDrr, "vpand", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5700 { X86::VPANDrm, "vpand", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5701 { X86::VPANDNrr, "vpandn", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5702 { X86::VPANDNrm, "vpandn", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5703 { X86::VPAVGBrr, "vpavgb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5704 { X86::VPAVGBrm, "vpavgb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5705 { X86::VPAVGWrr, "vpavgw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5706 { X86::VPAVGWrm, "vpavgw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5707 { X86::VPBLENDVBrr, "vpblendvb", Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5708 { X86::VPBLENDVBrm, "vpblendvb", Convert__Reg1_3__Reg1_2__Mem5_1__Reg1_0, { MCK_FR32, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5709 { X86::VPBLENDWrri, "vpblendw", Convert__Reg1_3__Reg1_2__Reg1_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5710 { X86::VPBLENDWrmi, "vpblendw", Convert__Reg1_3__Reg1_2__Mem5_1__ImmZExtu32u81_0, { MCK_ImmZExtu32u8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5711 { X86::VPCLMULQDQrr, "vpclmulhqhqdq", Convert__Reg1_2__Reg1_1__Reg1_0__imm17, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5712 { X86::VPCLMULQDQrm, "vpclmulhqhqdq", Convert__Reg1_2__Reg1_1__Mem5_0__imm17, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5713 { X86::VPCLMULQDQrr, "vpclmulhqlqdq", Convert__Reg1_2__Reg1_1__Reg1_0__imm1, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5714 { X86::VPCLMULQDQrm, "vpclmulhqlqdq", Convert__Reg1_2__Reg1_1__Mem5_0__imm1, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5715 { X86::VPCLMULQDQrr, "vpclmullqhqdq", Convert__Reg1_2__Reg1_1__Reg1_0__imm16, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5716 { X86::VPCLMULQDQrm, "vpclmullqhqdq", Convert__Reg1_2__Reg1_1__Mem5_0__imm16, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5717 { X86::VPCLMULQDQrr, "vpclmullqlqdq", Convert__Reg1_2__Reg1_1__Reg1_0__imm0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5718 { X86::VPCLMULQDQrm, "vpclmullqlqdq", Convert__Reg1_2__Reg1_1__Mem5_0__imm0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5719 { X86::VPCLMULQDQrr, "vpclmulqdq", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5720 { X86::VPCLMULQDQrm, "vpclmulqdq", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5721 { X86::VPCMPEQBrr, "vpcmpeqb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5722 { X86::VPCMPEQBrm, "vpcmpeqb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5723 { X86::VPCMPEQDrr, "vpcmpeqd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5724 { X86::VPCMPEQDrm, "vpcmpeqd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5725 { X86::VPCMPEQQrr, "vpcmpeqq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5726 { X86::VPCMPEQQrm, "vpcmpeqq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5727 { X86::VPCMPEQWrr, "vpcmpeqw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5728 { X86::VPCMPEQWrm, "vpcmpeqw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5729 { X86::VPCMPESTRIArr, "vpcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5730 { X86::VPCMPESTRICrr, "vpcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5731 { X86::VPCMPESTRIOrr, "vpcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5732 { X86::VPCMPESTRISrr, "vpcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5733 { X86::VPCMPESTRIZrr, "vpcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5734 { X86::VPCMPESTRIrr, "vpcmpestri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5735 { X86::VPCMPESTRIArm, "vpcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5736 { X86::VPCMPESTRICrm, "vpcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5737 { X86::VPCMPESTRIOrm, "vpcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5738 { X86::VPCMPESTRISrm, "vpcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5739 { X86::VPCMPESTRIZrm, "vpcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5740 { X86::VPCMPESTRIrm, "vpcmpestri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5741 { X86::VPCMPESTRM128rr, "vpcmpestrm", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5742 { X86::VPCMPESTRM128rm, "vpcmpestrm", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5743 { X86::VPCMPGTBrr, "vpcmpgtb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5744 { X86::VPCMPGTBrm, "vpcmpgtb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5745 { X86::VPCMPGTDrr, "vpcmpgtd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5746 { X86::VPCMPGTDrm, "vpcmpgtd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5747 { X86::VPCMPGTQrr, "vpcmpgtq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5748 { X86::VPCMPGTQrm, "vpcmpgtq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5749 { X86::VPCMPGTWrr, "vpcmpgtw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5750 { X86::VPCMPGTWrm, "vpcmpgtw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5751 { X86::VPCMPISTRIArr, "vpcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5752 { X86::VPCMPISTRICrr, "vpcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5753 { X86::VPCMPISTRIOrr, "vpcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5754 { X86::VPCMPISTRISrr, "vpcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5755 { X86::VPCMPISTRIZrr, "vpcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5756 { X86::VPCMPISTRIrr, "vpcmpistri", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5757 { X86::VPCMPISTRIArm, "vpcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5758 { X86::VPCMPISTRICrm, "vpcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5759 { X86::VPCMPISTRIOrm, "vpcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5760 { X86::VPCMPISTRISrm, "vpcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5761 { X86::VPCMPISTRIZrm, "vpcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5762 { X86::VPCMPISTRIrm, "vpcmpistri", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5763 { X86::VPCMPISTRM128rr, "vpcmpistrm", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5764 { X86::VPCMPISTRM128rm, "vpcmpistrm", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5765 { X86::VPERM2F128rr, "vperm2f128", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5766 { X86::VPERM2F128rm, "vperm2f128", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5767 { X86::VPERMILPDrr, "vpermilpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5768 { X86::VPERMILPDYrr, "vpermilpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5769 { X86::VPERMILPDri, "vpermilpd", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5770 { X86::VPERMILPDYri, "vpermilpd", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR256, MCK_VR256 }, 0}, 5771 { X86::VPERMILPDmi, "vpermilpd", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5772 { X86::VPERMILPDYmi, "vpermilpd", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR256 }, 0}, 5773 { X86::VPERMILPDrm, "vpermilpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5774 { X86::VPERMILPDYrm, "vpermilpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5775 { X86::VPERMILPSrr, "vpermilps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5776 { X86::VPERMILPSYrr, "vpermilps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 5777 { X86::VPERMILPSri, "vpermilps", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5778 { X86::VPERMILPSYri, "vpermilps", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR256, MCK_VR256 }, 0}, 5779 { X86::VPERMILPSmi, "vpermilps", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5780 { X86::VPERMILPSYmi, "vpermilps", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR256 }, 0}, 5781 { X86::VPERMILPSrm, "vpermilps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5782 { X86::VPERMILPSYrm, "vpermilps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 5783 { X86::VPEXTRBrr, "vpextrb", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR32 }, 0}, 5784 { X86::VPEXTRBrr64, "vpextrb", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR64 }, 0}, 5785 { X86::VPEXTRBmr, "vpextrb", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 5786 { X86::VPEXTRDrr, "vpextrd", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR32 }, 0}, 5787 { X86::VPEXTRDmr, "vpextrd", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 5788 { X86::VPEXTRQrr, "vpextrq", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR64 }, 0}, 5789 { X86::VPEXTRQmr, "vpextrq", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 5790 { X86::VPEXTRWri, "vpextrw", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_GR32 }, 0}, 5791 { X86::VPEXTRWmr, "vpextrw", Convert__Mem5_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_Mem }, 0}, 5792 { X86::VPHADDDrr128, "vphaddd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5793 { X86::VPHADDDrm128, "vphaddd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5794 { X86::VPHADDSWrr128, "vphaddsw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5795 { X86::VPHADDSWrm128, "vphaddsw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5796 { X86::VPHADDWrr128, "vphaddw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5797 { X86::VPHADDWrm128, "vphaddw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5798 { X86::VPHMINPOSUWrr128, "vphminposuw", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5799 { X86::VPHMINPOSUWrm128, "vphminposuw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5800 { X86::VPHSUBDrr128, "vphsubd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5801 { X86::VPHSUBDrm128, "vphsubd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5802 { X86::VPHSUBSWrr128, "vphsubsw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5803 { X86::VPHSUBSWrm128, "vphsubsw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5804 { X86::VPHSUBWrr128, "vphsubw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5805 { X86::VPHSUBWrm128, "vphsubw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5806 { X86::VPINSRBrr, "vpinsrb", Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32, MCK_FR32, MCK_FR32 }, 0}, 5807 { X86::VPINSRBrm, "vpinsrb", Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5808 { X86::VPINSRDrr, "vpinsrd", Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32, MCK_FR32, MCK_FR32 }, 0}, 5809 { X86::VPINSRDrm, "vpinsrd", Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5810 { X86::VPINSRQrr, "vpinsrq", Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR64, MCK_FR32, MCK_FR32 }, 0}, 5811 { X86::VPINSRQrm, "vpinsrq", Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5812 { X86::VPINSRWrri, "vpinsrw", Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32, MCK_FR32, MCK_FR32 }, 0}, 5813 { X86::VPINSRWrr64i, "vpinsrw", Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR64, MCK_FR32, MCK_FR32 }, 0}, 5814 { X86::VPINSRWrmi, "vpinsrw", Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5815 { X86::VPMADDUBSWrr128, "vpmaddubsw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5816 { X86::VPMADDUBSWrm128, "vpmaddubsw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5817 { X86::VPMADDWDrr, "vpmaddwd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5818 { X86::VPMADDWDrm, "vpmaddwd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5819 { X86::VPMAXSBrr, "vpmaxsb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5820 { X86::VPMAXSBrm, "vpmaxsb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5821 { X86::VPMAXSDrr, "vpmaxsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5822 { X86::VPMAXSDrm, "vpmaxsd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5823 { X86::VPMAXSWrr, "vpmaxsw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5824 { X86::VPMAXSWrm, "vpmaxsw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5825 { X86::VPMAXUBrr, "vpmaxub", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5826 { X86::VPMAXUBrm, "vpmaxub", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5827 { X86::VPMAXUDrr, "vpmaxud", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5828 { X86::VPMAXUDrm, "vpmaxud", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5829 { X86::VPMAXUWrr, "vpmaxuw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5830 { X86::VPMAXUWrm, "vpmaxuw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5831 { X86::VPMINSBrr, "vpminsb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5832 { X86::VPMINSBrm, "vpminsb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5833 { X86::VPMINSDrr, "vpminsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5834 { X86::VPMINSDrm, "vpminsd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5835 { X86::VPMINSWrr, "vpminsw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5836 { X86::VPMINSWrm, "vpminsw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5837 { X86::VPMINUBrr, "vpminub", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5838 { X86::VPMINUBrm, "vpminub", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5839 { X86::VPMINUDrr, "vpminud", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5840 { X86::VPMINUDrm, "vpminud", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5841 { X86::VPMINUWrr, "vpminuw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5842 { X86::VPMINUWrm, "vpminuw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5843 { X86::VPMOVMSKBrr, "vpmovmskb", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR32 }, 0}, 5844 { X86::VPMOVMSKBr64r, "vpmovmskb", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_GR64 }, 0}, 5845 { X86::VPMOVSXBDrr, "vpmovsxbd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5846 { X86::VPMOVSXBDrm, "vpmovsxbd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5847 { X86::VPMOVSXBQrr, "vpmovsxbq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5848 { X86::VPMOVSXBQrm, "vpmovsxbq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5849 { X86::VPMOVSXBWrr, "vpmovsxbw", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5850 { X86::VPMOVSXBWrm, "vpmovsxbw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5851 { X86::VPMOVSXDQrr, "vpmovsxdq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5852 { X86::VPMOVSXDQrm, "vpmovsxdq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5853 { X86::VPMOVSXWDrr, "vpmovsxwd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5854 { X86::VPMOVSXWDrm, "vpmovsxwd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5855 { X86::VPMOVSXWQrr, "vpmovsxwq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5856 { X86::VPMOVSXWQrm, "vpmovsxwq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5857 { X86::VPMOVZXBDrr, "vpmovzxbd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5858 { X86::VPMOVZXBDrm, "vpmovzxbd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5859 { X86::VPMOVZXBQrr, "vpmovzxbq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5860 { X86::VPMOVZXBQrm, "vpmovzxbq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5861 { X86::VPMOVZXBWrr, "vpmovzxbw", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5862 { X86::VPMOVZXBWrm, "vpmovzxbw", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5863 { X86::VPMOVZXDQrr, "vpmovzxdq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5864 { X86::VPMOVZXDQrm, "vpmovzxdq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5865 { X86::VPMOVZXWDrr, "vpmovzxwd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5866 { X86::VPMOVZXWDrm, "vpmovzxwd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5867 { X86::VPMOVZXWQrr, "vpmovzxwq", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5868 { X86::VPMOVZXWQrm, "vpmovzxwq", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5869 { X86::VPMULDQrr, "vpmuldq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5870 { X86::VPMULDQrm, "vpmuldq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5871 { X86::VPMULHRSWrr128, "vpmulhrsw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5872 { X86::VPMULHRSWrm128, "vpmulhrsw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5873 { X86::VPMULHUWrr, "vpmulhuw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5874 { X86::VPMULHUWrm, "vpmulhuw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5875 { X86::VPMULHWrr, "vpmulhw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5876 { X86::VPMULHWrm, "vpmulhw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5877 { X86::VPMULLDrr, "vpmulld", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5878 { X86::VPMULLDrm, "vpmulld", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5879 { X86::VPMULLWrr, "vpmullw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5880 { X86::VPMULLWrm, "vpmullw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5881 { X86::VPMULUDQrr, "vpmuludq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5882 { X86::VPMULUDQrm, "vpmuludq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5883 { X86::VPORrr, "vpor", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5884 { X86::VPORrm, "vpor", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5885 { X86::VPSADBWrr, "vpsadbw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5886 { X86::VPSADBWrm, "vpsadbw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5887 { X86::VPSHUFBrr128, "vpshufb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5888 { X86::VPSHUFBrm128, "vpshufb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5889 { X86::VPSHUFDri, "vpshufd", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5890 { X86::VPSHUFDmi, "vpshufd", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5891 { X86::VPSHUFHWri, "vpshufhw", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5892 { X86::VPSHUFHWmi, "vpshufhw", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5893 { X86::VPSHUFLWri, "vpshuflw", Convert__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32 }, 0}, 5894 { X86::VPSHUFLWmi, "vpshuflw", Convert__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32 }, 0}, 5895 { X86::VPSIGNBrr128, "vpsignb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5896 { X86::VPSIGNBrm128, "vpsignb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5897 { X86::VPSIGNDrr128, "vpsignd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5898 { X86::VPSIGNDrm128, "vpsignd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5899 { X86::VPSIGNWrr128, "vpsignw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5900 { X86::VPSIGNWrm128, "vpsignw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5901 { X86::VPSLLDrr, "vpslld", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5902 { X86::VPSLLDri, "vpslld", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5903 { X86::VPSLLDrm, "vpslld", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5904 { X86::VPSLLDQri, "vpslldq", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5905 { X86::VPSLLQrr, "vpsllq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5906 { X86::VPSLLQri, "vpsllq", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5907 { X86::VPSLLQrm, "vpsllq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5908 { X86::VPSLLWrr, "vpsllw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5909 { X86::VPSLLWri, "vpsllw", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5910 { X86::VPSLLWrm, "vpsllw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5911 { X86::VPSRADrr, "vpsrad", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5912 { X86::VPSRADri, "vpsrad", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5913 { X86::VPSRADrm, "vpsrad", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5914 { X86::VPSRAWrr, "vpsraw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5915 { X86::VPSRAWri, "vpsraw", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5916 { X86::VPSRAWrm, "vpsraw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5917 { X86::VPSRLDrr, "vpsrld", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5918 { X86::VPSRLDri, "vpsrld", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5919 { X86::VPSRLDrm, "vpsrld", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5920 { X86::VPSRLDQri, "vpsrldq", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5921 { X86::VPSRLQrr, "vpsrlq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5922 { X86::VPSRLQri, "vpsrlq", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5923 { X86::VPSRLQrm, "vpsrlq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5924 { X86::VPSRLWrr, "vpsrlw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5925 { X86::VPSRLWri, "vpsrlw", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5926 { X86::VPSRLWrm, "vpsrlw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5927 { X86::VPSUBBrr, "vpsubb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5928 { X86::VPSUBBrm, "vpsubb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5929 { X86::VPSUBDrr, "vpsubd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5930 { X86::VPSUBDrm, "vpsubd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5931 { X86::VPSUBQrr, "vpsubq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5932 { X86::VPSUBQrm, "vpsubq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5933 { X86::VPSUBSBrr, "vpsubsb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5934 { X86::VPSUBSBrm, "vpsubsb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5935 { X86::VPSUBSWrr, "vpsubsw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5936 { X86::VPSUBSWrm, "vpsubsw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5937 { X86::VPSUBUSBrr, "vpsubusb", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5938 { X86::VPSUBUSBrm, "vpsubusb", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5939 { X86::VPSUBUSWrr, "vpsubusw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5940 { X86::VPSUBUSWrm, "vpsubusw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5941 { X86::VPSUBWrr, "vpsubw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5942 { X86::VPSUBWrm, "vpsubw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5943 { X86::VPTESTrr, "vptest", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5944 { X86::VPTESTYrr, "vptest", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5945 { X86::VPTESTrm, "vptest", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5946 { X86::VPTESTYrm, "vptest", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5947 { X86::VPUNPCKHBWrr, "vpunpckhbw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5948 { X86::VPUNPCKHBWrm, "vpunpckhbw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5949 { X86::VPUNPCKHDQrr, "vpunpckhdq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5950 { X86::VPUNPCKHDQrm, "vpunpckhdq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5951 { X86::VPUNPCKHQDQrr, "vpunpckhqdq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5952 { X86::VPUNPCKHQDQrm, "vpunpckhqdq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5953 { X86::VPUNPCKHWDrr, "vpunpckhwd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5954 { X86::VPUNPCKHWDrm, "vpunpckhwd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5955 { X86::VPUNPCKLBWrr, "vpunpcklbw", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5956 { X86::VPUNPCKLBWrm, "vpunpcklbw", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5957 { X86::VPUNPCKLDQrr, "vpunpckldq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5958 { X86::VPUNPCKLDQrm, "vpunpckldq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5959 { X86::VPUNPCKLQDQrr, "vpunpcklqdq", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5960 { X86::VPUNPCKLQDQrm, "vpunpcklqdq", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5961 { X86::VPUNPCKLWDrr, "vpunpcklwd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5962 { X86::VPUNPCKLWDrm, "vpunpcklwd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5963 { X86::VPXORrr, "vpxor", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5964 { X86::VPXORrm, "vpxor", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5965 { X86::VRCPPSr, "vrcpps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5966 { X86::VRCPPSYr, "vrcpps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5967 { X86::VRCPPSm, "vrcpps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5968 { X86::VRCPPSYm, "vrcpps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5969 { X86::VRCPSSr, "vrcpss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5970 { X86::VRCPSSm, "vrcpss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5971 { X86::VROUNDPDr, "vroundpd", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5972 { X86::VROUNDPDr_AVX, "vroundpd", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5973 { X86::VROUNDYPDr, "vroundpd", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR256, MCK_VR256 }, 0}, 5974 { X86::VROUNDYPDr_AVX, "vroundpd", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR256, MCK_VR256 }, 0}, 5975 { X86::VROUNDPDm, "vroundpd", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 5976 { X86::VROUNDPDm_AVX, "vroundpd", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 5977 { X86::VROUNDYPDm, "vroundpd", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_VR256 }, 0}, 5978 { X86::VROUNDYPDm_AVX, "vroundpd", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_VR256 }, 0}, 5979 { X86::VROUNDPSr, "vroundps", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5980 { X86::VROUNDPSr_AVX, "vroundps", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32 }, 0}, 5981 { X86::VROUNDYPSr, "vroundps", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR256, MCK_VR256 }, 0}, 5982 { X86::VROUNDYPSr_AVX, "vroundps", Convert__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_VR256, MCK_VR256 }, 0}, 5983 { X86::VROUNDPSm, "vroundps", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 5984 { X86::VROUNDPSm_AVX, "vroundps", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32 }, 0}, 5985 { X86::VROUNDYPSm, "vroundps", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_VR256 }, 0}, 5986 { X86::VROUNDYPSm_AVX, "vroundps", Convert__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_VR256 }, 0}, 5987 { X86::VROUNDSDr, "vroundsd", Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5988 { X86::VROUNDSDr_AVX, "vroundsd", Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5989 { X86::VROUNDSDm, "vroundsd", Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5990 { X86::VROUNDSDm_AVX, "vroundsd", Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5991 { X86::VROUNDSSr, "vroundss", Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5992 { X86::VROUNDSSr_AVX, "vroundss", Convert__Reg1_3__Reg1_2__Reg1_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 5993 { X86::VROUNDSSm, "vroundss", Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5994 { X86::VROUNDSSm_AVX, "vroundss", Convert__Reg1_3__Reg1_2__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 5995 { X86::VRSQRTPSr, "vrsqrtps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 5996 { X86::VRSQRTPSYr, "vrsqrtps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 5997 { X86::VRSQRTPSm, "vrsqrtps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 5998 { X86::VRSQRTPSYm, "vrsqrtps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 5999 { X86::VRSQRTSSr, "vrsqrtss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6000 { X86::VRSQRTSSm, "vrsqrtss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6001 { X86::VSHUFPDrri, "vshufpd", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6002 { X86::VSHUFPDYrri, "vshufpd", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6003 { X86::VSHUFPDrmi, "vshufpd", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6004 { X86::VSHUFPDYrmi, "vshufpd", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6005 { X86::VSHUFPSrri, "vshufps", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6006 { X86::VSHUFPSYrri, "vshufps", Convert__Reg1_3__Reg1_2__Reg1_1__Imm1_0, { MCK_Imm, MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6007 { X86::VSHUFPSrmi, "vshufps", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6008 { X86::VSHUFPSYrmi, "vshufps", Convert__Reg1_3__Reg1_2__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6009 { X86::VSQRTPDr, "vsqrtpd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6010 { X86::VSQRTPDYr, "vsqrtpd", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 6011 { X86::VSQRTPDm, "vsqrtpd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6012 { X86::VSQRTPDYm, "vsqrtpd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 6013 { X86::VSQRTPSr, "vsqrtps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6014 { X86::VSQRTPSYr, "vsqrtps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 6015 { X86::VSQRTPSm, "vsqrtps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6016 { X86::VSQRTPSYm, "vsqrtps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 6017 { X86::VSQRTSDr, "vsqrtsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6018 { X86::VSQRTSDm, "vsqrtsd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6019 { X86::VSQRTSSr, "vsqrtss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6020 { X86::VSQRTSSm, "vsqrtss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6021 { X86::VSTMXCSR, "vstmxcsr", Convert__Mem5_0, { MCK_Mem }, 0}, 6022 { X86::VSUBPDrr, "vsubpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6023 { X86::VSUBPDYrr, "vsubpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6024 { X86::VSUBPDrm, "vsubpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6025 { X86::VSUBPDYrm, "vsubpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6026 { X86::VSUBPSrr, "vsubps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6027 { X86::VSUBPSYrr, "vsubps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6028 { X86::VSUBPSrm, "vsubps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6029 { X86::VSUBPSYrm, "vsubps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6030 { X86::VSUBSDrr, "vsubsd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6031 { X86::VSUBSDrm, "vsubsd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6032 { X86::VSUBSSrr, "vsubss", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6033 { X86::VSUBSSrm, "vsubss", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6034 { X86::VTESTPDrr, "vtestpd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6035 { X86::VTESTPDYrr, "vtestpd", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 6036 { X86::VTESTPDrm, "vtestpd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6037 { X86::VTESTPDYrm, "vtestpd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 6038 { X86::VTESTPSrr, "vtestps", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6039 { X86::VTESTPSYrr, "vtestps", Convert__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256 }, 0}, 6040 { X86::VTESTPSrm, "vtestps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6041 { X86::VTESTPSYrm, "vtestps", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256 }, 0}, 6042 { X86::VUCOMISDrr, "vucomisd", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6043 { X86::VUCOMISDrm, "vucomisd", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6044 { X86::VUCOMISSrr, "vucomiss", Convert__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6045 { X86::VUCOMISSrm, "vucomiss", Convert__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6046 { X86::VUNPCKHPDrr, "vunpckhpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6047 { X86::VUNPCKHPDYrr, "vunpckhpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6048 { X86::VUNPCKHPDrm, "vunpckhpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6049 { X86::VUNPCKHPDYrm, "vunpckhpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6050 { X86::VUNPCKHPSrr, "vunpckhps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6051 { X86::VUNPCKHPSYrr, "vunpckhps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6052 { X86::VUNPCKHPSrm, "vunpckhps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6053 { X86::VUNPCKHPSYrm, "vunpckhps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6054 { X86::VUNPCKLPDrr, "vunpcklpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6055 { X86::VUNPCKLPDYrr, "vunpcklpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6056 { X86::VUNPCKLPDrm, "vunpcklpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6057 { X86::VUNPCKLPDYrm, "vunpcklpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6058 { X86::VUNPCKLPSrr, "vunpcklps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6059 { X86::VUNPCKLPSYrr, "vunpcklps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6060 { X86::VUNPCKLPSrm, "vunpcklps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6061 { X86::VUNPCKLPSYrm, "vunpcklps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6062 { X86::VFsXORPDrr, "vxorpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6063 { X86::VXORPDrr, "vxorpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6064 { X86::VXORPDYrr, "vxorpd", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6065 { X86::VFsXORPDrm, "vxorpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6066 { X86::VXORPDrm, "vxorpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6067 { X86::VXORPDYrm, "vxorpd", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6068 { X86::VFsXORPSrr, "vxorps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6069 { X86::VXORPSrr, "vxorps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_FR32, MCK_FR32, MCK_FR32 }, 0}, 6070 { X86::VXORPSYrr, "vxorps", Convert__Reg1_2__Reg1_1__Reg1_0, { MCK_VR256, MCK_VR256, MCK_VR256 }, 0}, 6071 { X86::VFsXORPSrm, "vxorps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6072 { X86::VXORPSrm, "vxorps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_FR32, MCK_FR32 }, 0}, 6073 { X86::VXORPSYrm, "vxorps", Convert__Reg1_2__Reg1_1__Mem5_0, { MCK_Mem, MCK_VR256, MCK_VR256 }, 0}, 6074 { X86::VZEROALL, "vzeroall", Convert, { }, 0}, 6075 { X86::VZEROUPPER, "vzeroupper", Convert, { }, 0}, 6076 { X86::WAIT, "wait", Convert, { }, 0}, 6077 { X86::WBINVD, "wbinvd", Convert, { }, 0}, 6078 { X86::WRFSBASE, "wrfsbasel", Convert__Reg1_0, { MCK_GR32 }, Feature_In64BitMode}, 6079 { X86::WRFSBASE64, "wrfsbaseq", Convert__Reg1_0, { MCK_GR64 }, Feature_In64BitMode}, 6080 { X86::WRGSBASE, "wrgsbasel", Convert__Reg1_0, { MCK_GR32 }, Feature_In64BitMode}, 6081 { X86::WRGSBASE64, "wrgsbaseq", Convert__Reg1_0, { MCK_GR64 }, Feature_In64BitMode}, 6082 { X86::WRMSR, "wrmsr", Convert, { }, 0}, 6083 { X86::XADD8rr, "xaddb", Convert__Reg1_1__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 6084 { X86::XADD8rm, "xaddb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 6085 { X86::XADD32rr, "xaddl", Convert__Reg1_1__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 6086 { X86::XADD32rm, "xaddl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 6087 { X86::XADD64rr, "xaddq", Convert__Reg1_1__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 6088 { X86::XADD64rm, "xaddq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 6089 { X86::XADD16rr, "xaddw", Convert__Reg1_1__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 6090 { X86::XADD16rm, "xaddw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 6091 { X86::XCHG8rr, "xchgb", Convert__Reg1_0__Tie0__Reg1_1, { MCK_GR8, MCK_GR8 }, 0}, 6092 { X86::XCHG8rm, "xchgb", Convert__Reg1_0__Tie0__Mem5_1, { MCK_GR8, MCK_Mem }, 0}, 6093 { X86::XCHG8rm, "xchgb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 6094 { X86::XCHG32ar64, "xchgl", Convert__Reg1_1, { MCK_EAX, MCK_GR32_NOAX }, Feature_In64BitMode}, 6095 { X86::XCHG32ar, "xchgl", Convert__Reg1_1, { MCK_EAX, MCK_GR32 }, Feature_In32BitMode}, 6096 { X86::XCHG32ar64, "xchgl", Convert__Reg1_0, { MCK_GR32_NOAX, MCK_EAX }, Feature_In64BitMode}, 6097 { X86::XCHG32ar, "xchgl", Convert__Reg1_0, { MCK_GR32, MCK_EAX }, Feature_In32BitMode}, 6098 { X86::XCHG32rr, "xchgl", Convert__Reg1_0__Tie0__Reg1_1, { MCK_GR32, MCK_GR32 }, 0}, 6099 { X86::XCHG32rm, "xchgl", Convert__Reg1_0__Tie0__Mem5_1, { MCK_GR32, MCK_Mem }, 0}, 6100 { X86::XCHG32rm, "xchgl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 6101 { X86::XCHG64ar, "xchgq", Convert__Reg1_1, { MCK_RAX, MCK_GR64 }, 0}, 6102 { X86::XCHG64ar, "xchgq", Convert__Reg1_0, { MCK_GR64, MCK_RAX }, 0}, 6103 { X86::XCHG64rr, "xchgq", Convert__Reg1_0__Tie0__Reg1_1, { MCK_GR64, MCK_GR64 }, 0}, 6104 { X86::XCHG64rm, "xchgq", Convert__Reg1_0__Tie0__Mem5_1, { MCK_GR64, MCK_Mem }, 0}, 6105 { X86::XCHG64rm, "xchgq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 6106 { X86::XCHG16ar, "xchgw", Convert__Reg1_1, { MCK_AX, MCK_GR16 }, 0}, 6107 { X86::XCHG16ar, "xchgw", Convert__Reg1_0, { MCK_GR16, MCK_AX }, 0}, 6108 { X86::XCHG16rr, "xchgw", Convert__Reg1_0__Tie0__Reg1_1, { MCK_GR16, MCK_GR16 }, 0}, 6109 { X86::XCHG16rm, "xchgw", Convert__Reg1_0__Tie0__Mem5_1, { MCK_GR16, MCK_Mem }, 0}, 6110 { X86::XCHG16rm, "xchgw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 6111 { X86::XCRYPTCBC, "xcryptcbc", Convert, { }, 0}, 6112 { X86::XCRYPTCFB, "xcryptcfb", Convert, { }, 0}, 6113 { X86::XCRYPTCTR, "xcryptctr", Convert, { }, 0}, 6114 { X86::XCRYPTECB, "xcryptecb", Convert, { }, 0}, 6115 { X86::XCRYPTOFB, "xcryptofb", Convert, { }, 0}, 6116 { X86::XGETBV, "xgetbv", Convert, { }, 0}, 6117 { X86::XLAT, "xlatb", Convert, { }, 0}, 6118 { X86::XOR8rr, "xorb", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR8, MCK_GR8 }, 0}, 6119 { X86::XOR8mr, "xorb", Convert__Mem5_1__Reg1_0, { MCK_GR8, MCK_Mem }, 0}, 6120 { X86::XOR8i8, "xorb", Convert__Imm1_0, { MCK_Imm, MCK_AL }, 0}, 6121 { X86::XOR8ri, "xorb", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR8 }, 0}, 6122 { X86::XOR8mi, "xorb", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 6123 { X86::XOR8rm, "xorb", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR8 }, 0}, 6124 { X86::XOR32rr, "xorl", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR32, MCK_GR32 }, 0}, 6125 { X86::XOR32mr, "xorl", Convert__Mem5_1__Reg1_0, { MCK_GR32, MCK_Mem }, 0}, 6126 { X86::XOR32ri8, "xorl", Convert__Reg1_1__Tie0__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_GR32 }, 0}, 6127 { X86::XOR32mi8, "xorl", Convert__Mem5_1__ImmSExti32i81_0, { MCK_ImmSExti32i8, MCK_Mem }, 0}, 6128 { X86::XOR32i32, "xorl", Convert__Imm1_0, { MCK_Imm, MCK_EAX }, 0}, 6129 { X86::XOR32ri, "xorl", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR32 }, 0}, 6130 { X86::XOR32mi, "xorl", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 6131 { X86::XOR32rm, "xorl", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR32 }, 0}, 6132 { X86::FsXORPDrr, "xorpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6133 { X86::XORPDrr, "xorpd", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6134 { X86::FsXORPDrm, "xorpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6135 { X86::XORPDrm, "xorpd", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6136 { X86::FsXORPSrr, "xorps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6137 { X86::XORPSrr, "xorps", Convert__Reg1_1__Tie0__Reg1_0, { MCK_FR32, MCK_FR32 }, 0}, 6138 { X86::FsXORPSrm, "xorps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6139 { X86::XORPSrm, "xorps", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_FR32 }, 0}, 6140 { X86::XOR64rr, "xorq", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR64, MCK_GR64 }, 0}, 6141 { X86::XOR64mr, "xorq", Convert__Mem5_1__Reg1_0, { MCK_GR64, MCK_Mem }, 0}, 6142 { X86::XOR64ri8, "xorq", Convert__Reg1_1__Tie0__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_GR64 }, 0}, 6143 { X86::XOR64mi8, "xorq", Convert__Mem5_1__ImmSExti64i81_0, { MCK_ImmSExti64i8, MCK_Mem }, 0}, 6144 { X86::XOR64i32, "xorq", Convert__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_RAX }, 0}, 6145 { X86::XOR64ri32, "xorq", Convert__Reg1_1__Tie0__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_GR64 }, 0}, 6146 { X86::XOR64mi32, "xorq", Convert__Mem5_1__ImmSExti64i321_0, { MCK_ImmSExti64i32, MCK_Mem }, 0}, 6147 { X86::XOR64rm, "xorq", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR64 }, 0}, 6148 { X86::XOR16rr, "xorw", Convert__Reg1_1__Tie0__Reg1_0, { MCK_GR16, MCK_GR16 }, 0}, 6149 { X86::XOR16mr, "xorw", Convert__Mem5_1__Reg1_0, { MCK_GR16, MCK_Mem }, 0}, 6150 { X86::XOR16ri8, "xorw", Convert__Reg1_1__Tie0__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_GR16 }, 0}, 6151 { X86::XOR16mi8, "xorw", Convert__Mem5_1__ImmSExti16i81_0, { MCK_ImmSExti16i8, MCK_Mem }, 0}, 6152 { X86::XOR16i16, "xorw", Convert__Imm1_0, { MCK_Imm, MCK_AX }, 0}, 6153 { X86::XOR16ri, "xorw", Convert__Reg1_1__Tie0__Imm1_0, { MCK_Imm, MCK_GR16 }, 0}, 6154 { X86::XOR16mi, "xorw", Convert__Mem5_1__Imm1_0, { MCK_Imm, MCK_Mem }, 0}, 6155 { X86::XOR16rm, "xorw", Convert__Reg1_1__Tie0__Mem5_0, { MCK_Mem, MCK_GR16 }, 0}, 6156 { X86::XRSTOR, "xrstor", Convert__Mem5_0, { MCK_Mem }, 0}, 6157 { X86::XRSTOR64, "xrstorq", Convert__Mem5_0, { MCK_Mem }, Feature_In64BitMode}, 6158 { X86::XSAVE, "xsave", Convert__Mem5_0, { MCK_Mem }, 0}, 6159 { X86::XSAVEOPT, "xsaveopt", Convert__Mem5_0, { MCK_Mem }, 0}, 6160 { X86::XSAVEOPT64, "xsaveoptq", Convert__Mem5_0, { MCK_Mem }, Feature_In64BitMode}, 6161 { X86::XSAVE64, "xsaveq", Convert__Mem5_0, { MCK_Mem }, Feature_In64BitMode}, 6162 { X86::XSETBV, "xsetbv", Convert, { }, 0}, 6163 { X86::XSHA1, "xsha1", Convert, { }, 0}, 6164 { X86::XSHA256, "xsha256", Convert, { }, 0}, 6165 { X86::XSTORE, "xstore", Convert, { }, 0}, 6166 { X86::XSTORE, "xstorerng", Convert, { }, 0}, 6167}; 6168 6169bool X86ATTAsmParser:: 6170MnemonicIsValid(StringRef Mnemonic) { 6171 // Search the table. 6172 std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange = 6173 std::equal_range(MatchTable, MatchTable+3300, Mnemonic, LessOpcode()); 6174 return MnemonicRange.first != MnemonicRange.second; 6175} 6176 6177unsigned X86ATTAsmParser:: 6178MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*> &Operands, 6179 MCInst &Inst, unsigned &ErrorInfo) { 6180 // Get the current feature set. 6181 unsigned AvailableFeatures = getAvailableFeatures(); 6182 6183 // Get the instruction mnemonic, which is the first token. 6184 StringRef Mnemonic = ((X86Operand*)Operands[0])->getToken(); 6185 6186 // Process all MnemonicAliases to remap the mnemonic. 6187 ApplyMnemonicAliases(Mnemonic, AvailableFeatures); 6188 6189 // Eliminate obvious mismatches. 6190 if (Operands.size() > 6) { 6191 ErrorInfo = 6; 6192 return Match_InvalidOperand; 6193 } 6194 6195 // Some state to try to produce better error messages. 6196 bool HadMatchOtherThanFeatures = false; 6197 bool HadMatchOtherThanPredicate = false; 6198 unsigned RetCode = Match_InvalidOperand; 6199 // Set ErrorInfo to the operand that mismatches if it is 6200 // wrong for all instances of the instruction. 6201 ErrorInfo = ~0U; 6202 // Search the table. 6203 std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange = 6204 std::equal_range(MatchTable, MatchTable+3300, Mnemonic, LessOpcode()); 6205 6206 // Return a more specific error code if no mnemonics match. 6207 if (MnemonicRange.first == MnemonicRange.second) 6208 return Match_MnemonicFail; 6209 6210 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 6211 it != ie; ++it) { 6212 // equal_range guarantees that instruction mnemonic matches. 6213 assert(Mnemonic == it->Mnemonic); 6214 bool OperandsValid = true; 6215 for (unsigned i = 0; i != 5; ++i) { 6216 if (i + 1 >= Operands.size()) { 6217 OperandsValid = (it->Classes[i] == InvalidMatchClass); 6218 break; 6219 } 6220 if (ValidateOperandClass(Operands[i+1], it->Classes[i])) 6221 continue; 6222 // If this operand is broken for all of the instances of this 6223 // mnemonic, keep track of it so we can report loc info. 6224 if (it == MnemonicRange.first || ErrorInfo <= i+1) 6225 ErrorInfo = i+1; 6226 // Otherwise, just reject this instance of the mnemonic. 6227 OperandsValid = false; 6228 break; 6229 } 6230 6231 if (!OperandsValid) continue; 6232 if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) { 6233 HadMatchOtherThanFeatures = true; 6234 continue; 6235 } 6236 6237 // We have selected a definite instruction, convert the parsed 6238 // operands into the appropriate MCInst. 6239 if (!ConvertToMCInst(it->ConvertFn, Inst, 6240 it->Opcode, Operands)) 6241 return Match_ConversionFail; 6242 6243 // We have a potential match. Check the target predicate to 6244 // handle any context sensitive constraints. 6245 unsigned MatchResult; 6246 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { 6247 Inst.clear(); 6248 RetCode = MatchResult; 6249 HadMatchOtherThanPredicate = true; 6250 continue; 6251 } 6252 6253 return Match_Success; 6254 } 6255 6256 // Okay, we had no match. Try to return a useful error code. 6257 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures) return RetCode; 6258 return Match_MissingFeature; 6259} 6260 6261#endif // GET_MATCHER_IMPLEMENTATION 6262 6263