1 // Copyright 2015, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28 // --------------------------------------------------------------------- 29 // This file is auto generated using tools/generate_simulator_traces.py. 30 // 31 // PLEASE DO NOT EDIT. 32 // --------------------------------------------------------------------- 33 34 #ifndef VIXL_SIM_FNEG_D_TRACE_AARCH64_H_ 35 #define VIXL_SIM_FNEG_D_TRACE_AARCH64_H_ 36 37 const uint64_t kExpected_fneg_d[] = { 38 0x8000000000000000, 39 0x8010000000000000, 40 0xbfdfffffffffffff, 41 0xbfe0000000000000, 42 0xbfe0000000000001, 43 0xbfefffffffffffff, 44 0xbff0000000000000, 45 0xbff0000000000001, 46 0xbff8000000000000, 47 0xc024000000000000, 48 0xffefffffffffffff, 49 0xfff0000000000000, 50 0xfff923456789abcd, 51 0xfff8000000000000, 52 0xfff123456789abcd, 53 0xfff0000000000000, 54 0x800123456789abcd, 55 0x800fffffffffffff, 56 0x8000000000000001, 57 0x0000000000000000, 58 0x0010000000000000, 59 0x3fdfffffffffffff, 60 0x3fe0000000000000, 61 0x3fe0000000000001, 62 0x3fefffffffffffff, 63 0x3ff0000000000000, 64 0x3ff0000000000001, 65 0x3ff8000000000000, 66 0x4024000000000000, 67 0x7fefffffffffffff, 68 0x7ff0000000000000, 69 0x7ff923456789abcd, 70 0x7ff8000000000000, 71 0x7ff123456789abcd, 72 0x7ff0000000000000, 73 0x000123456789abcd, 74 0x000fffffffffffff, 75 0x0000000000000001, 76 }; 77 const unsigned kExpectedCount_fneg_d = 38; 78 79 #endif // VIXL_SIM_FNEG_D_TRACE_AARCH64_H_ 80