1 // Copyright (c) 2012 The Chromium Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #include "base/cpu.h"
6 #include "build/build_config.h"
7
8 #include "testing/gtest/include/gtest/gtest.h"
9
10 #if _MSC_VER >= 1700
11 // C4752: found Intel(R) Advanced Vector Extensions; consider using /arch:AVX.
12 #pragma warning(disable: 4752)
13 #endif
14
15 // Tests whether we can run extended instructions represented by the CPU
16 // information. This test actually executes some extended instructions (such as
17 // MMX, SSE, etc.) supported by the CPU and sees we can run them without
18 // "undefined instruction" exceptions. That is, this test succeeds when this
19 // test finishes without a crash.
TEST(CPU,RunExtendedInstructions)20 TEST(CPU, RunExtendedInstructions) {
21 #if defined(ARCH_CPU_X86_FAMILY)
22 // Retrieve the CPU information.
23 base::CPU cpu;
24
25 ASSERT_TRUE(cpu.has_mmx());
26 ASSERT_TRUE(cpu.has_sse());
27 ASSERT_TRUE(cpu.has_sse2());
28
29 // GCC and clang instruction test.
30 #if defined(COMPILER_GCC)
31 // Execute an MMX instruction.
32 __asm__ __volatile__("emms\n" : : : "mm0");
33
34 // Execute an SSE instruction.
35 __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0");
36
37 // Execute an SSE 2 instruction.
38 __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0");
39
40 if (cpu.has_sse3()) {
41 // Execute an SSE 3 instruction.
42 __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
43 }
44
45 if (cpu.has_ssse3()) {
46 // Execute a Supplimental SSE 3 instruction.
47 __asm__ __volatile__("psignb %%xmm0, %%xmm0\n" : : : "xmm0");
48 }
49
50 if (cpu.has_sse41()) {
51 // Execute an SSE 4.1 instruction.
52 __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0");
53 }
54
55 if (cpu.has_sse42()) {
56 // Execute an SSE 4.2 instruction.
57 __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax");
58 }
59
60 if (cpu.has_avx()) {
61 // Execute an AVX instruction.
62 __asm__ __volatile__("vzeroupper\n" : : : "xmm0");
63 }
64
65 if (cpu.has_avx2()) {
66 // Execute an AVX 2 instruction.
67 __asm__ __volatile__("vpunpcklbw %%ymm0, %%ymm0, %%ymm0\n" : : : "xmm0");
68 }
69
70 // Visual C 32 bit and ClangCL 32/64 bit test.
71 #elif defined(COMPILER_MSVC) && (defined(ARCH_CPU_32_BITS) || \
72 (defined(ARCH_CPU_64_BITS) && defined(__clang__)))
73
74 // Execute an MMX instruction.
75 __asm emms;
76
77 // Execute an SSE instruction.
78 __asm xorps xmm0, xmm0;
79
80 // Execute an SSE 2 instruction.
81 __asm psrldq xmm0, 0;
82
83 if (cpu.has_sse3()) {
84 // Execute an SSE 3 instruction.
85 __asm addsubpd xmm0, xmm0;
86 }
87
88 if (cpu.has_ssse3()) {
89 // Execute a Supplimental SSE 3 instruction.
90 __asm psignb xmm0, xmm0;
91 }
92
93 if (cpu.has_sse41()) {
94 // Execute an SSE 4.1 instruction.
95 __asm pmuldq xmm0, xmm0;
96 }
97
98 if (cpu.has_sse42()) {
99 // Execute an SSE 4.2 instruction.
100 __asm crc32 eax, eax;
101 }
102
103 // Visual C 2012 required for AVX.
104 #if _MSC_VER >= 1700
105 if (cpu.has_avx()) {
106 // Execute an AVX instruction.
107 __asm vzeroupper;
108 }
109
110 if (cpu.has_avx2()) {
111 // Execute an AVX 2 instruction.
112 __asm vpunpcklbw ymm0, ymm0, ymm0
113 }
114 #endif // _MSC_VER >= 1700
115 #endif // defined(COMPILER_GCC)
116 #endif // defined(ARCH_CPU_X86_FAMILY)
117 }
118