1 /* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_UTILS_MIPS_CONSTANTS_MIPS_H_ 18 #define ART_COMPILER_UTILS_MIPS_CONSTANTS_MIPS_H_ 19 20 #include <iosfwd> 21 22 #include "arch/mips/registers_mips.h" 23 #include "base/logging.h" 24 #include "base/macros.h" 25 #include "globals.h" 26 27 namespace art { 28 namespace mips { 29 30 // Values for double-precision floating point registers. 31 enum DRegister { 32 D0 = 0, 33 D1 = 1, 34 D2 = 2, 35 D3 = 3, 36 D4 = 4, 37 D5 = 5, 38 D6 = 6, 39 D7 = 7, 40 D8 = 8, 41 D9 = 9, 42 D10 = 10, 43 D11 = 11, 44 D12 = 12, 45 D13 = 13, 46 D14 = 14, 47 D15 = 15, 48 kNumberOfDRegisters = 16, 49 kNumberOfOverlappingDRegisters = 16, 50 kNoDRegister = -1, 51 }; 52 std::ostream& operator<<(std::ostream& os, const DRegister& rhs); 53 54 // Constants used for the decoding or encoding of the individual fields of instructions. 55 enum InstructionFields { 56 kOpcodeShift = 26, 57 kOpcodeBits = 6, 58 kRsShift = 21, 59 kRsBits = 5, 60 kRtShift = 16, 61 kRtBits = 5, 62 kRdShift = 11, 63 kRdBits = 5, 64 kShamtShift = 6, 65 kShamtBits = 5, 66 kFunctShift = 0, 67 kFunctBits = 6, 68 69 kFmtShift = 21, 70 kFmtBits = 5, 71 kFtShift = 16, 72 kFtBits = 5, 73 kFsShift = 11, 74 kFsBits = 5, 75 kFdShift = 6, 76 kFdBits = 5, 77 78 kMsaOperationShift = 23, 79 kMsaELMOperationShift = 22, 80 kMsa2ROperationShift = 18, 81 kMsa2RFOperationShift = 17, 82 kDfShift = 21, 83 kDfMShift = 16, 84 kDf2RShift = 16, 85 kDfNShift = 16, 86 kWtShift = 16, 87 kWtBits = 5, 88 kWsShift = 11, 89 kWsBits = 5, 90 kWdShift = 6, 91 kWdBits = 5, 92 kS10Shift = 16, 93 kI10Shift = 11, 94 kS10MinorShift = 2, 95 96 kBranchOffsetMask = 0x0000ffff, 97 kJumpOffsetMask = 0x03ffffff, 98 99 kMsaMajorOpcode = 0x1e, 100 kMsaDfMByteMask = 0x70, 101 kMsaDfMHalfwordMask = 0x60, 102 kMsaDfMWordMask = 0x40, 103 kMsaDfMDoublewordMask = 0x00, 104 kMsaDfNByteMask = 0x00, 105 kMsaDfNHalfwordMask = 0x20, 106 kMsaDfNWordMask = 0x30, 107 kMsaDfNDoublewordMask = 0x38, 108 kMsaS10Mask = 0x3ff, 109 }; 110 111 enum ScaleFactor { 112 TIMES_1 = 0, 113 TIMES_2 = 1, 114 TIMES_4 = 2, 115 TIMES_8 = 3 116 }; 117 118 class Instr { 119 public: 120 static const uint32_t kBreakPointInstruction = 0x0000000D; 121 IsBreakPoint()122 bool IsBreakPoint() { 123 return ((*reinterpret_cast<const uint32_t*>(this)) & 0xFC0000CF) == kBreakPointInstruction; 124 } 125 126 // Instructions are read out of a code stream. The only way to get a 127 // reference to an instruction is to convert a pointer. There is no way 128 // to allocate or create instances of class Instr. 129 // Use the At(pc) function to create references to Instr. At(uintptr_t pc)130 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); } 131 132 private: 133 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); 134 }; 135 136 } // namespace mips 137 } // namespace art 138 139 #endif // ART_COMPILER_UTILS_MIPS_CONSTANTS_MIPS_H_ 140