1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /*****************************************************************************/
22 /* */
23 /* File Name : ih264d_api.c */
24 /* */
25 /* Description : Has all API related functions */
26 /* */
27 /* */
28 /* List of Functions : api_check_struct_sanity */
29 /* ih264d_set_processor */
30 /* ih264d_create */
31 /* ih264d_delete */
32 /* ih264d_init */
33 /* ih264d_map_error */
34 /* ih264d_video_decode */
35 /* ih264d_get_version */
36 /* ih264d_get_display_frame */
37 /* ih264d_set_display_frame */
38 /* ih264d_set_flush_mode */
39 /* ih264d_get_status */
40 /* ih264d_get_buf_info */
41 /* ih264d_set_params */
42 /* ih264d_set_default_params */
43 /* ih264d_reset */
44 /* ih264d_ctl */
45 /* ih264d_rel_display_frame */
46 /* ih264d_set_degrade */
47 /* ih264d_get_frame_dimensions */
48 /* ih264d_set_num_cores */
49 /* ih264d_fill_output_struct_from_context */
50 /* ih264d_api_function */
51 /* */
52 /* Issues / Problems : None */
53 /* */
54 /* Revision History : */
55 /* */
56 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
57 /* 14 10 2008 100356(SKV) Draft */
58 /* */
59 /*****************************************************************************/
60 #include "ih264_typedefs.h"
61 #include "ih264_macros.h"
62 #include "ih264_platform_macros.h"
63 #include "ih264d_tables.h"
64 #include "iv.h"
65 #include "ivd.h"
66 #include "ih264d.h"
67 #include "ih264d_defs.h"
68
69 #include <string.h>
70 #include <limits.h>
71 #include <stddef.h>
72
73 #include "ih264d_inter_pred.h"
74
75 #include "ih264d_structs.h"
76 #include "ih264d_nal.h"
77 #include "ih264d_error_handler.h"
78
79 #include "ih264d_defs.h"
80
81 #include "ithread.h"
82 #include "ih264d_parse_slice.h"
83 #include "ih264d_function_selector.h"
84 #include "ih264_error.h"
85 #include "ih264_disp_mgr.h"
86 #include "ih264_buf_mgr.h"
87 #include "ih264d_deblocking.h"
88 #include "ih264d_parse_cavlc.h"
89 #include "ih264d_parse_cabac.h"
90 #include "ih264d_utils.h"
91 #include "ih264d_format_conv.h"
92 #include "ih264d_parse_headers.h"
93 #include "ih264d_thread_compute_bs.h"
94 #include <assert.h>
95
96
97 /*********************/
98 /* Codec Versioning */
99 /*********************/
100 //Move this to where it is used
101 #define CODEC_NAME "H264VDEC"
102 #define CODEC_RELEASE_TYPE "production"
103 #define CODEC_RELEASE_VER "05.00"
104 #define CODEC_VENDOR "ITTIAM"
105 #define MAXVERSION_STRLEN 511
106 #ifdef __ANDROID__
107 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
108 snprintf(version_string, MAXVERSION_STRLEN, \
109 "@(#)Id:%s_%s Ver:%s Released by %s", \
110 codec_name, codec_release_type, codec_release_ver, codec_vendor)
111 #else
112 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
113 snprintf(version_string, MAXVERSION_STRLEN, \
114 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \
115 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
116 #endif
117
118
119 #define MIN_IN_BUFS 1
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125 #define NUM_FRAMES_LIMIT_ENABLED 0
126
127 #if NUM_FRAMES_LIMIT_ENABLED
128 #define NUM_FRAMES_LIMIT 10000
129 #else
130 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
131 #endif
132
133
134 UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136 void *pv_api_ip,
137 void *pv_api_op);
138 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
139 void *pv_api_ip,
140 void *pv_api_op);
141
142 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
143
144 WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
145
146 void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
147
148 void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
149 void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
150
151 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
152 void *pv_api_ip,
153 void *pv_api_op);
154
155 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
156 ivd_video_decode_op_t *ps_dec_op);
157
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)158 static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
159 void *pv_api_ip,
160 void *pv_api_op)
161 {
162 IVD_API_COMMAND_TYPE_T e_cmd;
163 UWORD32 *pu4_api_ip;
164 UWORD32 *pu4_api_op;
165 UWORD32 i, j;
166
167 if(NULL == pv_api_op)
168 return (IV_FAIL);
169
170 if(NULL == pv_api_ip)
171 return (IV_FAIL);
172
173 pu4_api_ip = (UWORD32 *)pv_api_ip;
174 pu4_api_op = (UWORD32 *)pv_api_op;
175 e_cmd = *(pu4_api_ip + 1);
176
177 /* error checks on handle */
178 switch((WORD32)e_cmd)
179 {
180 case IVD_CMD_CREATE:
181 break;
182
183 case IVD_CMD_REL_DISPLAY_FRAME:
184 case IVD_CMD_SET_DISPLAY_FRAME:
185 case IVD_CMD_GET_DISPLAY_FRAME:
186 case IVD_CMD_VIDEO_DECODE:
187 case IVD_CMD_DELETE:
188 case IVD_CMD_VIDEO_CTL:
189 if(ps_handle == NULL)
190 {
191 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
192 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
193 return IV_FAIL;
194 }
195
196 if(ps_handle->u4_size != sizeof(iv_obj_t))
197 {
198 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
199 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
200 return IV_FAIL;
201 }
202
203 if(ps_handle->pv_fxns != ih264d_api_function)
204 {
205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
206 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
207 return IV_FAIL;
208 }
209
210 if(ps_handle->pv_codec_handle == NULL)
211 {
212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
213 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
214 return IV_FAIL;
215 }
216 break;
217 default:
218 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
219 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
220 return IV_FAIL;
221 }
222
223 switch((WORD32)e_cmd)
224 {
225 case IVD_CMD_CREATE:
226 {
227 ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip;
228 ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op;
229
230
231 ps_op->s_ivd_create_op_t.u4_error_code = 0;
232
233 if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t))
234 || (ps_ip->s_ivd_create_ip_t.u4_size
235 < sizeof(ivd_create_ip_t)))
236 {
237 ps_op->s_ivd_create_op_t.u4_error_code |= 1
238 << IVD_UNSUPPORTEDPARAM;
239 ps_op->s_ivd_create_op_t.u4_error_code |=
240 IVD_IP_API_STRUCT_SIZE_INCORRECT;
241 H264_DEC_DEBUG_PRINT("\n");
242 return (IV_FAIL);
243 }
244
245 if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t))
246 && (ps_op->s_ivd_create_op_t.u4_size
247 != sizeof(ivd_create_op_t)))
248 {
249 ps_op->s_ivd_create_op_t.u4_error_code |= 1
250 << IVD_UNSUPPORTEDPARAM;
251 ps_op->s_ivd_create_op_t.u4_error_code |=
252 IVD_OP_API_STRUCT_SIZE_INCORRECT;
253 H264_DEC_DEBUG_PRINT("\n");
254 return (IV_FAIL);
255 }
256
257
258 if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P)
259 && (ps_ip->s_ivd_create_ip_t.e_output_format
260 != IV_YUV_422ILE)
261 && (ps_ip->s_ivd_create_ip_t.e_output_format
262 != IV_RGB_565)
263 && (ps_ip->s_ivd_create_ip_t.e_output_format
264 != IV_YUV_420SP_UV)
265 && (ps_ip->s_ivd_create_ip_t.e_output_format
266 != IV_YUV_420SP_VU))
267 {
268 ps_op->s_ivd_create_op_t.u4_error_code |= 1
269 << IVD_UNSUPPORTEDPARAM;
270 ps_op->s_ivd_create_op_t.u4_error_code |=
271 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
272 H264_DEC_DEBUG_PRINT("\n");
273 return (IV_FAIL);
274 }
275
276 }
277 break;
278
279 case IVD_CMD_GET_DISPLAY_FRAME:
280 {
281 ih264d_get_display_frame_ip_t *ps_ip =
282 (ih264d_get_display_frame_ip_t *)pv_api_ip;
283 ih264d_get_display_frame_op_t *ps_op =
284 (ih264d_get_display_frame_op_t *)pv_api_op;
285
286 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
287
288 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
289 != sizeof(ih264d_get_display_frame_ip_t))
290 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
291 != sizeof(ivd_get_display_frame_ip_t)))
292 {
293 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
294 << IVD_UNSUPPORTEDPARAM;
295 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
296 IVD_IP_API_STRUCT_SIZE_INCORRECT;
297 return (IV_FAIL);
298 }
299
300 if((ps_op->s_ivd_get_display_frame_op_t.u4_size
301 != sizeof(ih264d_get_display_frame_op_t))
302 && (ps_op->s_ivd_get_display_frame_op_t.u4_size
303 != sizeof(ivd_get_display_frame_op_t)))
304 {
305 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
306 << IVD_UNSUPPORTEDPARAM;
307 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
308 IVD_OP_API_STRUCT_SIZE_INCORRECT;
309 return (IV_FAIL);
310 }
311 }
312 break;
313
314 case IVD_CMD_REL_DISPLAY_FRAME:
315 {
316 ih264d_rel_display_frame_ip_t *ps_ip =
317 (ih264d_rel_display_frame_ip_t *)pv_api_ip;
318 ih264d_rel_display_frame_op_t *ps_op =
319 (ih264d_rel_display_frame_op_t *)pv_api_op;
320
321 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
322
323 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
324 != sizeof(ih264d_rel_display_frame_ip_t))
325 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
326 != sizeof(ivd_rel_display_frame_ip_t)))
327 {
328 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
329 << IVD_UNSUPPORTEDPARAM;
330 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
331 IVD_IP_API_STRUCT_SIZE_INCORRECT;
332 return (IV_FAIL);
333 }
334
335 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
336 != sizeof(ih264d_rel_display_frame_op_t))
337 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
338 != sizeof(ivd_rel_display_frame_op_t)))
339 {
340 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
341 << IVD_UNSUPPORTEDPARAM;
342 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
343 IVD_OP_API_STRUCT_SIZE_INCORRECT;
344 return (IV_FAIL);
345 }
346
347 }
348 break;
349
350 case IVD_CMD_SET_DISPLAY_FRAME:
351 {
352 ih264d_set_display_frame_ip_t *ps_ip =
353 (ih264d_set_display_frame_ip_t *)pv_api_ip;
354 ih264d_set_display_frame_op_t *ps_op =
355 (ih264d_set_display_frame_op_t *)pv_api_op;
356 UWORD32 j;
357
358 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
359
360 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
361 != sizeof(ih264d_set_display_frame_ip_t))
362 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
363 != sizeof(ivd_set_display_frame_ip_t)))
364 {
365 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
366 << IVD_UNSUPPORTEDPARAM;
367 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
368 IVD_IP_API_STRUCT_SIZE_INCORRECT;
369 return (IV_FAIL);
370 }
371
372 if((ps_op->s_ivd_set_display_frame_op_t.u4_size
373 != sizeof(ih264d_set_display_frame_op_t))
374 && (ps_op->s_ivd_set_display_frame_op_t.u4_size
375 != sizeof(ivd_set_display_frame_op_t)))
376 {
377 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
378 << IVD_UNSUPPORTEDPARAM;
379 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
380 IVD_OP_API_STRUCT_SIZE_INCORRECT;
381 return (IV_FAIL);
382 }
383
384 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
385 {
386 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
387 << IVD_UNSUPPORTEDPARAM;
388 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
389 IVD_DISP_FRM_ZERO_OP_BUFS;
390 return IV_FAIL;
391 }
392
393 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
394 j++)
395 {
396 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
397 == 0)
398 {
399 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
400 << IVD_UNSUPPORTEDPARAM;
401 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
402 IVD_DISP_FRM_ZERO_OP_BUFS;
403 return IV_FAIL;
404 }
405
406 for(i = 0;
407 i
408 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
409 i++)
410 {
411 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
412 == NULL)
413 {
414 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
415 << IVD_UNSUPPORTEDPARAM;
416 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
417 IVD_DISP_FRM_OP_BUF_NULL;
418 return IV_FAIL;
419 }
420
421 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
422 == 0)
423 {
424 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
425 << IVD_UNSUPPORTEDPARAM;
426 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
427 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
428 return IV_FAIL;
429 }
430 }
431 }
432 }
433 break;
434
435 case IVD_CMD_VIDEO_DECODE:
436 {
437 ih264d_video_decode_ip_t *ps_ip =
438 (ih264d_video_decode_ip_t *)pv_api_ip;
439 ih264d_video_decode_op_t *ps_op =
440 (ih264d_video_decode_op_t *)pv_api_op;
441
442 H264_DEC_DEBUG_PRINT("The input bytes is: %d",
443 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
444 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
445
446 if(ps_ip->s_ivd_video_decode_ip_t.u4_size
447 != sizeof(ih264d_video_decode_ip_t)&&
448 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer))
449 {
450 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
451 << IVD_UNSUPPORTEDPARAM;
452 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
453 IVD_IP_API_STRUCT_SIZE_INCORRECT;
454 return (IV_FAIL);
455 }
456
457 if(ps_op->s_ivd_video_decode_op_t.u4_size
458 != sizeof(ih264d_video_decode_op_t)&&
459 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present))
460 {
461 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
462 << IVD_UNSUPPORTEDPARAM;
463 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
464 IVD_OP_API_STRUCT_SIZE_INCORRECT;
465 return (IV_FAIL);
466 }
467
468 }
469 break;
470
471 case IVD_CMD_DELETE:
472 {
473 ih264d_delete_ip_t *ps_ip =
474 (ih264d_delete_ip_t *)pv_api_ip;
475 ih264d_delete_op_t *ps_op =
476 (ih264d_delete_op_t *)pv_api_op;
477
478 ps_op->s_ivd_delete_op_t.u4_error_code = 0;
479
480 if(ps_ip->s_ivd_delete_ip_t.u4_size
481 != sizeof(ih264d_delete_ip_t))
482 {
483 ps_op->s_ivd_delete_op_t.u4_error_code |= 1
484 << IVD_UNSUPPORTEDPARAM;
485 ps_op->s_ivd_delete_op_t.u4_error_code |=
486 IVD_IP_API_STRUCT_SIZE_INCORRECT;
487 return (IV_FAIL);
488 }
489
490 if(ps_op->s_ivd_delete_op_t.u4_size
491 != sizeof(ih264d_delete_op_t))
492 {
493 ps_op->s_ivd_delete_op_t.u4_error_code |= 1
494 << IVD_UNSUPPORTEDPARAM;
495 ps_op->s_ivd_delete_op_t.u4_error_code |=
496 IVD_OP_API_STRUCT_SIZE_INCORRECT;
497 return (IV_FAIL);
498 }
499
500 }
501 break;
502
503 case IVD_CMD_VIDEO_CTL:
504 {
505 UWORD32 *pu4_ptr_cmd;
506 UWORD32 sub_command;
507
508 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
509 pu4_ptr_cmd += 2;
510 sub_command = *pu4_ptr_cmd;
511
512 switch(sub_command)
513 {
514 case IVD_CMD_CTL_SETPARAMS:
515 {
516 ih264d_ctl_set_config_ip_t *ps_ip;
517 ih264d_ctl_set_config_op_t *ps_op;
518 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
519 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
520
521 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
522 != sizeof(ih264d_ctl_set_config_ip_t))
523 {
524 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
525 << IVD_UNSUPPORTEDPARAM;
526 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
527 IVD_IP_API_STRUCT_SIZE_INCORRECT;
528 return IV_FAIL;
529 }
530 }
531 //no break; is needed here
532 case IVD_CMD_CTL_SETDEFAULT:
533 {
534 ih264d_ctl_set_config_op_t *ps_op;
535 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
536 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
537 != sizeof(ih264d_ctl_set_config_op_t))
538 {
539 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
540 << IVD_UNSUPPORTEDPARAM;
541 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
542 IVD_OP_API_STRUCT_SIZE_INCORRECT;
543 return IV_FAIL;
544 }
545 }
546 break;
547
548 case IVD_CMD_CTL_GETPARAMS:
549 {
550 ih264d_ctl_getstatus_ip_t *ps_ip;
551 ih264d_ctl_getstatus_op_t *ps_op;
552
553 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
554 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
555 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
556 != sizeof(ih264d_ctl_getstatus_ip_t))
557 {
558 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
559 << IVD_UNSUPPORTEDPARAM;
560 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
561 IVD_IP_API_STRUCT_SIZE_INCORRECT;
562 return IV_FAIL;
563 }
564 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
565 != sizeof(ih264d_ctl_getstatus_op_t))
566 {
567 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
568 << IVD_UNSUPPORTEDPARAM;
569 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
570 IVD_OP_API_STRUCT_SIZE_INCORRECT;
571 return IV_FAIL;
572 }
573 }
574 break;
575
576 case IVD_CMD_CTL_GETBUFINFO:
577 {
578 ih264d_ctl_getbufinfo_ip_t *ps_ip;
579 ih264d_ctl_getbufinfo_op_t *ps_op;
580 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
581 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
582
583 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
584 != sizeof(ih264d_ctl_getbufinfo_ip_t))
585 {
586 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
587 << IVD_UNSUPPORTEDPARAM;
588 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
589 IVD_IP_API_STRUCT_SIZE_INCORRECT;
590 return IV_FAIL;
591 }
592 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
593 != sizeof(ih264d_ctl_getbufinfo_op_t))
594 {
595 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
596 << IVD_UNSUPPORTEDPARAM;
597 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
598 IVD_OP_API_STRUCT_SIZE_INCORRECT;
599 return IV_FAIL;
600 }
601 }
602 break;
603
604 case IVD_CMD_CTL_GETVERSION:
605 {
606 ih264d_ctl_getversioninfo_ip_t *ps_ip;
607 ih264d_ctl_getversioninfo_op_t *ps_op;
608 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
609 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
610 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
611 != sizeof(ih264d_ctl_getversioninfo_ip_t))
612 {
613 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
614 << IVD_UNSUPPORTEDPARAM;
615 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
616 IVD_IP_API_STRUCT_SIZE_INCORRECT;
617 return IV_FAIL;
618 }
619 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
620 != sizeof(ih264d_ctl_getversioninfo_op_t))
621 {
622 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
623 << IVD_UNSUPPORTEDPARAM;
624 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
625 IVD_OP_API_STRUCT_SIZE_INCORRECT;
626 return IV_FAIL;
627 }
628 }
629 break;
630
631 case IVD_CMD_CTL_FLUSH:
632 {
633 ih264d_ctl_flush_ip_t *ps_ip;
634 ih264d_ctl_flush_op_t *ps_op;
635 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
636 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
637 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
638 != sizeof(ih264d_ctl_flush_ip_t))
639 {
640 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
641 << IVD_UNSUPPORTEDPARAM;
642 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
643 IVD_IP_API_STRUCT_SIZE_INCORRECT;
644 return IV_FAIL;
645 }
646 if(ps_op->s_ivd_ctl_flush_op_t.u4_size
647 != sizeof(ih264d_ctl_flush_op_t))
648 {
649 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
650 << IVD_UNSUPPORTEDPARAM;
651 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
652 IVD_OP_API_STRUCT_SIZE_INCORRECT;
653 return IV_FAIL;
654 }
655 }
656 break;
657
658 case IVD_CMD_CTL_RESET:
659 {
660 ih264d_ctl_reset_ip_t *ps_ip;
661 ih264d_ctl_reset_op_t *ps_op;
662 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
663 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
664 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
665 != sizeof(ih264d_ctl_reset_ip_t))
666 {
667 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
668 << IVD_UNSUPPORTEDPARAM;
669 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
670 IVD_IP_API_STRUCT_SIZE_INCORRECT;
671 return IV_FAIL;
672 }
673 if(ps_op->s_ivd_ctl_reset_op_t.u4_size
674 != sizeof(ih264d_ctl_reset_op_t))
675 {
676 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
677 << IVD_UNSUPPORTEDPARAM;
678 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
679 IVD_OP_API_STRUCT_SIZE_INCORRECT;
680 return IV_FAIL;
681 }
682 }
683 break;
684
685 case IH264D_CMD_CTL_DEGRADE:
686 {
687 ih264d_ctl_degrade_ip_t *ps_ip;
688 ih264d_ctl_degrade_op_t *ps_op;
689
690 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
691 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
692
693 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
694 {
695 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
696 ps_op->u4_error_code |=
697 IVD_IP_API_STRUCT_SIZE_INCORRECT;
698 return IV_FAIL;
699 }
700
701 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
702 {
703 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
704 ps_op->u4_error_code |=
705 IVD_OP_API_STRUCT_SIZE_INCORRECT;
706 return IV_FAIL;
707 }
708
709 if((ps_ip->i4_degrade_pics < 0)
710 || (ps_ip->i4_degrade_pics > 4)
711 || (ps_ip->i4_nondegrade_interval < 0)
712 || (ps_ip->i4_degrade_type < 0)
713 || (ps_ip->i4_degrade_type > 15))
714 {
715 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
716 return IV_FAIL;
717 }
718
719 break;
720 }
721
722 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
723 {
724 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
725 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
726
727 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
728 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
729
730 if(ps_ip->u4_size
731 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
732 {
733 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
734 ps_op->u4_error_code |=
735 IVD_IP_API_STRUCT_SIZE_INCORRECT;
736 return IV_FAIL;
737 }
738
739 if(ps_op->u4_size
740 != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
741 {
742 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
743 ps_op->u4_error_code |=
744 IVD_OP_API_STRUCT_SIZE_INCORRECT;
745 return IV_FAIL;
746 }
747
748 break;
749 }
750 case IH264D_CMD_CTL_GET_VUI_PARAMS:
751 {
752 ih264d_ctl_get_vui_params_ip_t *ps_ip;
753 ih264d_ctl_get_vui_params_op_t *ps_op;
754
755 ps_ip =
756 (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
757 ps_op =
758 (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
759
760 if(ps_ip->u4_size
761 != sizeof(ih264d_ctl_get_vui_params_ip_t))
762 {
763 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
764 ps_op->u4_error_code |=
765 IVD_IP_API_STRUCT_SIZE_INCORRECT;
766 return IV_FAIL;
767 }
768
769 if(ps_op->u4_size
770 != sizeof(ih264d_ctl_get_vui_params_op_t))
771 {
772 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
773 ps_op->u4_error_code |=
774 IVD_OP_API_STRUCT_SIZE_INCORRECT;
775 return IV_FAIL;
776 }
777
778 break;
779 }
780 case IH264D_CMD_CTL_SET_NUM_CORES:
781 {
782 ih264d_ctl_set_num_cores_ip_t *ps_ip;
783 ih264d_ctl_set_num_cores_op_t *ps_op;
784
785 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
786 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
787
788 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
789 {
790 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
791 ps_op->u4_error_code |=
792 IVD_IP_API_STRUCT_SIZE_INCORRECT;
793 return IV_FAIL;
794 }
795
796 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
797 {
798 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
799 ps_op->u4_error_code |=
800 IVD_OP_API_STRUCT_SIZE_INCORRECT;
801 return IV_FAIL;
802 }
803
804 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
805 && (ps_ip->u4_num_cores != 3)
806 && (ps_ip->u4_num_cores != 4))
807 {
808 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
809 return IV_FAIL;
810 }
811 break;
812 }
813 case IH264D_CMD_CTL_SET_PROCESSOR:
814 {
815 ih264d_ctl_set_processor_ip_t *ps_ip;
816 ih264d_ctl_set_processor_op_t *ps_op;
817
818 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
819 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
820
821 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
822 {
823 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
824 ps_op->u4_error_code |=
825 IVD_IP_API_STRUCT_SIZE_INCORRECT;
826 return IV_FAIL;
827 }
828
829 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
830 {
831 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
832 ps_op->u4_error_code |=
833 IVD_OP_API_STRUCT_SIZE_INCORRECT;
834 return IV_FAIL;
835 }
836
837 break;
838 }
839 default:
840 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
841 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
842 return IV_FAIL;
843 break;
844 }
845 }
846 break;
847 }
848
849 return IV_SUCCESS;
850 }
851
852
853 /**
854 *******************************************************************************
855 *
856 * @brief
857 * Sets Processor type
858 *
859 * @par Description:
860 * Sets Processor type
861 *
862 * @param[in] ps_codec_obj
863 * Pointer to codec object at API level
864 *
865 * @param[in] pv_api_ip
866 * Pointer to input argument structure
867 *
868 * @param[out] pv_api_op
869 * Pointer to output argument structure
870 *
871 * @returns Status
872 *
873 * @remarks
874 *
875 *
876 *******************************************************************************
877 */
878
ih264d_set_processor(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)879 WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
880 {
881 ih264d_ctl_set_processor_ip_t *ps_ip;
882 ih264d_ctl_set_processor_op_t *ps_op;
883 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
884
885 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
886 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
887
888 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
889 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
890
891 ih264d_init_function_ptr(ps_codec);
892
893 ps_op->u4_error_code = 0;
894 return IV_SUCCESS;
895 }
896
897
898 /**************************************************************************
899 * \if Function name : ih264d_init_decoder \endif
900 *
901 *
902 * \brief
903 * Initializes the decoder
904 *
905 * \param apiVersion : Version of the api being used.
906 * \param errorHandlingMechanism : Mechanism to be used for errror handling.
907 * \param postFilteringType: Type of post filtering operation to be used.
908 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
909 * \param uc_dispBufs: Number of Display Buffers.
910 * \param p_NALBufAPI: Pointer to NAL Buffer API.
911 * \param p_DispBufAPI: Pointer to Display Buffer API.
912 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
913 * for memory allocation and freeing.
914 *
915 * \return
916 * 0 on Success and -1 on error
917 *
918 **************************************************************************
919 */
ih264d_init_decoder(void * ps_dec_params)920 void ih264d_init_decoder(void * ps_dec_params)
921 {
922 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
923 dec_slice_params_t *ps_cur_slice;
924 pocstruct_t *ps_prev_poc, *ps_cur_poc;
925 WORD32 size;
926
927 size = sizeof(pred_info_t) * 2 * 32;
928 memset(ps_dec->ps_pred, 0 , size);
929
930 size = sizeof(disp_mgr_t);
931 memset(ps_dec->pv_disp_buf_mgr, 0 , size);
932
933 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
934 memset(ps_dec->pv_pic_buf_mgr, 0, size);
935
936 size = sizeof(dec_err_status_t);
937 memset(ps_dec->ps_dec_err_status, 0, size);
938
939 size = sizeof(sei);
940 memset(ps_dec->ps_sei, 0, size);
941
942 size = sizeof(dpb_commands_t);
943 memset(ps_dec->ps_dpb_cmds, 0, size);
944
945 size = sizeof(dec_bit_stream_t);
946 memset(ps_dec->ps_bitstrm, 0, size);
947
948 size = sizeof(dec_slice_params_t);
949 memset(ps_dec->ps_cur_slice, 0, size);
950
951 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
952 memset(ps_dec->pv_scratch_sps_pps, 0, size);
953
954 size = sizeof(ctxt_inc_mb_info_t);
955 memset(ps_dec->ps_left_mb_ctxt_info, 0, size);
956
957 size = (sizeof(neighbouradd_t) << 2);
958 memset(ps_dec->ps_left_mvpred_addr, 0 ,size);
959
960 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
961 memset(ps_dec->pv_mv_buf_mgr, 0, size);
962
963 /* Free any dynamic buffers that are allocated */
964 ih264d_free_dynamic_bufs(ps_dec);
965
966 {
967 UWORD8 i;
968 struct pic_buffer_t *ps_init_dpb;
969 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0];
970 for(i = 0; i < 2 * MAX_REF_BUFS; i++)
971 {
972 ps_init_dpb->pu1_buf1 = NULL;
973 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
974 ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb;
975 ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb;
976 ps_init_dpb++;
977 }
978
979 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0];
980 for(i = 0; i < 2 * MAX_REF_BUFS; i++)
981 {
982 ps_init_dpb->pu1_buf1 = NULL;
983 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
984 ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb;
985 ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb;
986 ps_init_dpb++;
987 }
988 }
989
990 ps_cur_slice = ps_dec->ps_cur_slice;
991 ps_dec->init_done = 0;
992
993 ps_dec->u4_num_cores = 1;
994
995 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
996
997 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
998 ps_dec->u4_app_disable_deblk_frm = 0;
999 ps_dec->i4_degrade_type = 0;
1000 ps_dec->i4_degrade_pics = 0;
1001
1002 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE;
1003 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE;
1004
1005 memset(ps_dec->ps_pps, 0,
1006 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1007 memset(ps_dec->ps_sps, 0,
1008 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1009
1010 /* Initialization of function pointers ih264d_deblock_picture function*/
1011
1012 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1013 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1014
1015 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1016
1017 ps_dec->u4_num_fld_in_frm = 0;
1018
1019 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1020
1021 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1022 ps_dec->ps_sei->u1_is_valid = 0;
1023
1024 /* decParams Initializations */
1025 ps_dec->ps_cur_pps = NULL;
1026 ps_dec->ps_cur_sps = NULL;
1027 ps_dec->u1_init_dec_flag = 0;
1028 ps_dec->u1_first_slice_in_stream = 1;
1029 ps_dec->u1_last_pic_not_decoded = 0;
1030 ps_dec->u4_app_disp_width = 0;
1031 ps_dec->i4_header_decoded = 0;
1032 ps_dec->u4_total_frames_decoded = 0;
1033
1034 ps_dec->i4_error_code = 0;
1035 ps_dec->i4_content_type = -1;
1036 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1037
1038 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1039 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1040 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1041 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1042 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1043
1044 ps_dec->u1_pr_sl_type = 0xFF;
1045 ps_dec->u2_mbx = 0xffff;
1046 ps_dec->u2_mby = 0;
1047 ps_dec->u2_total_mbs_coded = 0;
1048
1049 /* POC initializations */
1050 ps_prev_poc = &ps_dec->s_prev_pic_poc;
1051 ps_cur_poc = &ps_dec->s_cur_pic_poc;
1052 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1053 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1054 ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1055 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1056 ps_prev_poc->i4_delta_pic_order_cnt[0] =
1057 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1058 ps_prev_poc->i4_delta_pic_order_cnt[1] =
1059 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1060 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1061 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1062 0;
1063 ps_prev_poc->i4_bottom_field_order_count =
1064 ps_cur_poc->i4_bottom_field_order_count = 0;
1065 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1066 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1067 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1068 ps_cur_slice->u1_mmco_equalto5 = 0;
1069 ps_cur_slice->u2_frame_num = 0;
1070
1071 ps_dec->i4_max_poc = 0;
1072 ps_dec->i4_prev_max_display_seq = 0;
1073 ps_dec->u1_recon_mb_grp = 4;
1074
1075 /* Field PIC initializations */
1076 ps_dec->u1_second_field = 0;
1077 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1078
1079 /* Set the cropping parameters as zero */
1080 ps_dec->u2_crop_offset_y = 0;
1081 ps_dec->u2_crop_offset_uv = 0;
1082
1083 /* The Initial Frame Rate Info is not Present */
1084 ps_dec->i4_vui_frame_rate = -1;
1085 ps_dec->i4_pic_type = -1;
1086 ps_dec->i4_frametype = -1;
1087 ps_dec->i4_content_type = -1;
1088
1089 ps_dec->u1_res_changed = 0;
1090
1091
1092 ps_dec->u1_frame_decoded_flag = 0;
1093
1094 /* Set the default frame seek mask mode */
1095 ps_dec->u4_skip_frm_mask = SKIP_NONE;
1096
1097 /********************************************************/
1098 /* Initialize CAVLC residual decoding function pointers */
1099 /********************************************************/
1100 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1101 ps_dec->pf_cavlc_4x4res_block[1] =
1102 ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1103 ps_dec->pf_cavlc_4x4res_block[2] =
1104 ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1105
1106 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1107 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1108
1109 ps_dec->pf_cavlc_parse_8x8block[0] =
1110 ih264d_cavlc_parse_8x8block_none_available;
1111 ps_dec->pf_cavlc_parse_8x8block[1] =
1112 ih264d_cavlc_parse_8x8block_left_available;
1113 ps_dec->pf_cavlc_parse_8x8block[2] =
1114 ih264d_cavlc_parse_8x8block_top_available;
1115 ps_dec->pf_cavlc_parse_8x8block[3] =
1116 ih264d_cavlc_parse_8x8block_both_available;
1117
1118 /***************************************************************************/
1119 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1120 /***************************************************************************/
1121 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1122 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1123
1124 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1125 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1126
1127 ps_dec->pf_fill_bs_xtra_left_edge[0] =
1128 ih264d_fill_bs_xtra_left_edge_cur_frm;
1129 ps_dec->pf_fill_bs_xtra_left_edge[1] =
1130 ih264d_fill_bs_xtra_left_edge_cur_fld;
1131
1132 /* Initialize Reference Pic Buffers */
1133 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1134
1135 ps_dec->u2_prv_frame_num = 0;
1136 ps_dec->u1_top_bottom_decoded = 0;
1137 ps_dec->u1_dangling_field = 0;
1138
1139 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1140
1141 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1142 ps_dec->pi1_left_ref_idx_ctxt_inc =
1143 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1144 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1145
1146 /* ! */
1147 /* Initializing flush frame u4_flag */
1148 ps_dec->u1_flushfrm = 0;
1149
1150 {
1151 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1152 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1153 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1154 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1155 }
1156
1157 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1158 memset(ps_dec->u4_disp_buf_mapping, 0,
1159 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1160 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1161 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1162 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t));
1163
1164 ih264d_init_arch(ps_dec);
1165 ih264d_init_function_ptr(ps_dec);
1166 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
1167 ps_dec->init_done = 1;
1168
1169 }
ih264d_free_static_bufs(iv_obj_t * dec_hdl)1170 WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl)
1171 {
1172 dec_struct_t *ps_dec;
1173
1174 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1175 void *pv_mem_ctxt;
1176
1177 ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1178 pf_aligned_free = ps_dec->pf_aligned_free;
1179 pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1180
1181 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps);
1182 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps);
1183 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle);
1184 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle);
1185 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr);
1186 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred);
1187 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr);
1188 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr);
1189 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base);
1190 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status);
1191 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei);
1192 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds);
1193 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm);
1194 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice);
1195 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps);
1196 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static);
1197 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base);
1198 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t);
1199 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info);
1200 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base);
1201 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1);
1202 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer);
1203 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base);
1204 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat);
1205 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat);
1206 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr);
1207 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr);
1208 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base);
1209 PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle);
1210
1211 if(dec_hdl)
1212 {
1213 pf_aligned_free(pv_mem_ctxt, dec_hdl);
1214 }
1215 return IV_SUCCESS;
1216 }
1217 /*****************************************************************************/
1218 /* */
1219 /* Function Name : ih264d_create */
1220 /* */
1221 /* Description : creates decoder */
1222 /* */
1223 /* Inputs :iv_obj_t decoder handle */
1224 /* :pv_api_ip pointer to input structure */
1225 /* :pv_api_op pointer to output structure */
1226 /* Outputs : */
1227 /* Returns : void */
1228 /* */
1229 /* Issues : none */
1230 /* */
1231 /* Revision History: */
1232 /* */
1233 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1234 /* 22 10 2008 100356 Draft */
1235 /* */
1236 /*****************************************************************************/
ih264d_allocate_static_bufs(iv_obj_t ** dec_hdl,void * pv_api_ip,void * pv_api_op)1237 WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op)
1238 {
1239 ih264d_create_ip_t *ps_create_ip;
1240 ih264d_create_op_t *ps_create_op;
1241 void *pv_buf;
1242 UWORD8 *pu1_buf;
1243 dec_struct_t *ps_dec;
1244 void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size);
1245 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1246 void *pv_mem_ctxt;
1247 WORD32 size;
1248
1249 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1250 ps_create_op = (ih264d_create_op_t *)pv_api_op;
1251
1252 ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1253
1254 pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc;
1255 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1256 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1257
1258 /* Initialize return handle to NULL */
1259 ps_create_op->s_ivd_create_op_t.pv_handle = NULL;
1260 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t));
1261 RETURN_IF((NULL == pv_buf), IV_FAIL);
1262 *dec_hdl = (iv_obj_t *)pv_buf;
1263 ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl;
1264
1265 (*dec_hdl)->pv_codec_handle = NULL;
1266 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t));
1267 RETURN_IF((NULL == pv_buf), IV_FAIL);
1268 (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf;
1269 ps_dec = (dec_struct_t *)pv_buf;
1270
1271 memset(ps_dec, 0, sizeof(dec_struct_t));
1272
1273 #ifndef LOGO_EN
1274 ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf;
1275 #else
1276 ps_dec->u4_share_disp_buf = 0;
1277 #endif
1278
1279 ps_dec->u1_chroma_format =
1280 (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format);
1281
1282 if((ps_dec->u1_chroma_format != IV_YUV_420P)
1283 && (ps_dec->u1_chroma_format
1284 != IV_YUV_420SP_UV)
1285 && (ps_dec->u1_chroma_format
1286 != IV_YUV_420SP_VU))
1287 {
1288 ps_dec->u4_share_disp_buf = 0;
1289 }
1290
1291 ps_dec->pf_aligned_alloc = pf_aligned_alloc;
1292 ps_dec->pf_aligned_free = pf_aligned_free;
1293 ps_dec->pv_mem_ctxt = pv_mem_ctxt;
1294
1295
1296 size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS);
1297 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1298 RETURN_IF((NULL == pv_buf), IV_FAIL);
1299 ps_dec->ps_sps = pv_buf;
1300
1301 size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS;
1302 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1303 RETURN_IF((NULL == pv_buf), IV_FAIL);
1304 ps_dec->ps_pps = pv_buf;
1305
1306 size = ithread_get_handle_size();
1307 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1308 RETURN_IF((NULL == pv_buf), IV_FAIL);
1309 ps_dec->pv_dec_thread_handle = pv_buf;
1310
1311 size = ithread_get_handle_size();
1312 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1313 RETURN_IF((NULL == pv_buf), IV_FAIL);
1314 ps_dec->pv_bs_deblk_thread_handle = pv_buf;
1315
1316 size = sizeof(dpb_manager_t);
1317 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1318 RETURN_IF((NULL == pv_buf), IV_FAIL);
1319 ps_dec->ps_dpb_mgr = pv_buf;
1320
1321 size = sizeof(pred_info_t) * 2 * 32;
1322 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1323 RETURN_IF((NULL == pv_buf), IV_FAIL);
1324 ps_dec->ps_pred = pv_buf;
1325
1326 size = sizeof(disp_mgr_t);
1327 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1328 RETURN_IF((NULL == pv_buf), IV_FAIL);
1329 ps_dec->pv_disp_buf_mgr = pv_buf;
1330
1331 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1332 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1333 RETURN_IF((NULL == pv_buf), IV_FAIL);
1334 ps_dec->pv_pic_buf_mgr = pv_buf;
1335
1336 size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
1337 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1338 RETURN_IF((NULL == pv_buf), IV_FAIL);
1339 ps_dec->ps_pic_buf_base = pv_buf;
1340
1341 size = sizeof(dec_err_status_t);
1342 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1343 RETURN_IF((NULL == pv_buf), IV_FAIL);
1344 ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf;
1345
1346 size = sizeof(sei);
1347 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1348 RETURN_IF((NULL == pv_buf), IV_FAIL);
1349 ps_dec->ps_sei = (sei *)pv_buf;
1350
1351 size = sizeof(dpb_commands_t);
1352 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1353 RETURN_IF((NULL == pv_buf), IV_FAIL);
1354 ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf;
1355
1356 size = sizeof(dec_bit_stream_t);
1357 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1358 RETURN_IF((NULL == pv_buf), IV_FAIL);
1359 ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf;
1360
1361 size = sizeof(dec_slice_params_t);
1362 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1363 RETURN_IF((NULL == pv_buf), IV_FAIL);
1364 ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf;
1365
1366 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1367 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1368 RETURN_IF((NULL == pv_buf), IV_FAIL);
1369 ps_dec->pv_scratch_sps_pps = pv_buf;
1370
1371
1372 ps_dec->u4_static_bits_buf_size = 256000;
1373 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size);
1374 RETURN_IF((NULL == pv_buf), IV_FAIL);
1375 ps_dec->pu1_bits_buf_static = pv_buf;
1376
1377
1378 size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC)
1379 * sizeof(void *));
1380 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1381 RETURN_IF((NULL == pv_buf), IV_FAIL);
1382 ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf;
1383 memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size);
1384
1385 ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC;
1386
1387
1388 size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
1389 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1390 RETURN_IF((NULL == pv_buf), IV_FAIL);
1391 ps_dec->p_cabac_ctxt_table_t = pv_buf;
1392
1393
1394
1395 size = sizeof(ctxt_inc_mb_info_t);
1396 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1397 RETURN_IF((NULL == pv_buf), IV_FAIL);
1398 ps_dec->ps_left_mb_ctxt_info = pv_buf;
1399
1400
1401
1402 size = MAX_REF_BUF_SIZE * 2;
1403 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1404 RETURN_IF((NULL == pv_buf), IV_FAIL);
1405 ps_dec->pu1_ref_buff_base = pv_buf;
1406 ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE;
1407
1408
1409 size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
1410 * PRED_BUFFER_HEIGHT * 2);
1411 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1412 RETURN_IF((NULL == pv_buf), IV_FAIL);
1413 ps_dec->pi2_pred1 = pv_buf;
1414
1415
1416 size = sizeof(UWORD8) * (MB_LUM_SIZE);
1417 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1418 RETURN_IF((NULL == pv_buf), IV_FAIL);
1419 ps_dec->pu1_temp_mc_buffer = pv_buf;
1420
1421
1422
1423
1424 size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
1425 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1426 RETURN_IF((NULL == pv_buf), IV_FAIL);
1427
1428 ps_dec->pu1_init_dpb_base = pv_buf;
1429 pu1_buf = pv_buf;
1430 ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf;
1431
1432 pu1_buf += size / 2;
1433 ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf;
1434
1435 size = (sizeof(UWORD32) * 2 * 3
1436 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2);
1437 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1438 RETURN_IF((NULL == pv_buf), IV_FAIL);
1439 ps_dec->pu4_mbaff_wt_mat = pv_buf;
1440
1441 size = sizeof(UWORD32) * 2 * 3
1442 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
1443 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1444 RETURN_IF((NULL == pv_buf), IV_FAIL);
1445 ps_dec->pu4_wts_ofsts_mat = pv_buf;
1446
1447
1448 size = (sizeof(neighbouradd_t) << 2);
1449 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1450 RETURN_IF((NULL == pv_buf), IV_FAIL);
1451 ps_dec->ps_left_mvpred_addr = pv_buf;
1452
1453
1454 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1455 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1456 RETURN_IF((NULL == pv_buf), IV_FAIL);
1457 ps_dec->pv_mv_buf_mgr = pv_buf;
1458
1459
1460 size = sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
1461 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1462 RETURN_IF((NULL == pv_buf), IV_FAIL);
1463 ps_dec->ps_col_mv_base = pv_buf;
1464 memset(ps_dec->ps_col_mv_base, 0, size);
1465
1466 ih264d_init_decoder(ps_dec);
1467
1468 return IV_SUCCESS;
1469 }
1470
1471
1472 /*****************************************************************************/
1473 /* */
1474 /* Function Name : ih264d_create */
1475 /* */
1476 /* Description : creates decoder */
1477 /* */
1478 /* Inputs :iv_obj_t decoder handle */
1479 /* :pv_api_ip pointer to input structure */
1480 /* :pv_api_op pointer to output structure */
1481 /* Outputs : */
1482 /* Returns : void */
1483 /* */
1484 /* Issues : none */
1485 /* */
1486 /* Revision History: */
1487 /* */
1488 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1489 /* 22 10 2008 100356 Draft */
1490 /* */
1491 /*****************************************************************************/
ih264d_create(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1492 WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1493 {
1494 ih264d_create_ip_t *ps_create_ip;
1495 ih264d_create_op_t *ps_create_op;
1496
1497 WORD32 ret;
1498
1499 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1500 ps_create_op = (ih264d_create_op_t *)pv_api_op;
1501
1502 ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1503 dec_hdl = NULL;
1504 ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op);
1505
1506 /* If allocation of some buffer fails, then free buffers allocated till then */
1507 if(IV_FAIL == ret)
1508 {
1509 if(dec_hdl)
1510 {
1511 if(dec_hdl->pv_codec_handle)
1512 {
1513 ih264d_free_static_bufs(dec_hdl);
1514 }
1515 else
1516 {
1517 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1518 void *pv_mem_ctxt;
1519
1520 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1521 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1522 pf_aligned_free(pv_mem_ctxt, dec_hdl);
1523 }
1524 }
1525 ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED;
1526 ps_create_op->s_ivd_create_op_t.u4_error_code = 1 << IVD_FATALERROR;
1527
1528 return IV_FAIL;
1529 }
1530
1531 return IV_SUCCESS;
1532 }
1533
1534 /*****************************************************************************/
1535 /* */
1536 /* Function Name : ih264d_map_error */
1537 /* */
1538 /* Description : Maps error codes to IVD error groups */
1539 /* */
1540 /* Inputs : */
1541 /* Globals : <Does it use any global variables?> */
1542 /* Outputs : */
1543 /* Returns : void */
1544 /* */
1545 /* Issues : none */
1546 /* */
1547 /* Revision History: */
1548 /* */
1549 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1550 /* 22 10 2008 100356 Draft */
1551 /* */
1552 /*****************************************************************************/
ih264d_map_error(UWORD32 i4_err_status)1553 UWORD32 ih264d_map_error(UWORD32 i4_err_status)
1554 {
1555 UWORD32 temp = 0;
1556
1557 switch(i4_err_status)
1558 {
1559 case ERROR_MEM_ALLOC_ISRAM_T:
1560 case ERROR_MEM_ALLOC_SDRAM_T:
1561 case ERROR_BUF_MGR:
1562 case ERROR_MB_GROUP_ASSGN_T:
1563 case ERROR_FRAME_LIMIT_OVER:
1564 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
1565 case ERROR_PROFILE_NOT_SUPPORTED:
1566 case ERROR_INIT_NOT_DONE:
1567 case IVD_MEM_ALLOC_FAILED:
1568 temp = 1 << IVD_FATALERROR;
1569 H264_DEC_DEBUG_PRINT("\nFatal Error\n");
1570 break;
1571
1572 case ERROR_DBP_MANAGER_T:
1573 case ERROR_GAPS_IN_FRM_NUM:
1574 case ERROR_UNKNOWN_NAL:
1575 case ERROR_INV_MB_SLC_GRP_T:
1576 case ERROR_MULTIPLE_SLC_GRP_T:
1577 case ERROR_UNKNOWN_LEVEL:
1578 case ERROR_UNAVAIL_PICBUF_T:
1579 case ERROR_UNAVAIL_MVBUF_T:
1580 case ERROR_UNAVAIL_DISPBUF_T:
1581 case ERROR_NUM_REF:
1582 case ERROR_REFIDX_ORDER_T:
1583 case ERROR_PIC0_NOT_FOUND_T:
1584 case ERROR_MB_TYPE:
1585 case ERROR_SUB_MB_TYPE:
1586 case ERROR_CBP:
1587 case ERROR_REF_IDX:
1588 case ERROR_NUM_MV:
1589 case ERROR_CHROMA_PRED_MODE:
1590 case ERROR_INTRAPRED:
1591 case ERROR_NEXT_MB_ADDRESS_T:
1592 case ERROR_MB_ADDRESS_T:
1593 case ERROR_PIC1_NOT_FOUND_T:
1594 case ERROR_CAVLC_NUM_COEFF_T:
1595 case ERROR_CAVLC_SCAN_POS_T:
1596 case ERROR_PRED_WEIGHT_TABLE_T:
1597 case ERROR_CORRUPTED_SLICE:
1598 temp = 1 << IVD_CORRUPTEDDATA;
1599 break;
1600
1601 case ERROR_NOT_SUPP_RESOLUTION:
1602 case ERROR_FEATURE_UNAVAIL:
1603 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
1604 temp = 1 << IVD_UNSUPPORTEDINPUT;
1605 break;
1606
1607 case ERROR_INVALID_PIC_PARAM:
1608 case ERROR_INVALID_SEQ_PARAM:
1609 case ERROR_EGC_EXCEED_32_1_T:
1610 case ERROR_EGC_EXCEED_32_2_T:
1611 case ERROR_INV_RANGE_TEV_T:
1612 case ERROR_INV_SLC_TYPE_T:
1613 case ERROR_INV_POC_TYPE_T:
1614 case ERROR_INV_RANGE_QP_T:
1615 case ERROR_INV_SPS_PPS_T:
1616 case ERROR_INV_SLICE_HDR_T:
1617 temp = 1 << IVD_CORRUPTEDHEADER;
1618 break;
1619
1620 case ERROR_EOB_FLUSHBITS_T:
1621 case ERROR_EOB_GETBITS_T:
1622 case ERROR_EOB_GETBIT_T:
1623 case ERROR_EOB_BYPASS_T:
1624 case ERROR_EOB_DECISION_T:
1625 case ERROR_EOB_TERMINATE_T:
1626 case ERROR_EOB_READCOEFF4X4CAB_T:
1627 temp = 1 << IVD_INSUFFICIENTDATA;
1628 break;
1629 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
1630 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
1631 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
1632 break;
1633
1634 case ERROR_DANGLING_FIELD_IN_PIC:
1635 temp = 1 << IVD_APPLIEDCONCEALMENT;
1636 break;
1637
1638 }
1639
1640 return temp;
1641
1642 }
1643
ih264d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht,UWORD8 u1_chroma_format,UWORD32 * p_buf_size)1644 UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd,
1645 UWORD32 pic_ht,
1646 UWORD8 u1_chroma_format,
1647 UWORD32 *p_buf_size)
1648 {
1649 UWORD32 u4_min_num_out_bufs = 0;
1650
1651 if(u1_chroma_format == IV_YUV_420P)
1652 u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1653 else if(u1_chroma_format == IV_YUV_422ILE)
1654 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1655 else if(u1_chroma_format == IV_RGB_565)
1656 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1657 else if((u1_chroma_format == IV_YUV_420SP_UV)
1658 || (u1_chroma_format == IV_YUV_420SP_VU))
1659 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
1660
1661 if(u1_chroma_format == IV_YUV_420P)
1662 {
1663 p_buf_size[0] = (pic_wd * pic_ht);
1664 p_buf_size[1] = (pic_wd * pic_ht) >> 2;
1665 p_buf_size[2] = (pic_wd * pic_ht) >> 2;
1666 }
1667 else if(u1_chroma_format == IV_YUV_422ILE)
1668 {
1669 p_buf_size[0] = (pic_wd * pic_ht) * 2;
1670 p_buf_size[1] = p_buf_size[2] = 0;
1671 }
1672 else if(u1_chroma_format == IV_RGB_565)
1673 {
1674 p_buf_size[0] = (pic_wd * pic_ht) * 2;
1675 p_buf_size[1] = p_buf_size[2] = 0;
1676 }
1677 else if((u1_chroma_format == IV_YUV_420SP_UV)
1678 || (u1_chroma_format == IV_YUV_420SP_VU))
1679 {
1680 p_buf_size[0] = (pic_wd * pic_ht);
1681 p_buf_size[1] = (pic_wd * pic_ht) >> 1;
1682 p_buf_size[2] = 0;
1683 }
1684
1685 return u4_min_num_out_bufs;
1686 }
1687
check_app_out_buf_size(dec_struct_t * ps_dec)1688 WORD32 check_app_out_buf_size(dec_struct_t *ps_dec)
1689 {
1690 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
1691 UWORD32 u4_min_num_out_bufs, i;
1692 UWORD32 pic_wd, pic_ht;
1693
1694 if(0 == ps_dec->u4_share_disp_buf)
1695 {
1696 pic_wd = ps_dec->u2_disp_width;
1697 pic_ht = ps_dec->u2_disp_height;
1698
1699 }
1700 else
1701 {
1702 pic_wd = ps_dec->u2_frm_wd_y;
1703 pic_ht = ps_dec->u2_frm_ht_y;
1704 }
1705
1706 if(ps_dec->u4_app_disp_width > pic_wd)
1707 pic_wd = ps_dec->u4_app_disp_width;
1708
1709 u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht,
1710 ps_dec->u1_chroma_format,
1711 &au4_min_out_buf_size[0]);
1712
1713
1714 if(0 == ps_dec->u4_share_disp_buf)
1715 {
1716 if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs)
1717 return IV_FAIL;
1718
1719 for(i = 0; i < u4_min_num_out_bufs; i++)
1720 {
1721 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i]
1722 < au4_min_out_buf_size[i])
1723 return (IV_FAIL);
1724 }
1725 }
1726 else
1727 {
1728 if(ps_dec->disp_bufs[0].u4_num_bufs < u4_min_num_out_bufs)
1729 return IV_FAIL;
1730
1731 for(i = 0; i < u4_min_num_out_bufs; i++)
1732 {
1733 /* We need to check only with the disp_buffer[0], because we have
1734 * already ensured that all the buffers are of the same size in
1735 * ih264d_set_display_frame.
1736 */
1737 if(ps_dec->disp_bufs[0].u4_bufsize[i] < au4_min_out_buf_size[i])
1738 return (IV_FAIL);
1739 }
1740
1741 }
1742
1743 return (IV_SUCCESS);
1744 }
1745
1746
1747 /*****************************************************************************/
1748 /* */
1749 /* Function Name : ih264d_video_decode */
1750 /* */
1751 /* Description : handle video decode API command */
1752 /* */
1753 /* Inputs :iv_obj_t decoder handle */
1754 /* :pv_api_ip pointer to input structure */
1755 /* :pv_api_op pointer to output structure */
1756 /* Outputs : */
1757 /* Returns : void */
1758 /* */
1759 /* Issues : none */
1760 /* */
1761 /* Revision History: */
1762 /* */
1763 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1764 /* 22 10 2008 100356 Draft */
1765 /* */
1766 /*****************************************************************************/
1767
ih264d_video_decode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1768 WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1769 {
1770 /* ! */
1771
1772 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
1773
1774 WORD32 i4_err_status = 0;
1775 UWORD8 *pu1_buf = NULL;
1776 WORD32 buflen;
1777 UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
1778
1779 UWORD32 bytes_consumed = 0;
1780 UWORD32 cur_slice_is_nonref = 0;
1781 UWORD32 u4_next_is_aud;
1782 UWORD32 u4_first_start_code_found = 0;
1783 WORD32 ret = 0,api_ret_value = IV_SUCCESS;
1784 WORD32 header_data_left = 0,frame_data_left = 0;
1785 UWORD8 *pu1_bitstrm_buf;
1786 ivd_video_decode_ip_t *ps_dec_ip;
1787 ivd_video_decode_op_t *ps_dec_op;
1788
1789 ithread_set_name((void*)"Parse_thread");
1790
1791 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip;
1792 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op;
1793
1794 {
1795 UWORD32 u4_size;
1796 u4_size = ps_dec_op->u4_size;
1797 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t));
1798 ps_dec_op->u4_size = u4_size;
1799 }
1800
1801 ps_dec->pv_dec_out = ps_dec_op;
1802 if(ps_dec->init_done != 1)
1803 {
1804 return IV_FAIL;
1805 }
1806
1807 /*Data memory barries instruction,so that bitstream write by the application is complete*/
1808 DATA_SYNC();
1809
1810 if(0 == ps_dec->u1_flushfrm)
1811 {
1812 if(ps_dec_ip->pv_stream_buffer == NULL)
1813 {
1814 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1815 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
1816 return IV_FAIL;
1817 }
1818 if(ps_dec_ip->u4_num_Bytes <= 0)
1819 {
1820 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1821 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
1822 return IV_FAIL;
1823
1824 }
1825 }
1826 ps_dec->u1_pic_decode_done = 0;
1827
1828 ps_dec_op->u4_num_bytes_consumed = 0;
1829
1830 ps_dec->ps_out_buffer = NULL;
1831
1832 if(ps_dec_ip->u4_size
1833 >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
1834 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
1835
1836 ps_dec->u4_fmt_conv_cur_row = 0;
1837
1838 ps_dec->u4_output_present = 0;
1839 ps_dec->s_disp_op.u4_error_code = 1;
1840 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
1841 if(0 == ps_dec->u4_share_disp_buf
1842 && ps_dec->i4_decode_header == 0)
1843 {
1844 UWORD32 i;
1845 if((ps_dec->ps_out_buffer->u4_num_bufs == 0) ||
1846 (ps_dec->ps_out_buffer->u4_num_bufs > IVD_VIDDEC_MAX_IO_BUFFERS))
1847 {
1848 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1849 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
1850 return IV_FAIL;
1851 }
1852
1853 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
1854 {
1855 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
1856 {
1857 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1858 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
1859 return IV_FAIL;
1860 }
1861
1862 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
1863 {
1864 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1865 ps_dec_op->u4_error_code |=
1866 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
1867 return IV_FAIL;
1868 }
1869 }
1870 }
1871
1872 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
1873 {
1874 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
1875 return IV_FAIL;
1876 }
1877
1878 /* ! */
1879 ps_dec->u4_ts = ps_dec_ip->u4_ts;
1880
1881 ps_dec_op->u4_error_code = 0;
1882 ps_dec_op->e_pic_type = -1;
1883 ps_dec_op->u4_output_present = 0;
1884 ps_dec_op->u4_frame_decoded_flag = 0;
1885
1886 ps_dec->i4_frametype = -1;
1887 ps_dec->i4_content_type = -1;
1888
1889 ps_dec->u4_slice_start_code_found = 0;
1890
1891 /* In case the deocder is not in flush mode(in shared mode),
1892 then decoder has to pick up a buffer to write current frame.
1893 Check if a frame is available in such cases */
1894
1895 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
1896 && ps_dec->u1_flushfrm == 0)
1897 {
1898 UWORD32 i;
1899
1900 WORD32 disp_avail = 0, free_id;
1901
1902 /* Check if at least one buffer is available with the codec */
1903 /* If not then return to application with error */
1904 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
1905 {
1906 if(0 == ps_dec->u4_disp_buf_mapping[i]
1907 || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
1908 {
1909 disp_avail = 1;
1910 break;
1911 }
1912
1913 }
1914
1915 if(0 == disp_avail)
1916 {
1917 /* If something is queued for display wait for that buffer to be returned */
1918
1919 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
1920 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
1921 return (IV_FAIL);
1922 }
1923
1924 while(1)
1925 {
1926 pic_buffer_t *ps_pic_buf;
1927 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
1928 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
1929
1930 if(ps_pic_buf == NULL)
1931 {
1932 UWORD32 i, display_queued = 0;
1933
1934 /* check if any buffer was given for display which is not returned yet */
1935 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
1936 {
1937 if(0 != ps_dec->u4_disp_buf_mapping[i])
1938 {
1939 display_queued = 1;
1940 break;
1941 }
1942 }
1943 /* If some buffer is queued for display, then codec has to singal an error and wait
1944 for that buffer to be returned.
1945 If nothing is queued for display then codec has ownership of all display buffers
1946 and it can reuse any of the existing buffers and continue decoding */
1947
1948 if(1 == display_queued)
1949 {
1950 /* If something is queued for display wait for that buffer to be returned */
1951 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
1952 ps_dec_op->u4_error_code |= (1
1953 << IVD_UNSUPPORTEDPARAM);
1954 return (IV_FAIL);
1955 }
1956 }
1957 else
1958 {
1959 /* If the buffer is with display, then mark it as in use and then look for a buffer again */
1960 if(1 == ps_dec->u4_disp_buf_mapping[free_id])
1961 {
1962 ih264_buf_mgr_set_status(
1963 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1964 free_id,
1965 BUF_MGR_IO);
1966 }
1967 else
1968 {
1969 /**
1970 * Found a free buffer for present call. Release it now.
1971 * Will be again obtained later.
1972 */
1973 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1974 free_id,
1975 BUF_MGR_IO);
1976 break;
1977 }
1978 }
1979 }
1980
1981 }
1982
1983 if(ps_dec->u1_flushfrm)
1984 {
1985 if(ps_dec->u1_init_dec_flag == 0)
1986 {
1987 /*Come out of flush mode and return*/
1988 ps_dec->u1_flushfrm = 0;
1989 return (IV_FAIL);
1990 }
1991
1992
1993
1994 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
1995 &(ps_dec->s_disp_op));
1996 if(0 == ps_dec->s_disp_op.u4_error_code)
1997 {
1998 /* check output buffer size given by the application */
1999 if(check_app_out_buf_size(ps_dec) != IV_SUCCESS)
2000 {
2001 ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2002 return (IV_FAIL);
2003 }
2004
2005 ps_dec->u4_fmt_conv_cur_row = 0;
2006 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2007 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2008 ps_dec->u4_fmt_conv_cur_row,
2009 ps_dec->u4_fmt_conv_num_rows);
2010 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2011 ps_dec->u4_output_present = 1;
2012
2013 }
2014 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2015
2016 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2017 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2018
2019 ps_dec_op->u4_new_seq = 0;
2020
2021 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2022 ps_dec_op->u4_progressive_frame_flag =
2023 ps_dec->s_disp_op.u4_progressive_frame_flag;
2024 ps_dec_op->e_output_format =
2025 ps_dec->s_disp_op.e_output_format;
2026 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2027 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2028 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2029 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2030
2031 /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2032 ps_dec_op->u4_is_ref_flag = -1;
2033 ps_dec_op->e_pic_type = IV_NA_FRAME;
2034 ps_dec_op->u4_frame_decoded_flag = 0;
2035
2036 if(0 == ps_dec->s_disp_op.u4_error_code)
2037 {
2038 return (IV_SUCCESS);
2039 }
2040 else
2041 return (IV_FAIL);
2042
2043 }
2044 if(ps_dec->u1_res_changed == 1)
2045 {
2046 /*if resolution has changed and all buffers have been flushed, reset decoder*/
2047 ih264d_init_decoder(ps_dec);
2048 }
2049
2050 ps_dec->u4_prev_nal_skipped = 0;
2051
2052 ps_dec->u2_cur_mb_addr = 0;
2053 ps_dec->u2_total_mbs_coded = 0;
2054 ps_dec->u2_cur_slice_num = 0;
2055 ps_dec->cur_dec_mb_num = 0;
2056 ps_dec->cur_recon_mb_num = 0;
2057 ps_dec->u4_first_slice_in_pic = 1;
2058 ps_dec->u1_slice_header_done = 0;
2059 ps_dec->u1_dangling_field = 0;
2060
2061 ps_dec->u4_dec_thread_created = 0;
2062 ps_dec->u4_bs_deblk_thread_created = 0;
2063 ps_dec->u4_cur_bs_mb_num = 0;
2064 ps_dec->u4_start_recon_deblk = 0;
2065 ps_dec->u4_sps_cnt_in_process = 0;
2066
2067 DEBUG_THREADS_PRINTF(" Starting process call\n");
2068
2069
2070 ps_dec->u4_pic_buf_got = 0;
2071
2072 do
2073 {
2074 WORD32 buf_size;
2075
2076 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2077 + ps_dec_op->u4_num_bytes_consumed;
2078
2079 u4_max_ofst = ps_dec_ip->u4_num_Bytes
2080 - ps_dec_op->u4_num_bytes_consumed;
2081
2082 /* If dynamic bitstream buffer is not allocated and
2083 * header decode is done, then allocate dynamic bitstream buffer
2084 */
2085 if((NULL == ps_dec->pu1_bits_buf_dynamic) &&
2086 (ps_dec->i4_header_decoded & 1))
2087 {
2088 WORD32 size;
2089
2090 void *pv_buf;
2091 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
2092 size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2);
2093 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128,
2094 size + EXTRA_BS_OFFSET);
2095 RETURN_IF((NULL == pv_buf), IV_FAIL);
2096 ps_dec->pu1_bits_buf_dynamic = pv_buf;
2097 ps_dec->u4_dynamic_bits_buf_size = size;
2098 }
2099
2100 if(ps_dec->pu1_bits_buf_dynamic)
2101 {
2102 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic;
2103 buf_size = ps_dec->u4_dynamic_bits_buf_size;
2104 }
2105 else
2106 {
2107 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static;
2108 buf_size = ps_dec->u4_static_bits_buf_size;
2109 }
2110
2111 u4_next_is_aud = 0;
2112
2113 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2114 &u4_length_of_start_code,
2115 &u4_next_is_aud);
2116
2117 if(buflen == -1)
2118 buflen = 0;
2119 /* Ignore bytes beyond the allocated size of intermediate buffer */
2120 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the
2121 end of the buffer, which will be memset to 0 after emulation prevention */
2122 buflen = MIN(buflen, buf_size - 8);
2123
2124 bytes_consumed = buflen + u4_length_of_start_code;
2125 ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2126
2127 {
2128 UWORD8 u1_firstbyte, u1_nal_ref_idc;
2129
2130 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B)
2131 {
2132 u1_firstbyte = *(pu1_buf + u4_length_of_start_code);
2133 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte));
2134 if(u1_nal_ref_idc == 0)
2135 {
2136 /*skip non reference frames*/
2137 cur_slice_is_nonref = 1;
2138 continue;
2139 }
2140 else
2141 {
2142 if(1 == cur_slice_is_nonref)
2143 {
2144 /*We have encountered a referenced frame,return to app*/
2145 ps_dec_op->u4_num_bytes_consumed -=
2146 bytes_consumed;
2147 ps_dec_op->e_pic_type = IV_B_FRAME;
2148 ps_dec_op->u4_error_code =
2149 IVD_DEC_FRM_SKIPPED;
2150 ps_dec_op->u4_error_code |= (1
2151 << IVD_UNSUPPORTEDPARAM);
2152 ps_dec_op->u4_frame_decoded_flag = 0;
2153 ps_dec_op->u4_size =
2154 sizeof(ivd_video_decode_op_t);
2155 /*signal the decode thread*/
2156 ih264d_signal_decode_thread(ps_dec);
2157 /* close deblock thread if it is not closed yet*/
2158 if(ps_dec->u4_num_cores == 3)
2159 {
2160 ih264d_signal_bs_deblk_thread(ps_dec);
2161 }
2162
2163 return (IV_FAIL);
2164 }
2165 }
2166
2167 }
2168
2169 }
2170
2171
2172 if(buflen)
2173 {
2174 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
2175 buflen);
2176 /* Decoder may read extra 8 bytes near end of the frame */
2177 if((buflen + 8) < buf_size)
2178 {
2179 memset(pu1_bitstrm_buf + buflen, 0, 8);
2180 }
2181 u4_first_start_code_found = 1;
2182
2183 }
2184 else
2185 {
2186 /*start code not found*/
2187
2188 if(u4_first_start_code_found == 0)
2189 {
2190 /*no start codes found in current process call*/
2191
2192 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
2193 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
2194
2195 if(ps_dec->u4_pic_buf_got == 0)
2196 {
2197
2198 ih264d_fill_output_struct_from_context(ps_dec,
2199 ps_dec_op);
2200
2201 ps_dec_op->u4_error_code = ps_dec->i4_error_code;
2202 ps_dec_op->u4_frame_decoded_flag = 0;
2203
2204 return (IV_FAIL);
2205 }
2206 else
2207 {
2208 ps_dec->u1_pic_decode_done = 1;
2209 continue;
2210 }
2211 }
2212 else
2213 {
2214 /* a start code has already been found earlier in the same process call*/
2215 frame_data_left = 0;
2216 header_data_left = 0;
2217 continue;
2218 }
2219
2220 }
2221
2222 ps_dec->u4_return_to_app = 0;
2223 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
2224 pu1_bitstrm_buf, buflen);
2225 if(ret != OK)
2226 {
2227 UWORD32 error = ih264d_map_error(ret);
2228 ps_dec_op->u4_error_code = error | ret;
2229 api_ret_value = IV_FAIL;
2230
2231 if((ret == IVD_RES_CHANGED)
2232 || (ret == IVD_MEM_ALLOC_FAILED)
2233 || (ret == ERROR_UNAVAIL_PICBUF_T)
2234 || (ret == ERROR_UNAVAIL_MVBUF_T)
2235 || (ret == ERROR_INV_SPS_PPS_T)
2236 || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE))
2237 {
2238 ps_dec->u4_slice_start_code_found = 0;
2239 break;
2240 }
2241
2242 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
2243 {
2244 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2245 api_ret_value = IV_FAIL;
2246 break;
2247 }
2248
2249 if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
2250 {
2251 api_ret_value = IV_FAIL;
2252 break;
2253 }
2254
2255 }
2256
2257 if(ps_dec->u4_return_to_app)
2258 {
2259 /*We have encountered a referenced frame,return to app*/
2260 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2261 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED;
2262 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2263 ps_dec_op->u4_frame_decoded_flag = 0;
2264 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t);
2265 /*signal the decode thread*/
2266 ih264d_signal_decode_thread(ps_dec);
2267 /* close deblock thread if it is not closed yet*/
2268 if(ps_dec->u4_num_cores == 3)
2269 {
2270 ih264d_signal_bs_deblk_thread(ps_dec);
2271 }
2272 return (IV_FAIL);
2273
2274 }
2275
2276
2277
2278 header_data_left = ((ps_dec->i4_decode_header == 1)
2279 && (ps_dec->i4_header_decoded != 3)
2280 && (ps_dec_op->u4_num_bytes_consumed
2281 < ps_dec_ip->u4_num_Bytes));
2282 frame_data_left = (((ps_dec->i4_decode_header == 0)
2283 && ((ps_dec->u1_pic_decode_done == 0)
2284 || (u4_next_is_aud == 1)))
2285 && (ps_dec_op->u4_num_bytes_consumed
2286 < ps_dec_ip->u4_num_Bytes));
2287 }
2288 while(( header_data_left == 1)||(frame_data_left == 1));
2289
2290 if((ps_dec->u4_pic_buf_got == 1)
2291 && (ret != IVD_MEM_ALLOC_FAILED)
2292 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2293 {
2294 // last slice - missing/corruption
2295 WORD32 num_mb_skipped;
2296 WORD32 prev_slice_err;
2297 pocstruct_t temp_poc;
2298 WORD32 ret1;
2299 WORD32 ht_in_mbs;
2300 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag);
2301 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2302 - ps_dec->u2_total_mbs_coded;
2303
2304 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0))
2305 prev_slice_err = 1;
2306 else
2307 prev_slice_err = 2;
2308
2309 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0))
2310 prev_slice_err = 1;
2311
2312 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
2313 &temp_poc, prev_slice_err);
2314
2315 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) ||
2316 (ret1 == ERROR_INV_SPS_PPS_T))
2317 {
2318 ret = ret1;
2319 }
2320 }
2321
2322 if((ret == IVD_RES_CHANGED)
2323 || (ret == IVD_MEM_ALLOC_FAILED)
2324 || (ret == ERROR_UNAVAIL_PICBUF_T)
2325 || (ret == ERROR_UNAVAIL_MVBUF_T)
2326 || (ret == ERROR_INV_SPS_PPS_T))
2327 {
2328
2329 /* signal the decode thread */
2330 ih264d_signal_decode_thread(ps_dec);
2331 /* close deblock thread if it is not closed yet */
2332 if(ps_dec->u4_num_cores == 3)
2333 {
2334 ih264d_signal_bs_deblk_thread(ps_dec);
2335 }
2336 /* dont consume bitstream for change in resolution case */
2337 if(ret == IVD_RES_CHANGED)
2338 {
2339 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2340 }
2341 return IV_FAIL;
2342 }
2343
2344
2345 if(ps_dec->u1_separate_parse)
2346 {
2347 /* If Format conversion is not complete,
2348 complete it here */
2349 if(ps_dec->u4_num_cores == 2)
2350 {
2351
2352 /*do deblocking of all mbs*/
2353 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
2354 {
2355 UWORD32 u4_num_mbs,u4_max_addr;
2356 tfr_ctxt_t s_tfr_ctxt;
2357 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
2358 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
2359
2360 /*BS is done for all mbs while parsing*/
2361 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
2362 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
2363
2364
2365 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
2366 ps_dec->u2_frm_wd_in_mbs, 0);
2367
2368
2369 u4_num_mbs = u4_max_addr
2370 - ps_dec->u4_cur_deblk_mb_num + 1;
2371
2372 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
2373
2374 if(u4_num_mbs != 0)
2375 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
2376 ps_tfr_cxt,1);
2377
2378 ps_dec->u4_start_recon_deblk = 0;
2379
2380 }
2381
2382 }
2383
2384 /*signal the decode thread*/
2385 ih264d_signal_decode_thread(ps_dec);
2386 /* close deblock thread if it is not closed yet*/
2387 if(ps_dec->u4_num_cores == 3)
2388 {
2389 ih264d_signal_bs_deblk_thread(ps_dec);
2390 }
2391 }
2392
2393
2394 DATA_SYNC();
2395
2396
2397 if((ps_dec_op->u4_error_code & 0xff)
2398 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
2399 {
2400 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2401 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2402 }
2403
2404 //Report if header (sps and pps) has not been decoded yet
2405 if(ps_dec->i4_header_decoded != 3)
2406 {
2407 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
2408
2409 }
2410
2411 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
2412 {
2413 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
2414
2415 }
2416 if(ps_dec->u4_prev_nal_skipped)
2417 {
2418 /*We have encountered a referenced frame,return to app*/
2419 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED;
2420 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2421 ps_dec_op->u4_frame_decoded_flag = 0;
2422 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t);
2423 /* close deblock thread if it is not closed yet*/
2424 if(ps_dec->u4_num_cores == 3)
2425 {
2426 ih264d_signal_bs_deblk_thread(ps_dec);
2427 }
2428 return (IV_FAIL);
2429
2430 }
2431
2432 if((ps_dec->u4_pic_buf_got == 1)
2433 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
2434 {
2435 /*
2436 * For field pictures, set the bottom and top picture decoded u4_flag correctly.
2437 */
2438
2439 if(ps_dec->ps_cur_slice->u1_field_pic_flag)
2440 {
2441 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
2442 {
2443 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
2444 }
2445 else
2446 {
2447 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
2448 }
2449 }
2450 else
2451 {
2452 ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
2453 }
2454
2455 /* if new frame in not found (if we are still getting slices from previous frame)
2456 * ih264d_deblock_display is not called. Such frames will not be added to reference /display
2457 */
2458 if ((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
2459 {
2460 /* Calling Function to deblock Picture and Display */
2461 ret = ih264d_deblock_display(ps_dec);
2462 }
2463
2464
2465 /*set to complete ,as we dont support partial frame decode*/
2466 if(ps_dec->i4_header_decoded == 3)
2467 {
2468 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
2469 }
2470
2471 /*Update the i4_frametype at the end of picture*/
2472 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
2473 {
2474 ps_dec->i4_frametype = IV_IDR_FRAME;
2475 }
2476 else if(ps_dec->i4_pic_type == B_SLICE)
2477 {
2478 ps_dec->i4_frametype = IV_B_FRAME;
2479 }
2480 else if(ps_dec->i4_pic_type == P_SLICE)
2481 {
2482 ps_dec->i4_frametype = IV_P_FRAME;
2483 }
2484 else if(ps_dec->i4_pic_type == I_SLICE)
2485 {
2486 ps_dec->i4_frametype = IV_I_FRAME;
2487 }
2488 else
2489 {
2490 H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
2491 }
2492
2493 //Update the content type
2494 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
2495
2496 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
2497 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
2498 - ps_dec->ps_cur_slice->u1_field_pic_flag;
2499
2500 }
2501
2502 /* close deblock thread if it is not closed yet*/
2503 if(ps_dec->u4_num_cores == 3)
2504 {
2505 ih264d_signal_bs_deblk_thread(ps_dec);
2506 }
2507
2508
2509 {
2510 /* In case the decoder is configured to run in low delay mode,
2511 * then get display buffer and then format convert.
2512 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
2513 */
2514
2515 if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
2516 && ps_dec->u1_init_dec_flag)
2517 {
2518
2519 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2520 &(ps_dec->s_disp_op));
2521 if(0 == ps_dec->s_disp_op.u4_error_code)
2522 {
2523 ps_dec->u4_fmt_conv_cur_row = 0;
2524 ps_dec->u4_output_present = 1;
2525 }
2526 }
2527
2528 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
2529
2530 /* If Format conversion is not complete,
2531 complete it here */
2532 if(ps_dec->u4_output_present &&
2533 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
2534 {
2535 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
2536 - ps_dec->u4_fmt_conv_cur_row;
2537 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2538 ps_dec->u4_fmt_conv_cur_row,
2539 ps_dec->u4_fmt_conv_num_rows);
2540 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2541 }
2542
2543 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2544 }
2545
2546 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
2547 {
2548 ps_dec_op->u4_progressive_frame_flag = 1;
2549 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2550 {
2551 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
2552 && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
2553 ps_dec_op->u4_progressive_frame_flag = 0;
2554
2555 }
2556 }
2557
2558 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
2559 {
2560 ps_dec->u1_top_bottom_decoded = 0;
2561 }
2562 /*--------------------------------------------------------------------*/
2563 /* Do End of Pic processing. */
2564 /* Should be called only if frame was decoded in previous process call*/
2565 /*--------------------------------------------------------------------*/
2566 if(ps_dec->u4_pic_buf_got == 1)
2567 {
2568 if(1 == ps_dec->u1_last_pic_not_decoded)
2569 {
2570 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec);
2571
2572 if(ret != OK)
2573 return ret;
2574
2575 ret = ih264d_end_of_pic(ps_dec);
2576 if(ret != OK)
2577 return ret;
2578 }
2579 else
2580 {
2581 ret = ih264d_end_of_pic(ps_dec);
2582 if(ret != OK)
2583 return ret;
2584 }
2585
2586 }
2587
2588
2589 /*Data memory barrier instruction,so that yuv write by the library is complete*/
2590 DATA_SYNC();
2591
2592 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
2593 ps_dec_op->u4_num_bytes_consumed);
2594 return api_ret_value;
2595 }
2596
ih264d_get_version(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2597 WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2598 {
2599 char version_string[MAXVERSION_STRLEN + 1];
2600 UWORD32 version_string_len;
2601
2602 ivd_ctl_getversioninfo_ip_t *ps_ip;
2603 ivd_ctl_getversioninfo_op_t *ps_op;
2604
2605 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
2606 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
2607 UNUSED(dec_hdl);
2608 ps_op->u4_error_code = IV_SUCCESS;
2609
2610 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
2611 CODEC_VENDOR);
2612
2613 if((WORD32)ps_ip->u4_version_buffer_size <= 0)
2614 {
2615 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2616 return (IV_FAIL);
2617 }
2618
2619 version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1;
2620
2621 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
2622 {
2623 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
2624 ps_op->u4_error_code = IV_SUCCESS;
2625 }
2626 else
2627 {
2628 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2629 return IV_FAIL;
2630 }
2631 return (IV_SUCCESS);
2632 }
2633
2634 /*****************************************************************************/
2635 /* */
2636 /* Function Name : ih264d_get_display_frame */
2637 /* */
2638 /* Description : */
2639 /* Inputs :iv_obj_t decoder handle */
2640 /* :pv_api_ip pointer to input structure */
2641 /* :pv_api_op pointer to output structure */
2642 /* Outputs : */
2643 /* Returns : void */
2644 /* */
2645 /* Issues : none */
2646 /* */
2647 /* Revision History: */
2648 /* */
2649 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2650 /* 22 10 2008 100356 Draft */
2651 /* */
2652 /*****************************************************************************/
ih264d_get_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2653 WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
2654 void *pv_api_ip,
2655 void *pv_api_op)
2656 {
2657
2658 UNUSED(dec_hdl);
2659 UNUSED(pv_api_ip);
2660 UNUSED(pv_api_op);
2661 // This function is no longer needed, output is returned in the process()
2662 return IV_FAIL;
2663 }
2664
2665 /*****************************************************************************/
2666 /* */
2667 /* Function Name : ih264d_set_display_frame */
2668 /* */
2669 /* Description : */
2670 /* */
2671 /* Inputs :iv_obj_t decoder handle */
2672 /* :pv_api_ip pointer to input structure */
2673 /* :pv_api_op pointer to output structure */
2674 /* Outputs : */
2675 /* Returns : void */
2676 /* */
2677 /* Issues : none */
2678 /* */
2679 /* Revision History: */
2680 /* */
2681 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2682 /* 22 10 2008 100356 Draft */
2683 /* */
2684 /*****************************************************************************/
ih264d_set_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2685 WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
2686 void *pv_api_ip,
2687 void *pv_api_op)
2688 {
2689
2690 UWORD32 u4_disp_buf_size[3], u4_num_disp_bufs;
2691 ivd_set_display_frame_ip_t *dec_disp_ip;
2692 ivd_set_display_frame_op_t *dec_disp_op;
2693
2694 UWORD32 i;
2695 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2696
2697 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
2698 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
2699 dec_disp_op->u4_error_code = 0;
2700
2701
2702 ps_dec->u4_num_disp_bufs = 0;
2703 if(ps_dec->u4_share_disp_buf)
2704 {
2705 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
2706
2707 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
2708
2709 ps_dec->u4_num_disp_bufs = u4_num_bufs;
2710
2711 /* Get the number and sizes of the first buffer. Compare this with the
2712 * rest to make sure all the buffers are of the same size.
2713 */
2714 u4_num_disp_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
2715
2716 u4_disp_buf_size[0] =
2717 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
2718 u4_disp_buf_size[1] =
2719 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
2720 u4_disp_buf_size[2] =
2721 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
2722
2723 for(i = 0; i < u4_num_bufs; i++)
2724 {
2725 if(dec_disp_ip->s_disp_buffer[i].u4_num_bufs != u4_num_disp_bufs)
2726 {
2727 return IV_FAIL;
2728 }
2729
2730 if((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
2731 != u4_disp_buf_size[0])
2732 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
2733 != u4_disp_buf_size[1])
2734 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
2735 != u4_disp_buf_size[2]))
2736 {
2737 return IV_FAIL;
2738 }
2739
2740 ps_dec->disp_bufs[i].u4_num_bufs =
2741 dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
2742
2743 ps_dec->disp_bufs[i].buf[0] =
2744 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
2745 ps_dec->disp_bufs[i].buf[1] =
2746 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
2747 ps_dec->disp_bufs[i].buf[2] =
2748 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
2749
2750 ps_dec->disp_bufs[i].u4_bufsize[0] =
2751 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
2752 ps_dec->disp_bufs[i].u4_bufsize[1] =
2753 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
2754 ps_dec->disp_bufs[i].u4_bufsize[2] =
2755 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
2756
2757 }
2758 }
2759 return IV_SUCCESS;
2760
2761 }
2762
2763 /*****************************************************************************/
2764 /* */
2765 /* Function Name : ih264d_set_flush_mode */
2766 /* */
2767 /* Description : */
2768 /* */
2769 /* Inputs :iv_obj_t decoder handle */
2770 /* :pv_api_ip pointer to input structure */
2771 /* :pv_api_op pointer to output structure */
2772 /* Globals : <Does it use any global variables?> */
2773 /* Outputs : */
2774 /* Returns : void */
2775 /* */
2776 /* Issues : none */
2777 /* */
2778 /* Revision History: */
2779 /* */
2780 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2781 /* 22 10 2008 100356 Draft */
2782 /* */
2783 /*****************************************************************************/
ih264d_set_flush_mode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2784 WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2785 {
2786 dec_struct_t * ps_dec;
2787 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
2788 ps_ctl_op->u4_error_code = 0;
2789
2790 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2791 UNUSED(pv_api_ip);
2792 /* ! */
2793 /* Signal flush frame control call */
2794 ps_dec->u1_flushfrm = 1;
2795
2796 if(ps_dec->u1_init_dec_flag == 1)
2797 {
2798 ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs);
2799 ih264d_release_display_bufs(ps_dec);
2800 }
2801
2802 ps_ctl_op->u4_error_code = 0;
2803
2804 /* Ignore dangling fields during flush */
2805 ps_dec->u1_top_bottom_decoded = 0;
2806
2807 return IV_SUCCESS;
2808 }
2809
2810 /*****************************************************************************/
2811 /* */
2812 /* Function Name : ih264d_get_status */
2813 /* */
2814 /* Description : */
2815 /* */
2816 /* Inputs :iv_obj_t decoder handle */
2817 /* :pv_api_ip pointer to input structure */
2818 /* :pv_api_op pointer to output structure */
2819 /* Globals : <Does it use any global variables?> */
2820 /* Outputs : */
2821 /* Returns : void */
2822 /* */
2823 /* Issues : none */
2824 /* */
2825 /* Revision History: */
2826 /* */
2827 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2828 /* 22 10 2008 100356 Draft */
2829 /* */
2830 /*****************************************************************************/
2831
ih264d_get_status(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2832 WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2833 {
2834
2835 UWORD32 i;
2836 dec_struct_t * ps_dec;
2837 UWORD32 pic_wd, pic_ht;
2838 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
2839 UNUSED(pv_api_ip);
2840 ps_ctl_op->u4_error_code = 0;
2841
2842 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2843
2844
2845 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2846 {
2847 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
2848 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
2849
2850 if(0 == ps_dec->u4_share_disp_buf)
2851 {
2852 pic_wd = ps_dec->u2_disp_width;
2853 pic_ht = ps_dec->u2_disp_height;
2854
2855 }
2856 else
2857 {
2858 pic_wd = ps_dec->u2_frm_wd_y;
2859 pic_ht = ps_dec->u2_frm_ht_y;
2860 }
2861 }
2862 else
2863 {
2864 pic_wd = 0;
2865 pic_ht = 0;
2866
2867 ps_ctl_op->u4_pic_ht = pic_wd;
2868 ps_ctl_op->u4_pic_wd = pic_ht;
2869
2870 if(1 == ps_dec->u4_share_disp_buf)
2871 {
2872 pic_wd += (PAD_LEN_Y_H << 1);
2873 pic_ht += (PAD_LEN_Y_V << 2);
2874
2875 }
2876
2877 }
2878
2879 if(ps_dec->u4_app_disp_width > pic_wd)
2880 pic_wd = ps_dec->u4_app_disp_width;
2881 if(0 == ps_dec->u4_share_disp_buf)
2882 ps_ctl_op->u4_num_disp_bufs = 1;
2883 else
2884 {
2885 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2886 {
2887 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
2888 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
2889 {
2890 ps_ctl_op->u4_num_disp_bufs =
2891 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
2892 }
2893 else
2894 {
2895 /*if VUI is not present assume maximum possible refrence frames for the level,
2896 * as max reorder frames*/
2897 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
2898 }
2899
2900 ps_ctl_op->u4_num_disp_bufs +=
2901 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
2902 }
2903 else
2904 {
2905 ps_ctl_op->u4_num_disp_bufs = 32;
2906 }
2907 ps_ctl_op->u4_num_disp_bufs = MAX(
2908 ps_ctl_op->u4_num_disp_bufs, 6);
2909 ps_ctl_op->u4_num_disp_bufs = MIN(
2910 ps_ctl_op->u4_num_disp_bufs, 32);
2911 }
2912
2913 ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
2914
2915 ps_ctl_op->u4_frame_rate = 0; //make it proper
2916 ps_ctl_op->u4_bit_rate = 0; //make it proper
2917 ps_ctl_op->e_content_type = ps_dec->i4_content_type;
2918 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
2919 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
2920
2921 if(ps_dec->u1_chroma_format == IV_YUV_420P)
2922 {
2923 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
2924 }
2925 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
2926 {
2927 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
2928 }
2929 else if(ps_dec->u1_chroma_format == IV_RGB_565)
2930 {
2931 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
2932 }
2933 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2934 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
2935 {
2936 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
2937 }
2938
2939 else
2940 {
2941 //Invalid chroma format; Error code may be updated, verify in testing if needed
2942 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
2943 return IV_FAIL;
2944 }
2945
2946 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
2947 {
2948 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
2949 }
2950
2951 /*!*/
2952 if(ps_dec->u1_chroma_format == IV_YUV_420P)
2953 {
2954 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
2955 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
2956 >> 2;
2957 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
2958 >> 2;
2959 }
2960 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
2961 {
2962 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
2963 * 2;
2964 ps_ctl_op->u4_min_out_buf_size[1] =
2965 ps_ctl_op->u4_min_out_buf_size[2] = 0;
2966 }
2967 else if(ps_dec->u1_chroma_format == IV_RGB_565)
2968 {
2969 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
2970 * 2;
2971 ps_ctl_op->u4_min_out_buf_size[1] =
2972 ps_ctl_op->u4_min_out_buf_size[2] = 0;
2973 }
2974 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2975 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
2976 {
2977 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
2978 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
2979 >> 1;
2980 ps_ctl_op->u4_min_out_buf_size[2] = 0;
2981 }
2982
2983 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
2984 return IV_SUCCESS;
2985 }
2986
2987 /*****************************************************************************/
2988 /* */
2989 /* Function Name : ih264d_get_buf_info */
2990 /* */
2991 /* Description : */
2992 /* */
2993 /* Inputs :iv_obj_t decoder handle */
2994 /* :pv_api_ip pointer to input structure */
2995 /* :pv_api_op pointer to output structure */
2996 /* Globals : <Does it use any global variables?> */
2997 /* Outputs : */
2998 /* Returns : void */
2999 /* */
3000 /* Issues : none */
3001 /* */
3002 /* Revision History: */
3003 /* */
3004 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3005 /* 22 10 2008 100356 Draft */
3006 /* */
3007 /*****************************************************************************/
ih264d_get_buf_info(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3008 WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3009 {
3010
3011 dec_struct_t * ps_dec;
3012 UWORD8 i = 0; // Default for 420P format
3013 UWORD16 pic_wd, pic_ht;
3014 ivd_ctl_getbufinfo_op_t *ps_ctl_op =
3015 (ivd_ctl_getbufinfo_op_t*)pv_api_op;
3016 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
3017 UNUSED(pv_api_ip);
3018
3019 ps_ctl_op->u4_error_code = 0;
3020
3021 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3022
3023 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3024
3025
3026 ps_ctl_op->u4_num_disp_bufs = 1;
3027
3028
3029 pic_wd = 0;
3030 pic_ht = 0;
3031
3032 if(ps_dec->i4_header_decoded == 3)
3033 {
3034
3035 if(0 == ps_dec->u4_share_disp_buf)
3036 {
3037 pic_wd = ps_dec->u2_disp_width;
3038 pic_ht = ps_dec->u2_disp_height;
3039
3040 }
3041 else
3042 {
3043 pic_wd = ps_dec->u2_frm_wd_y;
3044 pic_ht = ps_dec->u2_frm_ht_y;
3045 }
3046
3047 }
3048
3049 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3050 {
3051 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3052 }
3053 if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
3054 pic_wd = ps_dec->u4_app_disp_width;
3055
3056 if(0 == ps_dec->u4_share_disp_buf)
3057 ps_ctl_op->u4_num_disp_bufs = 1;
3058 else
3059 {
3060 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3061 {
3062 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3063 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3064 {
3065 ps_ctl_op->u4_num_disp_bufs =
3066 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3067 }
3068 else
3069 {
3070 /*if VUI is not present assume maximum possible refrence frames for the level,
3071 * as max reorder frames*/
3072 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3073 }
3074
3075 ps_ctl_op->u4_num_disp_bufs +=
3076 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3077
3078 }
3079 else
3080 {
3081 ps_ctl_op->u4_num_disp_bufs = 32;
3082
3083 }
3084
3085 ps_ctl_op->u4_num_disp_bufs = MAX(
3086 ps_ctl_op->u4_num_disp_bufs, 6);
3087 ps_ctl_op->u4_num_disp_bufs = MIN(
3088 ps_ctl_op->u4_num_disp_bufs, 32);
3089 }
3090
3091 ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size(
3092 pic_wd, pic_ht, ps_dec->u1_chroma_format,
3093 &au4_min_out_buf_size[0]);
3094
3095 for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++)
3096 {
3097 ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i];
3098 }
3099
3100 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3101
3102 return IV_SUCCESS;
3103 }
3104
3105 /*****************************************************************************/
3106 /* */
3107 /* Function Name : ih264d_set_params */
3108 /* */
3109 /* Description : */
3110 /* */
3111 /* Inputs :iv_obj_t decoder handle */
3112 /* :pv_api_ip pointer to input structure */
3113 /* :pv_api_op pointer to output structure */
3114 /* Outputs : */
3115 /* Returns : void */
3116 /* */
3117 /* Issues : none */
3118 /* */
3119 /* Revision History: */
3120 /* */
3121 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3122 /* 22 10 2008 100356 Draft */
3123 /* */
3124 /*****************************************************************************/
ih264d_set_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3125 WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3126 {
3127
3128 dec_struct_t * ps_dec;
3129 WORD32 ret = IV_SUCCESS;
3130
3131 ivd_ctl_set_config_ip_t *ps_ctl_ip =
3132 (ivd_ctl_set_config_ip_t *)pv_api_ip;
3133 ivd_ctl_set_config_op_t *ps_ctl_op =
3134 (ivd_ctl_set_config_op_t *)pv_api_op;
3135
3136 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3137
3138 ps_dec->u4_skip_frm_mask = 0;
3139
3140 ps_ctl_op->u4_error_code = 0;
3141
3142 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode;
3143
3144 /*Is it really supported test it when you so the corner testing using test app*/
3145
3146 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
3147 {
3148
3149 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P)
3150 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT;
3151 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B)
3152 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT;
3153 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB)
3154 {
3155 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT;
3156 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT;
3157 }
3158 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I)
3159 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT;
3160 else
3161 {
3162 //dynamic parameter not supported
3163 //Put an appropriate error code to return the error..
3164 //when you do the error code tests and after that remove this comment
3165 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3166 ret = IV_FAIL;
3167 }
3168 }
3169
3170 if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd)
3171 {
3172 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3173 }
3174 else if(0 == ps_dec->i4_header_decoded)
3175 {
3176 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3177 }
3178 else if(ps_ctl_ip->u4_disp_wd == 0)
3179 {
3180 ps_dec->u4_app_disp_width = 0;
3181 }
3182 else
3183 {
3184 /*
3185 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
3186 * does not propogate.
3187 */
3188 ps_dec->u4_app_disp_width = 0;
3189 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3190 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
3191 ret = IV_FAIL;
3192 }
3193
3194 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
3195 ps_dec->i4_decode_header = 0;
3196 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
3197 ps_dec->i4_decode_header = 1;
3198 else
3199 {
3200 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3201 ps_dec->i4_decode_header = 1;
3202 ret = IV_FAIL;
3203 }
3204 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
3205
3206 if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) &&
3207 (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT))
3208 {
3209 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3210 ret = IV_FAIL;
3211 }
3212 ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode;
3213 return ret;
3214
3215 }
3216
3217 /*****************************************************************************/
3218 /* */
3219 /* Function Name : ih264d_set_default_params */
3220 /* */
3221 /* Description : */
3222 /* */
3223 /* Inputs :iv_obj_t decoder handle */
3224 /* :pv_api_ip pointer to input structure */
3225 /* :pv_api_op pointer to output structure */
3226 /* Outputs : */
3227 /* Returns : void */
3228 /* */
3229 /* Issues : none */
3230 /* */
3231 /* Revision History: */
3232 /* */
3233 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3234 /* 08 08 2011 100421 Copied from set_params */
3235 /* */
3236 /*****************************************************************************/
ih264d_set_default_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3237 WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
3238 void *pv_api_ip,
3239 void *pv_api_op)
3240 {
3241
3242 dec_struct_t * ps_dec;
3243 WORD32 ret = IV_SUCCESS;
3244
3245 ivd_ctl_set_config_op_t *ps_ctl_op =
3246 (ivd_ctl_set_config_op_t *)pv_api_op;
3247 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3248 UNUSED(pv_api_ip);
3249
3250
3251 {
3252 ps_dec->u4_app_disp_width = 0;
3253 ps_dec->u4_skip_frm_mask = 0;
3254 ps_dec->i4_decode_header = 1;
3255
3256 ps_ctl_op->u4_error_code = 0;
3257 }
3258
3259
3260 return ret;
3261 }
3262 /*****************************************************************************/
3263 /* */
3264 /* Function Name : ih264d_reset */
3265 /* */
3266 /* Description : */
3267 /* */
3268 /* Inputs :iv_obj_t decoder handle */
3269 /* :pv_api_ip pointer to input structure */
3270 /* :pv_api_op pointer to output structure */
3271 /* Globals : <Does it use any global variables?> */
3272 /* Outputs : */
3273 /* Returns : void */
3274 /* */
3275 /* Issues : none */
3276 /* */
3277 /* Revision History: */
3278 /* */
3279 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3280 /* 22 10 2008 100356 Draft */
3281 /* */
3282 /*****************************************************************************/
ih264d_delete(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3283 WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3284 {
3285 dec_struct_t *ps_dec;
3286 ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip;
3287 ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op;
3288
3289 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3290 UNUSED(ps_ip);
3291 ps_op->s_ivd_delete_op_t.u4_error_code = 0;
3292 ih264d_free_dynamic_bufs(ps_dec);
3293 ih264d_free_static_bufs(dec_hdl);
3294 return IV_SUCCESS;
3295 }
3296 /*****************************************************************************/
3297 /* */
3298 /* Function Name : ih264d_reset */
3299 /* */
3300 /* Description : */
3301 /* */
3302 /* Inputs :iv_obj_t decoder handle */
3303 /* :pv_api_ip pointer to input structure */
3304 /* :pv_api_op pointer to output structure */
3305 /* Globals : <Does it use any global variables?> */
3306 /* Outputs : */
3307 /* Returns : void */
3308 /* */
3309 /* Issues : none */
3310 /* */
3311 /* Revision History: */
3312 /* */
3313 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3314 /* 22 10 2008 100356 Draft */
3315 /* */
3316 /*****************************************************************************/
ih264d_reset(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3317 WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3318 {
3319 dec_struct_t * ps_dec;
3320 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
3321 UNUSED(pv_api_ip);
3322 ps_ctl_op->u4_error_code = 0;
3323
3324 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3325
3326 if(ps_dec != NULL)
3327 {
3328 ih264d_init_decoder(ps_dec);
3329 }
3330 else
3331 {
3332 H264_DEC_DEBUG_PRINT(
3333 "\nReset called without Initializing the decoder\n");
3334 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
3335 }
3336
3337 return IV_SUCCESS;
3338 }
3339
3340 /*****************************************************************************/
3341 /* */
3342 /* Function Name : ih264d_ctl */
3343 /* */
3344 /* Description : */
3345 /* */
3346 /* Inputs :iv_obj_t decoder handle */
3347 /* :pv_api_ip pointer to input structure */
3348 /* :pv_api_op pointer to output structure */
3349 /* Outputs : */
3350 /* Returns : void */
3351 /* */
3352 /* Issues : none */
3353 /* */
3354 /* Revision History: */
3355 /* */
3356 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3357 /* 22 10 2008 100356 Draft */
3358 /* */
3359 /*****************************************************************************/
ih264d_ctl(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3360 WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3361 {
3362 ivd_ctl_set_config_ip_t *ps_ctl_ip;
3363 ivd_ctl_set_config_op_t *ps_ctl_op;
3364 WORD32 ret = IV_SUCCESS;
3365 UWORD32 subcommand;
3366 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3367
3368 if(ps_dec->init_done != 1)
3369 {
3370 //Return proper Error Code
3371 return IV_FAIL;
3372 }
3373 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
3374 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
3375 ps_ctl_op->u4_error_code = 0;
3376 subcommand = ps_ctl_ip->e_sub_cmd;
3377
3378 switch(subcommand)
3379 {
3380 case IVD_CMD_CTL_GETPARAMS:
3381 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
3382 (void *)pv_api_op);
3383 break;
3384 case IVD_CMD_CTL_SETPARAMS:
3385 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
3386 (void *)pv_api_op);
3387 break;
3388 case IVD_CMD_CTL_RESET:
3389 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
3390 break;
3391 case IVD_CMD_CTL_SETDEFAULT:
3392 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
3393 (void *)pv_api_op);
3394 break;
3395 case IVD_CMD_CTL_FLUSH:
3396 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
3397 (void *)pv_api_op);
3398 break;
3399 case IVD_CMD_CTL_GETBUFINFO:
3400 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
3401 (void *)pv_api_op);
3402 break;
3403 case IVD_CMD_CTL_GETVERSION:
3404 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
3405 (void *)pv_api_op);
3406 break;
3407 case IH264D_CMD_CTL_DEGRADE:
3408 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
3409 (void *)pv_api_op);
3410 break;
3411
3412 case IH264D_CMD_CTL_SET_NUM_CORES:
3413 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
3414 (void *)pv_api_op);
3415 break;
3416 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
3417 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
3418 (void *)pv_api_op);
3419 break;
3420 case IH264D_CMD_CTL_GET_VUI_PARAMS:
3421 ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip,
3422 (void *)pv_api_op);
3423 break;
3424
3425 case IH264D_CMD_CTL_SET_PROCESSOR:
3426 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
3427 (void *)pv_api_op);
3428 break;
3429 default:
3430 H264_DEC_DEBUG_PRINT("\ndo nothing\n")
3431 ;
3432 break;
3433 }
3434
3435 return ret;
3436 }
3437 /*****************************************************************************/
3438 /* */
3439 /* Function Name : ih264d_rel_display_frame */
3440 /* */
3441 /* Description : */
3442 /* */
3443 /* Inputs :iv_obj_t decoder handle */
3444 /* :pv_api_ip pointer to input structure */
3445 /* :pv_api_op pointer to output structure */
3446 /* Outputs : */
3447 /* Returns : void */
3448 /* */
3449 /* Issues : none */
3450 /* */
3451 /* Revision History: */
3452 /* */
3453 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3454 /* 22 10 2008 100356 Draft */
3455 /* */
3456 /*****************************************************************************/
ih264d_rel_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3457 WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
3458 void *pv_api_ip,
3459 void *pv_api_op)
3460 {
3461
3462 ivd_rel_display_frame_ip_t *ps_rel_ip;
3463 ivd_rel_display_frame_op_t *ps_rel_op;
3464 UWORD32 buf_released = 0;
3465
3466 UWORD32 u4_ts = -1;
3467 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3468
3469 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
3470 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
3471 ps_rel_op->u4_error_code = 0;
3472 u4_ts = ps_rel_ip->u4_disp_buf_id;
3473
3474 if(0 == ps_dec->u4_share_disp_buf)
3475 {
3476 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3477 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
3478 return IV_SUCCESS;
3479 }
3480
3481 if(ps_dec->pv_pic_buf_mgr != NULL)
3482 {
3483 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
3484 {
3485 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
3486 ps_rel_ip->u4_disp_buf_id,
3487 BUF_MGR_IO);
3488 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3489 buf_released = 1;
3490 }
3491 }
3492
3493 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
3494 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
3495
3496 return IV_SUCCESS;
3497 }
3498
3499 /**
3500 *******************************************************************************
3501 *
3502 * @brief
3503 * Sets degrade params
3504 *
3505 * @par Description:
3506 * Sets degrade params.
3507 * Refer to ih264d_ctl_degrade_ip_t definition for details
3508 *
3509 * @param[in] ps_codec_obj
3510 * Pointer to codec object at API level
3511 *
3512 * @param[in] pv_api_ip
3513 * Pointer to input argument structure
3514 *
3515 * @param[out] pv_api_op
3516 * Pointer to output argument structure
3517 *
3518 * @returns Status
3519 *
3520 * @remarks
3521 *
3522 *
3523 *******************************************************************************
3524 */
3525
ih264d_set_degrade(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)3526 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
3527 void *pv_api_ip,
3528 void *pv_api_op)
3529 {
3530 ih264d_ctl_degrade_ip_t *ps_ip;
3531 ih264d_ctl_degrade_op_t *ps_op;
3532 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
3533
3534 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
3535 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
3536
3537 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
3538 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
3539 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
3540
3541 ps_op->u4_error_code = 0;
3542 ps_codec->i4_degrade_pic_cnt = 0;
3543
3544 return IV_SUCCESS;
3545 }
3546
ih264d_get_frame_dimensions(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3547 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
3548 void *pv_api_ip,
3549 void *pv_api_op)
3550 {
3551 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
3552 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
3553 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3554 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
3555
3556 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
3557
3558 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
3559 UNUSED(ps_ip);
3560 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3561 {
3562 disp_wd = ps_dec->u2_disp_width;
3563 disp_ht = ps_dec->u2_disp_height;
3564
3565 if(0 == ps_dec->u4_share_disp_buf)
3566 {
3567 buffer_wd = disp_wd;
3568 buffer_ht = disp_ht;
3569 }
3570 else
3571 {
3572 buffer_wd = ps_dec->u2_frm_wd_y;
3573 buffer_ht = ps_dec->u2_frm_ht_y;
3574 }
3575 }
3576 else
3577 {
3578 disp_wd = 0;
3579 disp_ht = 0;
3580
3581 if(0 == ps_dec->u4_share_disp_buf)
3582 {
3583 buffer_wd = disp_wd;
3584 buffer_ht = disp_ht;
3585 }
3586 else
3587 {
3588 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
3589 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
3590 }
3591 }
3592 if(ps_dec->u4_app_disp_width > buffer_wd)
3593 buffer_wd = ps_dec->u4_app_disp_width;
3594
3595 if(0 == ps_dec->u4_share_disp_buf)
3596 {
3597 x_offset = 0;
3598 y_offset = 0;
3599 }
3600 else
3601 {
3602 y_offset = (PAD_LEN_Y_V << 1);
3603 x_offset = PAD_LEN_Y_H;
3604
3605 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
3606 && (0 != ps_dec->u2_crop_offset_y))
3607 {
3608 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
3609 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
3610 }
3611 }
3612
3613 ps_op->u4_disp_wd[0] = disp_wd;
3614 ps_op->u4_disp_ht[0] = disp_ht;
3615 ps_op->u4_buffer_wd[0] = buffer_wd;
3616 ps_op->u4_buffer_ht[0] = buffer_ht;
3617 ps_op->u4_x_offset[0] = x_offset;
3618 ps_op->u4_y_offset[0] = y_offset;
3619
3620 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
3621 >> 1);
3622 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
3623 >> 1);
3624 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
3625 >> 1);
3626 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
3627 >> 1);
3628 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
3629 (ps_op->u4_x_offset[0] >> 1);
3630 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
3631 (ps_op->u4_y_offset[0] >> 1);
3632
3633 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3634 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3635 {
3636 ps_op->u4_disp_wd[2] = 0;
3637 ps_op->u4_disp_ht[2] = 0;
3638 ps_op->u4_buffer_wd[2] = 0;
3639 ps_op->u4_buffer_ht[2] = 0;
3640 ps_op->u4_x_offset[2] = 0;
3641 ps_op->u4_y_offset[2] = 0;
3642
3643 ps_op->u4_disp_wd[1] <<= 1;
3644 ps_op->u4_buffer_wd[1] <<= 1;
3645 ps_op->u4_x_offset[1] <<= 1;
3646 }
3647
3648 return IV_SUCCESS;
3649
3650 }
3651
ih264d_get_vui_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3652 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
3653 void *pv_api_ip,
3654 void *pv_api_op)
3655 {
3656 ih264d_ctl_get_vui_params_ip_t *ps_ip;
3657 ih264d_ctl_get_vui_params_op_t *ps_op;
3658 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3659 dec_seq_params_t *ps_sps;
3660 vui_t *ps_vui;
3661 WORD32 i;
3662 UWORD32 u4_size;
3663
3664 ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
3665 ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
3666 UNUSED(ps_ip);
3667
3668 u4_size = ps_op->u4_size;
3669 memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t));
3670 ps_op->u4_size = u4_size;
3671
3672 if(NULL == ps_dec->ps_cur_sps)
3673 {
3674 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
3675 return IV_FAIL;
3676 }
3677
3678 ps_sps = ps_dec->ps_cur_sps;
3679 if((0 == ps_sps->u1_is_valid)
3680 || (0 == ps_sps->u1_vui_parameters_present_flag))
3681 {
3682 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
3683 return IV_FAIL;
3684 }
3685
3686 ps_vui = &ps_sps->s_vui;
3687
3688 ps_op->u1_aspect_ratio_idc = ps_vui->u1_aspect_ratio_idc;
3689 ps_op->u2_sar_width = ps_vui->u2_sar_width;
3690 ps_op->u2_sar_height = ps_vui->u2_sar_height;
3691 ps_op->u1_overscan_appropriate_flag = ps_vui->u1_overscan_appropriate_flag;
3692 ps_op->u1_video_format = ps_vui->u1_video_format;
3693 ps_op->u1_video_full_range_flag = ps_vui->u1_video_full_range_flag;
3694 ps_op->u1_colour_primaries = ps_vui->u1_colour_primaries;
3695 ps_op->u1_tfr_chars = ps_vui->u1_tfr_chars;
3696 ps_op->u1_matrix_coeffs = ps_vui->u1_matrix_coeffs;
3697 ps_op->u1_cr_top_field = ps_vui->u1_cr_top_field;
3698 ps_op->u1_cr_bottom_field = ps_vui->u1_cr_bottom_field;
3699 ps_op->u4_num_units_in_tick = ps_vui->u4_num_units_in_tick;
3700 ps_op->u4_time_scale = ps_vui->u4_time_scale;
3701 ps_op->u1_fixed_frame_rate_flag = ps_vui->u1_fixed_frame_rate_flag;
3702 ps_op->u1_nal_hrd_params_present = ps_vui->u1_nal_hrd_params_present;
3703 ps_op->u1_vcl_hrd_params_present = ps_vui->u1_vcl_hrd_params_present;
3704 ps_op->u1_low_delay_hrd_flag = ps_vui->u1_low_delay_hrd_flag;
3705 ps_op->u1_pic_struct_present_flag = ps_vui->u1_pic_struct_present_flag;
3706 ps_op->u1_bitstream_restriction_flag = ps_vui->u1_bitstream_restriction_flag;
3707 ps_op->u1_mv_over_pic_boundaries_flag = ps_vui->u1_mv_over_pic_boundaries_flag;
3708 ps_op->u4_max_bytes_per_pic_denom = ps_vui->u4_max_bytes_per_pic_denom;
3709 ps_op->u4_max_bits_per_mb_denom = ps_vui->u4_max_bits_per_mb_denom;
3710 ps_op->u4_log2_max_mv_length_horz = ps_vui->u4_log2_max_mv_length_horz;
3711 ps_op->u4_log2_max_mv_length_vert = ps_vui->u4_log2_max_mv_length_vert;
3712 ps_op->u4_num_reorder_frames = ps_vui->u4_num_reorder_frames;
3713 ps_op->u4_max_dec_frame_buffering = ps_vui->u4_max_dec_frame_buffering;
3714
3715 return IV_SUCCESS;
3716 }
3717
ih264d_set_num_cores(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3718 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3719 {
3720 ih264d_ctl_set_num_cores_ip_t *ps_ip;
3721 ih264d_ctl_set_num_cores_op_t *ps_op;
3722 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3723
3724 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
3725 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
3726 ps_op->u4_error_code = 0;
3727 ps_dec->u4_num_cores = ps_ip->u4_num_cores;
3728 if(ps_dec->u4_num_cores == 1)
3729 {
3730 ps_dec->u1_separate_parse = 0;
3731 }
3732 else
3733 {
3734 ps_dec->u1_separate_parse = 1;
3735 }
3736
3737 /*using only upto three threads currently*/
3738 if(ps_dec->u4_num_cores > 3)
3739 ps_dec->u4_num_cores = 3;
3740
3741 return IV_SUCCESS;
3742 }
3743
ih264d_fill_output_struct_from_context(dec_struct_t * ps_dec,ivd_video_decode_op_t * ps_dec_op)3744 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
3745 ivd_video_decode_op_t *ps_dec_op)
3746 {
3747 if((ps_dec_op->u4_error_code & 0xff)
3748 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
3749 {
3750 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
3751 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
3752 }
3753 ps_dec_op->e_pic_type = ps_dec->i4_frametype;
3754
3755 ps_dec_op->u4_new_seq = 0;
3756 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
3757 ps_dec_op->u4_progressive_frame_flag =
3758 ps_dec->s_disp_op.u4_progressive_frame_flag;
3759
3760 ps_dec_op->u4_is_ref_flag = 1;
3761 if(ps_dec_op->u4_frame_decoded_flag)
3762 {
3763 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
3764 ps_dec_op->u4_is_ref_flag = 0;
3765 }
3766
3767 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
3768 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
3769 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
3770 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
3771 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
3772 }
3773
3774 /*****************************************************************************/
3775 /* */
3776 /* Function Name : ih264d_api_function */
3777 /* */
3778 /* Description : */
3779 /* */
3780 /* Inputs :iv_obj_t decoder handle */
3781 /* :pv_api_ip pointer to input structure */
3782 /* :pv_api_op pointer to output structure */
3783 /* Outputs : */
3784 /* Returns : void */
3785 /* */
3786 /* Issues : none */
3787 /* */
3788 /* Revision History: */
3789 /* */
3790 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3791 /* 22 10 2008 100356 Draft */
3792 /* */
3793 /*****************************************************************************/
ih264d_api_function(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3794 IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
3795 void *pv_api_ip,
3796 void *pv_api_op)
3797 {
3798 UWORD32 command;
3799 UWORD32 *pu2_ptr_cmd;
3800 UWORD32 u4_api_ret;
3801 IV_API_CALL_STATUS_T e_status;
3802 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
3803
3804 if(e_status != IV_SUCCESS)
3805 {
3806 UWORD32 *ptr_err;
3807
3808 ptr_err = (UWORD32 *)pv_api_op;
3809 UNUSED(ptr_err);
3810 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
3811 return IV_FAIL;
3812 }
3813
3814 pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
3815 pu2_ptr_cmd++;
3816
3817 command = *pu2_ptr_cmd;
3818 // H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
3819 switch(command)
3820 {
3821
3822 case IVD_CMD_CREATE:
3823 u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip,
3824 (void *)pv_api_op);
3825 break;
3826 case IVD_CMD_DELETE:
3827 u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip,
3828 (void *)pv_api_op);
3829 break;
3830
3831 case IVD_CMD_VIDEO_DECODE:
3832 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
3833 (void *)pv_api_op);
3834 break;
3835
3836 case IVD_CMD_GET_DISPLAY_FRAME:
3837 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
3838 (void *)pv_api_op);
3839
3840 break;
3841
3842 case IVD_CMD_SET_DISPLAY_FRAME:
3843 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
3844 (void *)pv_api_op);
3845
3846 break;
3847
3848 case IVD_CMD_REL_DISPLAY_FRAME:
3849 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
3850 (void *)pv_api_op);
3851 break;
3852
3853 case IVD_CMD_VIDEO_CTL:
3854 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
3855 (void *)pv_api_op);
3856 break;
3857 default:
3858 u4_api_ret = IV_FAIL;
3859 break;
3860 }
3861
3862 return u4_api_ret;
3863 }
3864