1//===- TableGen'erated file -------------------------------------*- C++ -*-===// 2// 3// Target Register Enum Values 4// 5// Automatically generated file, do not edit! 6// 7//===----------------------------------------------------------------------===// 8 9 10#ifdef GET_REGINFO_ENUM 11#undef GET_REGINFO_ENUM 12namespace llvm { 13 14class MCRegisterClass; 15extern MCRegisterClass X86MCRegisterClasses[]; 16 17namespace X86 { 18enum { 19 NoRegister, 20 AH = 1, 21 AL = 2, 22 AX = 3, 23 BH = 4, 24 BL = 5, 25 BP = 6, 26 BPL = 7, 27 BX = 8, 28 CH = 9, 29 CL = 10, 30 CR0 = 11, 31 CR1 = 12, 32 CR2 = 13, 33 CR3 = 14, 34 CR4 = 15, 35 CR5 = 16, 36 CR6 = 17, 37 CR7 = 18, 38 CR8 = 19, 39 CR9 = 20, 40 CR10 = 21, 41 CR11 = 22, 42 CR12 = 23, 43 CR13 = 24, 44 CR14 = 25, 45 CR15 = 26, 46 CS = 27, 47 CX = 28, 48 DH = 29, 49 DI = 30, 50 DIL = 31, 51 DL = 32, 52 DR0 = 33, 53 DR1 = 34, 54 DR2 = 35, 55 DR3 = 36, 56 DR4 = 37, 57 DR5 = 38, 58 DR6 = 39, 59 DR7 = 40, 60 DS = 41, 61 DX = 42, 62 EAX = 43, 63 EBP = 44, 64 EBX = 45, 65 ECX = 46, 66 EDI = 47, 67 EDX = 48, 68 EFLAGS = 49, 69 EIP = 50, 70 EIZ = 51, 71 ES = 52, 72 ESI = 53, 73 ESP = 54, 74 FP0 = 55, 75 FP1 = 56, 76 FP2 = 57, 77 FP3 = 58, 78 FP4 = 59, 79 FP5 = 60, 80 FP6 = 61, 81 FS = 62, 82 GS = 63, 83 IP = 64, 84 MM0 = 65, 85 MM1 = 66, 86 MM2 = 67, 87 MM3 = 68, 88 MM4 = 69, 89 MM5 = 70, 90 MM6 = 71, 91 MM7 = 72, 92 R8 = 73, 93 R8B = 74, 94 R8D = 75, 95 R8W = 76, 96 R9 = 77, 97 R9B = 78, 98 R9D = 79, 99 R9W = 80, 100 R10 = 81, 101 R10B = 82, 102 R10D = 83, 103 R10W = 84, 104 R11 = 85, 105 R11B = 86, 106 R11D = 87, 107 R11W = 88, 108 R12 = 89, 109 R12B = 90, 110 R12D = 91, 111 R12W = 92, 112 R13 = 93, 113 R13B = 94, 114 R13D = 95, 115 R13W = 96, 116 R14 = 97, 117 R14B = 98, 118 R14D = 99, 119 R14W = 100, 120 R15 = 101, 121 R15B = 102, 122 R15D = 103, 123 R15W = 104, 124 RAX = 105, 125 RBP = 106, 126 RBX = 107, 127 RCX = 108, 128 RDI = 109, 129 RDX = 110, 130 RIP = 111, 131 RIZ = 112, 132 RSI = 113, 133 RSP = 114, 134 SI = 115, 135 SIL = 116, 136 SP = 117, 137 SPL = 118, 138 SS = 119, 139 ST0 = 120, 140 ST1 = 121, 141 ST2 = 122, 142 ST3 = 123, 143 ST4 = 124, 144 ST5 = 125, 145 ST6 = 126, 146 ST7 = 127, 147 XMM0 = 128, 148 XMM1 = 129, 149 XMM2 = 130, 150 XMM3 = 131, 151 XMM4 = 132, 152 XMM5 = 133, 153 XMM6 = 134, 154 XMM7 = 135, 155 XMM8 = 136, 156 XMM9 = 137, 157 XMM10 = 138, 158 XMM11 = 139, 159 XMM12 = 140, 160 XMM13 = 141, 161 XMM14 = 142, 162 XMM15 = 143, 163 YMM0 = 144, 164 YMM1 = 145, 165 YMM2 = 146, 166 YMM3 = 147, 167 YMM4 = 148, 168 YMM5 = 149, 169 YMM6 = 150, 170 YMM7 = 151, 171 YMM8 = 152, 172 YMM9 = 153, 173 YMM10 = 154, 174 YMM11 = 155, 175 YMM12 = 156, 176 YMM13 = 157, 177 YMM14 = 158, 178 YMM15 = 159, 179 NUM_TARGET_REGS // 160 180}; 181} 182 183// Register classes 184namespace X86 { 185enum { 186 GR8RegClassID = 0, 187 GR64RegClassID = 1, 188 GR16RegClassID = 2, 189 GR32RegClassID = 3, 190 FR32RegClassID = 4, 191 GR64_with_sub_8bitRegClassID = 5, 192 FR64RegClassID = 6, 193 CONTROL_REGRegClassID = 7, 194 VR128RegClassID = 8, 195 VR256RegClassID = 9, 196 GR32_NOSPRegClassID = 10, 197 GR32_NOAXRegClassID = 11, 198 GR64_NOSPRegClassID = 12, 199 GR64_TCRegClassID = 13, 200 GR64_NOREXRegClassID = 14, 201 GR8_NOREXRegClassID = 15, 202 GR16_NOREXRegClassID = 16, 203 GR32_NOREXRegClassID = 17, 204 DEBUG_REGRegClassID = 18, 205 VR64RegClassID = 19, 206 GR64_TC_with_sub_8bitRegClassID = 20, 207 GR64_NOREX_with_sub_8bitRegClassID = 21, 208 RSTRegClassID = 22, 209 RFP32RegClassID = 23, 210 GR32_NOREX_NOSPRegClassID = 24, 211 RFP64RegClassID = 25, 212 GR64_NOREX_NOSPRegClassID = 26, 213 RFP80RegClassID = 27, 214 SEGMENT_REGRegClassID = 28, 215 GR64_TCW64RegClassID = 29, 216 GR8_ABCD_LRegClassID = 30, 217 GR8_ABCD_HRegClassID = 31, 218 GR16_ABCDRegClassID = 32, 219 GR32_ABCDRegClassID = 33, 220 GR64_ABCDRegClassID = 34, 221 GR32_TCRegClassID = 35, 222 GR32_NOAX_with_sub_8bit_hiRegClassID = 36, 223 GR64_TC_with_sub_8bit_hiRegClassID = 37, 224 GR32_ADRegClassID = 38, 225 CCRRegClassID = 39 226 }; 227} 228} // End llvm namespace 229#endif // GET_REGINFO_ENUM 230 231//===- TableGen'erated file -------------------------------------*- C++ -*-===// 232// 233// MC Register Information 234// 235// Automatically generated file, do not edit! 236// 237//===----------------------------------------------------------------------===// 238 239 240#ifdef GET_REGINFO_MC_DESC 241#undef GET_REGINFO_MC_DESC 242namespace llvm { 243 244struct X86GenMCRegisterInfo : public MCRegisterInfo { 245 explicit X86GenMCRegisterInfo(const MCRegisterDesc *D); 246}; 247 248namespace { 249 const unsigned AH_Overlaps[] = { X86::AH, X86::AX, X86::EAX, X86::RAX, 0 }; 250 const unsigned AL_Overlaps[] = { X86::AL, X86::AX, X86::EAX, X86::RAX, 0 }; 251 const unsigned AX_Overlaps[] = { X86::AX, X86::AH, X86::AL, X86::EAX, X86::RAX, 0 }; 252 const unsigned BH_Overlaps[] = { X86::BH, X86::BX, X86::EBX, X86::RBX, 0 }; 253 const unsigned BL_Overlaps[] = { X86::BL, X86::BX, X86::EBX, X86::RBX, 0 }; 254 const unsigned BP_Overlaps[] = { X86::BP, X86::BPL, X86::EBP, X86::RBP, 0 }; 255 const unsigned BPL_Overlaps[] = { X86::BPL, X86::BP, X86::EBP, X86::RBP, 0 }; 256 const unsigned BX_Overlaps[] = { X86::BX, X86::BH, X86::BL, X86::EBX, X86::RBX, 0 }; 257 const unsigned CH_Overlaps[] = { X86::CH, X86::CX, X86::ECX, X86::RCX, 0 }; 258 const unsigned CL_Overlaps[] = { X86::CL, X86::CX, X86::ECX, X86::RCX, 0 }; 259 const unsigned CR0_Overlaps[] = { X86::CR0, 0 }; 260 const unsigned CR1_Overlaps[] = { X86::CR1, 0 }; 261 const unsigned CR2_Overlaps[] = { X86::CR2, 0 }; 262 const unsigned CR3_Overlaps[] = { X86::CR3, 0 }; 263 const unsigned CR4_Overlaps[] = { X86::CR4, 0 }; 264 const unsigned CR5_Overlaps[] = { X86::CR5, 0 }; 265 const unsigned CR6_Overlaps[] = { X86::CR6, 0 }; 266 const unsigned CR7_Overlaps[] = { X86::CR7, 0 }; 267 const unsigned CR8_Overlaps[] = { X86::CR8, 0 }; 268 const unsigned CR9_Overlaps[] = { X86::CR9, 0 }; 269 const unsigned CR10_Overlaps[] = { X86::CR10, 0 }; 270 const unsigned CR11_Overlaps[] = { X86::CR11, 0 }; 271 const unsigned CR12_Overlaps[] = { X86::CR12, 0 }; 272 const unsigned CR13_Overlaps[] = { X86::CR13, 0 }; 273 const unsigned CR14_Overlaps[] = { X86::CR14, 0 }; 274 const unsigned CR15_Overlaps[] = { X86::CR15, 0 }; 275 const unsigned CS_Overlaps[] = { X86::CS, 0 }; 276 const unsigned CX_Overlaps[] = { X86::CX, X86::CH, X86::CL, X86::ECX, X86::RCX, 0 }; 277 const unsigned DH_Overlaps[] = { X86::DH, X86::DX, X86::EDX, X86::RDX, 0 }; 278 const unsigned DI_Overlaps[] = { X86::DI, X86::DIL, X86::EDI, X86::RDI, 0 }; 279 const unsigned DIL_Overlaps[] = { X86::DIL, X86::DI, X86::EDI, X86::RDI, 0 }; 280 const unsigned DL_Overlaps[] = { X86::DL, X86::DX, X86::EDX, X86::RDX, 0 }; 281 const unsigned DR0_Overlaps[] = { X86::DR0, 0 }; 282 const unsigned DR1_Overlaps[] = { X86::DR1, 0 }; 283 const unsigned DR2_Overlaps[] = { X86::DR2, 0 }; 284 const unsigned DR3_Overlaps[] = { X86::DR3, 0 }; 285 const unsigned DR4_Overlaps[] = { X86::DR4, 0 }; 286 const unsigned DR5_Overlaps[] = { X86::DR5, 0 }; 287 const unsigned DR6_Overlaps[] = { X86::DR6, 0 }; 288 const unsigned DR7_Overlaps[] = { X86::DR7, 0 }; 289 const unsigned DS_Overlaps[] = { X86::DS, 0 }; 290 const unsigned DX_Overlaps[] = { X86::DX, X86::DH, X86::DL, X86::EDX, X86::RDX, 0 }; 291 const unsigned EAX_Overlaps[] = { X86::EAX, X86::AH, X86::AL, X86::AX, X86::RAX, 0 }; 292 const unsigned EBP_Overlaps[] = { X86::EBP, X86::BP, X86::BPL, X86::RBP, 0 }; 293 const unsigned EBX_Overlaps[] = { X86::EBX, X86::BH, X86::BL, X86::BX, X86::RBX, 0 }; 294 const unsigned ECX_Overlaps[] = { X86::ECX, X86::CH, X86::CL, X86::CX, X86::RCX, 0 }; 295 const unsigned EDI_Overlaps[] = { X86::EDI, X86::DI, X86::DIL, X86::RDI, 0 }; 296 const unsigned EDX_Overlaps[] = { X86::EDX, X86::DH, X86::DL, X86::DX, X86::RDX, 0 }; 297 const unsigned EFLAGS_Overlaps[] = { X86::EFLAGS, 0 }; 298 const unsigned EIP_Overlaps[] = { X86::EIP, X86::IP, X86::RIP, 0 }; 299 const unsigned EIZ_Overlaps[] = { X86::EIZ, 0 }; 300 const unsigned ES_Overlaps[] = { X86::ES, 0 }; 301 const unsigned ESI_Overlaps[] = { X86::ESI, X86::RSI, X86::SI, X86::SIL, 0 }; 302 const unsigned ESP_Overlaps[] = { X86::ESP, X86::RSP, X86::SP, X86::SPL, 0 }; 303 const unsigned FP0_Overlaps[] = { X86::FP0, X86::ST7, 0 }; 304 const unsigned FP1_Overlaps[] = { X86::FP1, X86::ST6, 0 }; 305 const unsigned FP2_Overlaps[] = { X86::FP2, X86::ST5, 0 }; 306 const unsigned FP3_Overlaps[] = { X86::FP3, X86::ST4, 0 }; 307 const unsigned FP4_Overlaps[] = { X86::FP4, X86::ST3, 0 }; 308 const unsigned FP5_Overlaps[] = { X86::FP5, X86::ST2, 0 }; 309 const unsigned FP6_Overlaps[] = { X86::FP6, X86::ST1, 0 }; 310 const unsigned FS_Overlaps[] = { X86::FS, 0 }; 311 const unsigned GS_Overlaps[] = { X86::GS, 0 }; 312 const unsigned IP_Overlaps[] = { X86::IP, X86::EIP, X86::RIP, 0 }; 313 const unsigned MM0_Overlaps[] = { X86::MM0, 0 }; 314 const unsigned MM1_Overlaps[] = { X86::MM1, 0 }; 315 const unsigned MM2_Overlaps[] = { X86::MM2, 0 }; 316 const unsigned MM3_Overlaps[] = { X86::MM3, 0 }; 317 const unsigned MM4_Overlaps[] = { X86::MM4, 0 }; 318 const unsigned MM5_Overlaps[] = { X86::MM5, 0 }; 319 const unsigned MM6_Overlaps[] = { X86::MM6, 0 }; 320 const unsigned MM7_Overlaps[] = { X86::MM7, 0 }; 321 const unsigned R8_Overlaps[] = { X86::R8, X86::R8B, X86::R8D, X86::R8W, 0 }; 322 const unsigned R8B_Overlaps[] = { X86::R8B, X86::R8, X86::R8D, X86::R8W, 0 }; 323 const unsigned R8D_Overlaps[] = { X86::R8D, X86::R8, X86::R8B, X86::R8W, 0 }; 324 const unsigned R8W_Overlaps[] = { X86::R8W, X86::R8, X86::R8B, X86::R8D, 0 }; 325 const unsigned R9_Overlaps[] = { X86::R9, X86::R9B, X86::R9D, X86::R9W, 0 }; 326 const unsigned R9B_Overlaps[] = { X86::R9B, X86::R9, X86::R9D, X86::R9W, 0 }; 327 const unsigned R9D_Overlaps[] = { X86::R9D, X86::R9, X86::R9B, X86::R9W, 0 }; 328 const unsigned R9W_Overlaps[] = { X86::R9W, X86::R9, X86::R9B, X86::R9D, 0 }; 329 const unsigned R10_Overlaps[] = { X86::R10, X86::R10B, X86::R10D, X86::R10W, 0 }; 330 const unsigned R10B_Overlaps[] = { X86::R10B, X86::R10, X86::R10D, X86::R10W, 0 }; 331 const unsigned R10D_Overlaps[] = { X86::R10D, X86::R10, X86::R10B, X86::R10W, 0 }; 332 const unsigned R10W_Overlaps[] = { X86::R10W, X86::R10, X86::R10B, X86::R10D, 0 }; 333 const unsigned R11_Overlaps[] = { X86::R11, X86::R11B, X86::R11D, X86::R11W, 0 }; 334 const unsigned R11B_Overlaps[] = { X86::R11B, X86::R11, X86::R11D, X86::R11W, 0 }; 335 const unsigned R11D_Overlaps[] = { X86::R11D, X86::R11, X86::R11B, X86::R11W, 0 }; 336 const unsigned R11W_Overlaps[] = { X86::R11W, X86::R11, X86::R11B, X86::R11D, 0 }; 337 const unsigned R12_Overlaps[] = { X86::R12, X86::R12B, X86::R12D, X86::R12W, 0 }; 338 const unsigned R12B_Overlaps[] = { X86::R12B, X86::R12, X86::R12D, X86::R12W, 0 }; 339 const unsigned R12D_Overlaps[] = { X86::R12D, X86::R12, X86::R12B, X86::R12W, 0 }; 340 const unsigned R12W_Overlaps[] = { X86::R12W, X86::R12, X86::R12B, X86::R12D, 0 }; 341 const unsigned R13_Overlaps[] = { X86::R13, X86::R13B, X86::R13D, X86::R13W, 0 }; 342 const unsigned R13B_Overlaps[] = { X86::R13B, X86::R13, X86::R13D, X86::R13W, 0 }; 343 const unsigned R13D_Overlaps[] = { X86::R13D, X86::R13, X86::R13B, X86::R13W, 0 }; 344 const unsigned R13W_Overlaps[] = { X86::R13W, X86::R13, X86::R13B, X86::R13D, 0 }; 345 const unsigned R14_Overlaps[] = { X86::R14, X86::R14B, X86::R14D, X86::R14W, 0 }; 346 const unsigned R14B_Overlaps[] = { X86::R14B, X86::R14, X86::R14D, X86::R14W, 0 }; 347 const unsigned R14D_Overlaps[] = { X86::R14D, X86::R14, X86::R14B, X86::R14W, 0 }; 348 const unsigned R14W_Overlaps[] = { X86::R14W, X86::R14, X86::R14B, X86::R14D, 0 }; 349 const unsigned R15_Overlaps[] = { X86::R15, X86::R15B, X86::R15D, X86::R15W, 0 }; 350 const unsigned R15B_Overlaps[] = { X86::R15B, X86::R15, X86::R15D, X86::R15W, 0 }; 351 const unsigned R15D_Overlaps[] = { X86::R15D, X86::R15, X86::R15B, X86::R15W, 0 }; 352 const unsigned R15W_Overlaps[] = { X86::R15W, X86::R15, X86::R15B, X86::R15D, 0 }; 353 const unsigned RAX_Overlaps[] = { X86::RAX, X86::AH, X86::AL, X86::AX, X86::EAX, 0 }; 354 const unsigned RBP_Overlaps[] = { X86::RBP, X86::BP, X86::BPL, X86::EBP, 0 }; 355 const unsigned RBX_Overlaps[] = { X86::RBX, X86::BH, X86::BL, X86::BX, X86::EBX, 0 }; 356 const unsigned RCX_Overlaps[] = { X86::RCX, X86::CH, X86::CL, X86::CX, X86::ECX, 0 }; 357 const unsigned RDI_Overlaps[] = { X86::RDI, X86::DI, X86::DIL, X86::EDI, 0 }; 358 const unsigned RDX_Overlaps[] = { X86::RDX, X86::DH, X86::DL, X86::DX, X86::EDX, 0 }; 359 const unsigned RIP_Overlaps[] = { X86::RIP, X86::EIP, X86::IP, 0 }; 360 const unsigned RIZ_Overlaps[] = { X86::RIZ, 0 }; 361 const unsigned RSI_Overlaps[] = { X86::RSI, X86::ESI, X86::SI, X86::SIL, 0 }; 362 const unsigned RSP_Overlaps[] = { X86::RSP, X86::ESP, X86::SP, X86::SPL, 0 }; 363 const unsigned SI_Overlaps[] = { X86::SI, X86::ESI, X86::RSI, X86::SIL, 0 }; 364 const unsigned SIL_Overlaps[] = { X86::SIL, X86::ESI, X86::RSI, X86::SI, 0 }; 365 const unsigned SP_Overlaps[] = { X86::SP, X86::ESP, X86::RSP, X86::SPL, 0 }; 366 const unsigned SPL_Overlaps[] = { X86::SPL, X86::ESP, X86::RSP, X86::SP, 0 }; 367 const unsigned SS_Overlaps[] = { X86::SS, 0 }; 368 const unsigned ST0_Overlaps[] = { X86::ST0, 0 }; 369 const unsigned ST1_Overlaps[] = { X86::ST1, X86::FP6, 0 }; 370 const unsigned ST2_Overlaps[] = { X86::ST2, X86::FP5, 0 }; 371 const unsigned ST3_Overlaps[] = { X86::ST3, X86::FP4, 0 }; 372 const unsigned ST4_Overlaps[] = { X86::ST4, X86::FP3, 0 }; 373 const unsigned ST5_Overlaps[] = { X86::ST5, X86::FP2, 0 }; 374 const unsigned ST6_Overlaps[] = { X86::ST6, X86::FP1, 0 }; 375 const unsigned ST7_Overlaps[] = { X86::ST7, X86::FP0, 0 }; 376 const unsigned XMM0_Overlaps[] = { X86::XMM0, X86::YMM0, 0 }; 377 const unsigned XMM1_Overlaps[] = { X86::XMM1, X86::YMM1, 0 }; 378 const unsigned XMM2_Overlaps[] = { X86::XMM2, X86::YMM2, 0 }; 379 const unsigned XMM3_Overlaps[] = { X86::XMM3, X86::YMM3, 0 }; 380 const unsigned XMM4_Overlaps[] = { X86::XMM4, X86::YMM4, 0 }; 381 const unsigned XMM5_Overlaps[] = { X86::XMM5, X86::YMM5, 0 }; 382 const unsigned XMM6_Overlaps[] = { X86::XMM6, X86::YMM6, 0 }; 383 const unsigned XMM7_Overlaps[] = { X86::XMM7, X86::YMM7, 0 }; 384 const unsigned XMM8_Overlaps[] = { X86::XMM8, X86::YMM8, 0 }; 385 const unsigned XMM9_Overlaps[] = { X86::XMM9, X86::YMM9, 0 }; 386 const unsigned XMM10_Overlaps[] = { X86::XMM10, X86::YMM10, 0 }; 387 const unsigned XMM11_Overlaps[] = { X86::XMM11, X86::YMM11, 0 }; 388 const unsigned XMM12_Overlaps[] = { X86::XMM12, X86::YMM12, 0 }; 389 const unsigned XMM13_Overlaps[] = { X86::XMM13, X86::YMM13, 0 }; 390 const unsigned XMM14_Overlaps[] = { X86::XMM14, X86::YMM14, 0 }; 391 const unsigned XMM15_Overlaps[] = { X86::XMM15, X86::YMM15, 0 }; 392 const unsigned YMM0_Overlaps[] = { X86::YMM0, X86::XMM0, 0 }; 393 const unsigned YMM1_Overlaps[] = { X86::YMM1, X86::XMM1, 0 }; 394 const unsigned YMM2_Overlaps[] = { X86::YMM2, X86::XMM2, 0 }; 395 const unsigned YMM3_Overlaps[] = { X86::YMM3, X86::XMM3, 0 }; 396 const unsigned YMM4_Overlaps[] = { X86::YMM4, X86::XMM4, 0 }; 397 const unsigned YMM5_Overlaps[] = { X86::YMM5, X86::XMM5, 0 }; 398 const unsigned YMM6_Overlaps[] = { X86::YMM6, X86::XMM6, 0 }; 399 const unsigned YMM7_Overlaps[] = { X86::YMM7, X86::XMM7, 0 }; 400 const unsigned YMM8_Overlaps[] = { X86::YMM8, X86::XMM8, 0 }; 401 const unsigned YMM9_Overlaps[] = { X86::YMM9, X86::XMM9, 0 }; 402 const unsigned YMM10_Overlaps[] = { X86::YMM10, X86::XMM10, 0 }; 403 const unsigned YMM11_Overlaps[] = { X86::YMM11, X86::XMM11, 0 }; 404 const unsigned YMM12_Overlaps[] = { X86::YMM12, X86::XMM12, 0 }; 405 const unsigned YMM13_Overlaps[] = { X86::YMM13, X86::XMM13, 0 }; 406 const unsigned YMM14_Overlaps[] = { X86::YMM14, X86::XMM14, 0 }; 407 const unsigned YMM15_Overlaps[] = { X86::YMM15, X86::XMM15, 0 }; 408 const unsigned Empty_SubRegsSet[] = { 0 }; 409 const unsigned AX_SubRegsSet[] = { X86::AL, X86::AH, 0 }; 410 const unsigned BP_SubRegsSet[] = { X86::BPL, 0 }; 411 const unsigned BX_SubRegsSet[] = { X86::BL, X86::BH, 0 }; 412 const unsigned CX_SubRegsSet[] = { X86::CL, X86::CH, 0 }; 413 const unsigned DI_SubRegsSet[] = { X86::DIL, 0 }; 414 const unsigned DX_SubRegsSet[] = { X86::DL, X86::DH, 0 }; 415 const unsigned EAX_SubRegsSet[] = { X86::AX, X86::AL, X86::AH, 0 }; 416 const unsigned EBP_SubRegsSet[] = { X86::BP, X86::BPL, 0 }; 417 const unsigned EBX_SubRegsSet[] = { X86::BX, X86::BL, X86::BH, 0 }; 418 const unsigned ECX_SubRegsSet[] = { X86::CX, X86::CL, X86::CH, 0 }; 419 const unsigned EDI_SubRegsSet[] = { X86::DI, X86::DIL, 0 }; 420 const unsigned EDX_SubRegsSet[] = { X86::DX, X86::DL, X86::DH, 0 }; 421 const unsigned EIP_SubRegsSet[] = { X86::IP, 0 }; 422 const unsigned ESI_SubRegsSet[] = { X86::SI, X86::SIL, 0 }; 423 const unsigned ESP_SubRegsSet[] = { X86::SP, X86::SPL, 0 }; 424 const unsigned R8_SubRegsSet[] = { X86::R8D, X86::R8W, X86::R8B, 0 }; 425 const unsigned R8D_SubRegsSet[] = { X86::R8W, X86::R8B, 0 }; 426 const unsigned R8W_SubRegsSet[] = { X86::R8B, 0 }; 427 const unsigned R9_SubRegsSet[] = { X86::R9D, X86::R9W, X86::R9B, 0 }; 428 const unsigned R9D_SubRegsSet[] = { X86::R9W, X86::R9B, 0 }; 429 const unsigned R9W_SubRegsSet[] = { X86::R9B, 0 }; 430 const unsigned R10_SubRegsSet[] = { X86::R10D, X86::R10W, X86::R10B, 0 }; 431 const unsigned R10D_SubRegsSet[] = { X86::R10W, X86::R10B, 0 }; 432 const unsigned R10W_SubRegsSet[] = { X86::R10B, 0 }; 433 const unsigned R11_SubRegsSet[] = { X86::R11D, X86::R11W, X86::R11B, 0 }; 434 const unsigned R11D_SubRegsSet[] = { X86::R11W, X86::R11B, 0 }; 435 const unsigned R11W_SubRegsSet[] = { X86::R11B, 0 }; 436 const unsigned R12_SubRegsSet[] = { X86::R12D, X86::R12W, X86::R12B, 0 }; 437 const unsigned R12D_SubRegsSet[] = { X86::R12W, X86::R12B, 0 }; 438 const unsigned R12W_SubRegsSet[] = { X86::R12B, 0 }; 439 const unsigned R13_SubRegsSet[] = { X86::R13D, X86::R13W, X86::R13B, 0 }; 440 const unsigned R13D_SubRegsSet[] = { X86::R13W, X86::R13B, 0 }; 441 const unsigned R13W_SubRegsSet[] = { X86::R13B, 0 }; 442 const unsigned R14_SubRegsSet[] = { X86::R14D, X86::R14W, X86::R14B, 0 }; 443 const unsigned R14D_SubRegsSet[] = { X86::R14W, X86::R14B, 0 }; 444 const unsigned R14W_SubRegsSet[] = { X86::R14B, 0 }; 445 const unsigned R15_SubRegsSet[] = { X86::R15D, X86::R15W, X86::R15B, 0 }; 446 const unsigned R15D_SubRegsSet[] = { X86::R15W, X86::R15B, 0 }; 447 const unsigned R15W_SubRegsSet[] = { X86::R15B, 0 }; 448 const unsigned RAX_SubRegsSet[] = { X86::EAX, X86::AX, X86::AL, X86::AH, 0 }; 449 const unsigned RBP_SubRegsSet[] = { X86::EBP, X86::BP, X86::BPL, 0 }; 450 const unsigned RBX_SubRegsSet[] = { X86::EBX, X86::BX, X86::BL, X86::BH, 0 }; 451 const unsigned RCX_SubRegsSet[] = { X86::ECX, X86::CX, X86::CL, X86::CH, 0 }; 452 const unsigned RDI_SubRegsSet[] = { X86::EDI, X86::DI, X86::DIL, 0 }; 453 const unsigned RDX_SubRegsSet[] = { X86::EDX, X86::DX, X86::DL, X86::DH, 0 }; 454 const unsigned RIP_SubRegsSet[] = { X86::EIP, X86::IP, 0 }; 455 const unsigned RSI_SubRegsSet[] = { X86::ESI, X86::SI, X86::SIL, 0 }; 456 const unsigned RSP_SubRegsSet[] = { X86::ESP, X86::SP, X86::SPL, 0 }; 457 const unsigned SI_SubRegsSet[] = { X86::SIL, 0 }; 458 const unsigned SP_SubRegsSet[] = { X86::SPL, 0 }; 459 const unsigned XMM0_SubRegsSet[] = { 0 }; 460 const unsigned XMM1_SubRegsSet[] = { 0 }; 461 const unsigned XMM2_SubRegsSet[] = { 0 }; 462 const unsigned XMM3_SubRegsSet[] = { 0 }; 463 const unsigned XMM4_SubRegsSet[] = { 0 }; 464 const unsigned XMM5_SubRegsSet[] = { 0 }; 465 const unsigned XMM6_SubRegsSet[] = { 0 }; 466 const unsigned XMM7_SubRegsSet[] = { 0 }; 467 const unsigned XMM8_SubRegsSet[] = { 0 }; 468 const unsigned XMM9_SubRegsSet[] = { 0 }; 469 const unsigned XMM10_SubRegsSet[] = { 0 }; 470 const unsigned XMM11_SubRegsSet[] = { 0 }; 471 const unsigned XMM12_SubRegsSet[] = { 0 }; 472 const unsigned XMM13_SubRegsSet[] = { 0 }; 473 const unsigned XMM14_SubRegsSet[] = { 0 }; 474 const unsigned XMM15_SubRegsSet[] = { 0 }; 475 const unsigned YMM0_SubRegsSet[] = { X86::XMM0, 0 }; 476 const unsigned YMM1_SubRegsSet[] = { X86::XMM1, 0 }; 477 const unsigned YMM2_SubRegsSet[] = { X86::XMM2, 0 }; 478 const unsigned YMM3_SubRegsSet[] = { X86::XMM3, 0 }; 479 const unsigned YMM4_SubRegsSet[] = { X86::XMM4, 0 }; 480 const unsigned YMM5_SubRegsSet[] = { X86::XMM5, 0 }; 481 const unsigned YMM6_SubRegsSet[] = { X86::XMM6, 0 }; 482 const unsigned YMM7_SubRegsSet[] = { X86::XMM7, 0 }; 483 const unsigned YMM8_SubRegsSet[] = { X86::XMM8, 0 }; 484 const unsigned YMM9_SubRegsSet[] = { X86::XMM9, 0 }; 485 const unsigned YMM10_SubRegsSet[] = { X86::XMM10, 0 }; 486 const unsigned YMM11_SubRegsSet[] = { X86::XMM11, 0 }; 487 const unsigned YMM12_SubRegsSet[] = { X86::XMM12, 0 }; 488 const unsigned YMM13_SubRegsSet[] = { X86::XMM13, 0 }; 489 const unsigned YMM14_SubRegsSet[] = { X86::XMM14, 0 }; 490 const unsigned YMM15_SubRegsSet[] = { X86::XMM15, 0 }; 491 const unsigned Empty_SuperRegsSet[] = { 0 }; 492 const unsigned AH_SuperRegsSet[] = { X86::AX, X86::EAX, X86::RAX, 0 }; 493 const unsigned AL_SuperRegsSet[] = { X86::AX, X86::EAX, X86::RAX, 0 }; 494 const unsigned AX_SuperRegsSet[] = { X86::EAX, X86::RAX, 0 }; 495 const unsigned BH_SuperRegsSet[] = { X86::BX, X86::EBX, X86::RBX, 0 }; 496 const unsigned BL_SuperRegsSet[] = { X86::BX, X86::EBX, X86::RBX, 0 }; 497 const unsigned BP_SuperRegsSet[] = { X86::EBP, X86::RBP, 0 }; 498 const unsigned BPL_SuperRegsSet[] = { X86::BP, X86::EBP, X86::RBP, 0 }; 499 const unsigned BX_SuperRegsSet[] = { X86::EBX, X86::RBX, 0 }; 500 const unsigned CH_SuperRegsSet[] = { X86::CX, X86::ECX, X86::RCX, 0 }; 501 const unsigned CL_SuperRegsSet[] = { X86::CX, X86::ECX, X86::RCX, 0 }; 502 const unsigned CX_SuperRegsSet[] = { X86::ECX, X86::RCX, 0 }; 503 const unsigned DH_SuperRegsSet[] = { X86::DX, X86::EDX, X86::RDX, 0 }; 504 const unsigned DI_SuperRegsSet[] = { X86::EDI, X86::RDI, 0 }; 505 const unsigned DIL_SuperRegsSet[] = { X86::DI, X86::EDI, X86::RDI, 0 }; 506 const unsigned DL_SuperRegsSet[] = { X86::DX, X86::EDX, X86::RDX, 0 }; 507 const unsigned DX_SuperRegsSet[] = { X86::EDX, X86::RDX, 0 }; 508 const unsigned EAX_SuperRegsSet[] = { X86::RAX, 0 }; 509 const unsigned EBP_SuperRegsSet[] = { X86::RBP, 0 }; 510 const unsigned EBX_SuperRegsSet[] = { X86::RBX, 0 }; 511 const unsigned ECX_SuperRegsSet[] = { X86::RCX, 0 }; 512 const unsigned EDI_SuperRegsSet[] = { X86::RDI, 0 }; 513 const unsigned EDX_SuperRegsSet[] = { X86::RDX, 0 }; 514 const unsigned EIP_SuperRegsSet[] = { X86::RIP, 0 }; 515 const unsigned ESI_SuperRegsSet[] = { X86::RSI, 0 }; 516 const unsigned ESP_SuperRegsSet[] = { X86::RSP, 0 }; 517 const unsigned IP_SuperRegsSet[] = { X86::EIP, X86::RIP, 0 }; 518 const unsigned R8B_SuperRegsSet[] = { X86::R8W, X86::R8D, X86::R8, 0 }; 519 const unsigned R8D_SuperRegsSet[] = { X86::R8, 0 }; 520 const unsigned R8W_SuperRegsSet[] = { X86::R8D, X86::R8, 0 }; 521 const unsigned R9B_SuperRegsSet[] = { X86::R9W, X86::R9D, X86::R9, 0 }; 522 const unsigned R9D_SuperRegsSet[] = { X86::R9, 0 }; 523 const unsigned R9W_SuperRegsSet[] = { X86::R9D, X86::R9, 0 }; 524 const unsigned R10B_SuperRegsSet[] = { X86::R10W, X86::R10D, X86::R10, 0 }; 525 const unsigned R10D_SuperRegsSet[] = { X86::R10, 0 }; 526 const unsigned R10W_SuperRegsSet[] = { X86::R10D, X86::R10, 0 }; 527 const unsigned R11B_SuperRegsSet[] = { X86::R11W, X86::R11D, X86::R11, 0 }; 528 const unsigned R11D_SuperRegsSet[] = { X86::R11, 0 }; 529 const unsigned R11W_SuperRegsSet[] = { X86::R11D, X86::R11, 0 }; 530 const unsigned R12B_SuperRegsSet[] = { X86::R12W, X86::R12D, X86::R12, 0 }; 531 const unsigned R12D_SuperRegsSet[] = { X86::R12, 0 }; 532 const unsigned R12W_SuperRegsSet[] = { X86::R12D, X86::R12, 0 }; 533 const unsigned R13B_SuperRegsSet[] = { X86::R13W, X86::R13D, X86::R13, 0 }; 534 const unsigned R13D_SuperRegsSet[] = { X86::R13, 0 }; 535 const unsigned R13W_SuperRegsSet[] = { X86::R13D, X86::R13, 0 }; 536 const unsigned R14B_SuperRegsSet[] = { X86::R14W, X86::R14D, X86::R14, 0 }; 537 const unsigned R14D_SuperRegsSet[] = { X86::R14, 0 }; 538 const unsigned R14W_SuperRegsSet[] = { X86::R14D, X86::R14, 0 }; 539 const unsigned R15B_SuperRegsSet[] = { X86::R15W, X86::R15D, X86::R15, 0 }; 540 const unsigned R15D_SuperRegsSet[] = { X86::R15, 0 }; 541 const unsigned R15W_SuperRegsSet[] = { X86::R15D, X86::R15, 0 }; 542 const unsigned SI_SuperRegsSet[] = { X86::ESI, X86::RSI, 0 }; 543 const unsigned SIL_SuperRegsSet[] = { X86::SI, X86::ESI, X86::RSI, 0 }; 544 const unsigned SP_SuperRegsSet[] = { X86::ESP, X86::RSP, 0 }; 545 const unsigned SPL_SuperRegsSet[] = { X86::SP, X86::ESP, X86::RSP, 0 }; 546 const unsigned XMM0_SuperRegsSet[] = { X86::YMM0, 0 }; 547 const unsigned XMM1_SuperRegsSet[] = { X86::YMM1, 0 }; 548 const unsigned XMM2_SuperRegsSet[] = { X86::YMM2, 0 }; 549 const unsigned XMM3_SuperRegsSet[] = { X86::YMM3, 0 }; 550 const unsigned XMM4_SuperRegsSet[] = { X86::YMM4, 0 }; 551 const unsigned XMM5_SuperRegsSet[] = { X86::YMM5, 0 }; 552 const unsigned XMM6_SuperRegsSet[] = { X86::YMM6, 0 }; 553 const unsigned XMM7_SuperRegsSet[] = { X86::YMM7, 0 }; 554 const unsigned XMM8_SuperRegsSet[] = { X86::YMM8, 0 }; 555 const unsigned XMM9_SuperRegsSet[] = { X86::YMM9, 0 }; 556 const unsigned XMM10_SuperRegsSet[] = { X86::YMM10, 0 }; 557 const unsigned XMM11_SuperRegsSet[] = { X86::YMM11, 0 }; 558 const unsigned XMM12_SuperRegsSet[] = { X86::YMM12, 0 }; 559 const unsigned XMM13_SuperRegsSet[] = { X86::YMM13, 0 }; 560 const unsigned XMM14_SuperRegsSet[] = { X86::YMM14, 0 }; 561 const unsigned XMM15_SuperRegsSet[] = { X86::YMM15, 0 }; 562} 563 564MCRegisterDesc X86RegDesc[] = { // Descriptors 565 { "NOREG", 0, 0, 0 }, 566 { "AH", AH_Overlaps, Empty_SubRegsSet, AH_SuperRegsSet }, 567 { "AL", AL_Overlaps, Empty_SubRegsSet, AL_SuperRegsSet }, 568 { "AX", AX_Overlaps, AX_SubRegsSet, AX_SuperRegsSet }, 569 { "BH", BH_Overlaps, Empty_SubRegsSet, BH_SuperRegsSet }, 570 { "BL", BL_Overlaps, Empty_SubRegsSet, BL_SuperRegsSet }, 571 { "BP", BP_Overlaps, BP_SubRegsSet, BP_SuperRegsSet }, 572 { "BPL", BPL_Overlaps, Empty_SubRegsSet, BPL_SuperRegsSet }, 573 { "BX", BX_Overlaps, BX_SubRegsSet, BX_SuperRegsSet }, 574 { "CH", CH_Overlaps, Empty_SubRegsSet, CH_SuperRegsSet }, 575 { "CL", CL_Overlaps, Empty_SubRegsSet, CL_SuperRegsSet }, 576 { "CR0", CR0_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 577 { "CR1", CR1_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 578 { "CR2", CR2_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 579 { "CR3", CR3_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 580 { "CR4", CR4_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 581 { "CR5", CR5_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 582 { "CR6", CR6_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 583 { "CR7", CR7_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 584 { "CR8", CR8_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 585 { "CR9", CR9_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 586 { "CR10", CR10_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 587 { "CR11", CR11_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 588 { "CR12", CR12_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 589 { "CR13", CR13_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 590 { "CR14", CR14_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 591 { "CR15", CR15_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 592 { "CS", CS_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 593 { "CX", CX_Overlaps, CX_SubRegsSet, CX_SuperRegsSet }, 594 { "DH", DH_Overlaps, Empty_SubRegsSet, DH_SuperRegsSet }, 595 { "DI", DI_Overlaps, DI_SubRegsSet, DI_SuperRegsSet }, 596 { "DIL", DIL_Overlaps, Empty_SubRegsSet, DIL_SuperRegsSet }, 597 { "DL", DL_Overlaps, Empty_SubRegsSet, DL_SuperRegsSet }, 598 { "DR0", DR0_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 599 { "DR1", DR1_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 600 { "DR2", DR2_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 601 { "DR3", DR3_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 602 { "DR4", DR4_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 603 { "DR5", DR5_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 604 { "DR6", DR6_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 605 { "DR7", DR7_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 606 { "DS", DS_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 607 { "DX", DX_Overlaps, DX_SubRegsSet, DX_SuperRegsSet }, 608 { "EAX", EAX_Overlaps, EAX_SubRegsSet, EAX_SuperRegsSet }, 609 { "EBP", EBP_Overlaps, EBP_SubRegsSet, EBP_SuperRegsSet }, 610 { "EBX", EBX_Overlaps, EBX_SubRegsSet, EBX_SuperRegsSet }, 611 { "ECX", ECX_Overlaps, ECX_SubRegsSet, ECX_SuperRegsSet }, 612 { "EDI", EDI_Overlaps, EDI_SubRegsSet, EDI_SuperRegsSet }, 613 { "EDX", EDX_Overlaps, EDX_SubRegsSet, EDX_SuperRegsSet }, 614 { "EFLAGS", EFLAGS_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 615 { "EIP", EIP_Overlaps, EIP_SubRegsSet, EIP_SuperRegsSet }, 616 { "EIZ", EIZ_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 617 { "ES", ES_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 618 { "ESI", ESI_Overlaps, ESI_SubRegsSet, ESI_SuperRegsSet }, 619 { "ESP", ESP_Overlaps, ESP_SubRegsSet, ESP_SuperRegsSet }, 620 { "FP0", FP0_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 621 { "FP1", FP1_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 622 { "FP2", FP2_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 623 { "FP3", FP3_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 624 { "FP4", FP4_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 625 { "FP5", FP5_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 626 { "FP6", FP6_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 627 { "FS", FS_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 628 { "GS", GS_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 629 { "IP", IP_Overlaps, Empty_SubRegsSet, IP_SuperRegsSet }, 630 { "MM0", MM0_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 631 { "MM1", MM1_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 632 { "MM2", MM2_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 633 { "MM3", MM3_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 634 { "MM4", MM4_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 635 { "MM5", MM5_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 636 { "MM6", MM6_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 637 { "MM7", MM7_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 638 { "R8", R8_Overlaps, R8_SubRegsSet, Empty_SuperRegsSet }, 639 { "R8B", R8B_Overlaps, Empty_SubRegsSet, R8B_SuperRegsSet }, 640 { "R8D", R8D_Overlaps, R8D_SubRegsSet, R8D_SuperRegsSet }, 641 { "R8W", R8W_Overlaps, R8W_SubRegsSet, R8W_SuperRegsSet }, 642 { "R9", R9_Overlaps, R9_SubRegsSet, Empty_SuperRegsSet }, 643 { "R9B", R9B_Overlaps, Empty_SubRegsSet, R9B_SuperRegsSet }, 644 { "R9D", R9D_Overlaps, R9D_SubRegsSet, R9D_SuperRegsSet }, 645 { "R9W", R9W_Overlaps, R9W_SubRegsSet, R9W_SuperRegsSet }, 646 { "R10", R10_Overlaps, R10_SubRegsSet, Empty_SuperRegsSet }, 647 { "R10B", R10B_Overlaps, Empty_SubRegsSet, R10B_SuperRegsSet }, 648 { "R10D", R10D_Overlaps, R10D_SubRegsSet, R10D_SuperRegsSet }, 649 { "R10W", R10W_Overlaps, R10W_SubRegsSet, R10W_SuperRegsSet }, 650 { "R11", R11_Overlaps, R11_SubRegsSet, Empty_SuperRegsSet }, 651 { "R11B", R11B_Overlaps, Empty_SubRegsSet, R11B_SuperRegsSet }, 652 { "R11D", R11D_Overlaps, R11D_SubRegsSet, R11D_SuperRegsSet }, 653 { "R11W", R11W_Overlaps, R11W_SubRegsSet, R11W_SuperRegsSet }, 654 { "R12", R12_Overlaps, R12_SubRegsSet, Empty_SuperRegsSet }, 655 { "R12B", R12B_Overlaps, Empty_SubRegsSet, R12B_SuperRegsSet }, 656 { "R12D", R12D_Overlaps, R12D_SubRegsSet, R12D_SuperRegsSet }, 657 { "R12W", R12W_Overlaps, R12W_SubRegsSet, R12W_SuperRegsSet }, 658 { "R13", R13_Overlaps, R13_SubRegsSet, Empty_SuperRegsSet }, 659 { "R13B", R13B_Overlaps, Empty_SubRegsSet, R13B_SuperRegsSet }, 660 { "R13D", R13D_Overlaps, R13D_SubRegsSet, R13D_SuperRegsSet }, 661 { "R13W", R13W_Overlaps, R13W_SubRegsSet, R13W_SuperRegsSet }, 662 { "R14", R14_Overlaps, R14_SubRegsSet, Empty_SuperRegsSet }, 663 { "R14B", R14B_Overlaps, Empty_SubRegsSet, R14B_SuperRegsSet }, 664 { "R14D", R14D_Overlaps, R14D_SubRegsSet, R14D_SuperRegsSet }, 665 { "R14W", R14W_Overlaps, R14W_SubRegsSet, R14W_SuperRegsSet }, 666 { "R15", R15_Overlaps, R15_SubRegsSet, Empty_SuperRegsSet }, 667 { "R15B", R15B_Overlaps, Empty_SubRegsSet, R15B_SuperRegsSet }, 668 { "R15D", R15D_Overlaps, R15D_SubRegsSet, R15D_SuperRegsSet }, 669 { "R15W", R15W_Overlaps, R15W_SubRegsSet, R15W_SuperRegsSet }, 670 { "RAX", RAX_Overlaps, RAX_SubRegsSet, Empty_SuperRegsSet }, 671 { "RBP", RBP_Overlaps, RBP_SubRegsSet, Empty_SuperRegsSet }, 672 { "RBX", RBX_Overlaps, RBX_SubRegsSet, Empty_SuperRegsSet }, 673 { "RCX", RCX_Overlaps, RCX_SubRegsSet, Empty_SuperRegsSet }, 674 { "RDI", RDI_Overlaps, RDI_SubRegsSet, Empty_SuperRegsSet }, 675 { "RDX", RDX_Overlaps, RDX_SubRegsSet, Empty_SuperRegsSet }, 676 { "RIP", RIP_Overlaps, RIP_SubRegsSet, Empty_SuperRegsSet }, 677 { "RIZ", RIZ_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 678 { "RSI", RSI_Overlaps, RSI_SubRegsSet, Empty_SuperRegsSet }, 679 { "RSP", RSP_Overlaps, RSP_SubRegsSet, Empty_SuperRegsSet }, 680 { "SI", SI_Overlaps, SI_SubRegsSet, SI_SuperRegsSet }, 681 { "SIL", SIL_Overlaps, Empty_SubRegsSet, SIL_SuperRegsSet }, 682 { "SP", SP_Overlaps, SP_SubRegsSet, SP_SuperRegsSet }, 683 { "SPL", SPL_Overlaps, Empty_SubRegsSet, SPL_SuperRegsSet }, 684 { "SS", SS_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 685 { "ST0", ST0_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 686 { "ST1", ST1_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 687 { "ST2", ST2_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 688 { "ST3", ST3_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 689 { "ST4", ST4_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 690 { "ST5", ST5_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 691 { "ST6", ST6_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 692 { "ST7", ST7_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet }, 693 { "XMM0", XMM0_Overlaps, XMM0_SubRegsSet, XMM0_SuperRegsSet }, 694 { "XMM1", XMM1_Overlaps, XMM1_SubRegsSet, XMM1_SuperRegsSet }, 695 { "XMM2", XMM2_Overlaps, XMM2_SubRegsSet, XMM2_SuperRegsSet }, 696 { "XMM3", XMM3_Overlaps, XMM3_SubRegsSet, XMM3_SuperRegsSet }, 697 { "XMM4", XMM4_Overlaps, XMM4_SubRegsSet, XMM4_SuperRegsSet }, 698 { "XMM5", XMM5_Overlaps, XMM5_SubRegsSet, XMM5_SuperRegsSet }, 699 { "XMM6", XMM6_Overlaps, XMM6_SubRegsSet, XMM6_SuperRegsSet }, 700 { "XMM7", XMM7_Overlaps, XMM7_SubRegsSet, XMM7_SuperRegsSet }, 701 { "XMM8", XMM8_Overlaps, XMM8_SubRegsSet, XMM8_SuperRegsSet }, 702 { "XMM9", XMM9_Overlaps, XMM9_SubRegsSet, XMM9_SuperRegsSet }, 703 { "XMM10", XMM10_Overlaps, XMM10_SubRegsSet, XMM10_SuperRegsSet }, 704 { "XMM11", XMM11_Overlaps, XMM11_SubRegsSet, XMM11_SuperRegsSet }, 705 { "XMM12", XMM12_Overlaps, XMM12_SubRegsSet, XMM12_SuperRegsSet }, 706 { "XMM13", XMM13_Overlaps, XMM13_SubRegsSet, XMM13_SuperRegsSet }, 707 { "XMM14", XMM14_Overlaps, XMM14_SubRegsSet, XMM14_SuperRegsSet }, 708 { "XMM15", XMM15_Overlaps, XMM15_SubRegsSet, XMM15_SuperRegsSet }, 709 { "YMM0", YMM0_Overlaps, YMM0_SubRegsSet, Empty_SuperRegsSet }, 710 { "YMM1", YMM1_Overlaps, YMM1_SubRegsSet, Empty_SuperRegsSet }, 711 { "YMM2", YMM2_Overlaps, YMM2_SubRegsSet, Empty_SuperRegsSet }, 712 { "YMM3", YMM3_Overlaps, YMM3_SubRegsSet, Empty_SuperRegsSet }, 713 { "YMM4", YMM4_Overlaps, YMM4_SubRegsSet, Empty_SuperRegsSet }, 714 { "YMM5", YMM5_Overlaps, YMM5_SubRegsSet, Empty_SuperRegsSet }, 715 { "YMM6", YMM6_Overlaps, YMM6_SubRegsSet, Empty_SuperRegsSet }, 716 { "YMM7", YMM7_Overlaps, YMM7_SubRegsSet, Empty_SuperRegsSet }, 717 { "YMM8", YMM8_Overlaps, YMM8_SubRegsSet, Empty_SuperRegsSet }, 718 { "YMM9", YMM9_Overlaps, YMM9_SubRegsSet, Empty_SuperRegsSet }, 719 { "YMM10", YMM10_Overlaps, YMM10_SubRegsSet, Empty_SuperRegsSet }, 720 { "YMM11", YMM11_Overlaps, YMM11_SubRegsSet, Empty_SuperRegsSet }, 721 { "YMM12", YMM12_Overlaps, YMM12_SubRegsSet, Empty_SuperRegsSet }, 722 { "YMM13", YMM13_Overlaps, YMM13_SubRegsSet, Empty_SuperRegsSet }, 723 { "YMM14", YMM14_Overlaps, YMM14_SubRegsSet, Empty_SuperRegsSet }, 724 { "YMM15", YMM15_Overlaps, YMM15_SubRegsSet, Empty_SuperRegsSet }, 725}; 726 727namespace { // Register classes... 728 // GR8 Register Class... 729 static const unsigned GR8[] = { 730 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, 731 }; 732 733 // GR8 Bit set. 734 static const unsigned char GR8Bits[] = { 735 0xb6, 0x06, 0x00, 0xa0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x44, 0x00, 0x50, 736 }; 737 738 // GR64 Register Class... 739 static const unsigned GR64[] = { 740 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP, 741 }; 742 743 // GR64 Bit set. 744 static const unsigned char GR64Bits[] = { 745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0xfe, 0x06, 746 }; 747 748 // GR16 Register Class... 749 static const unsigned GR16[] = { 750 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, 751 }; 752 753 // GR16 Bit set. 754 static const unsigned char GR16Bits[] = { 755 0x48, 0x01, 0x00, 0x50, 0x00, 0x04, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11, 0x01, 0x28, 756 }; 757 758 // GR32 Register Class... 759 static const unsigned GR32[] = { 760 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 761 }; 762 763 // GR32 Bit set. 764 static const unsigned char GR32Bits[] = { 765 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x61, 0x00, 0x00, 0x88, 0x88, 0x88, 0x88, 766 }; 767 768 // FR32 Register Class... 769 static const unsigned FR32[] = { 770 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 771 }; 772 773 // FR32 Bit set. 774 static const unsigned char FR32Bits[] = { 775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 776 }; 777 778 // GR64_with_sub_8bit Register Class... 779 static const unsigned GR64_with_sub_8bit[] = { 780 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, 781 }; 782 783 // GR64_with_sub_8bit Bit set. 784 static const unsigned char GR64_with_sub_8bitBits[] = { 785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x7e, 0x06, 786 }; 787 788 // FR64 Register Class... 789 static const unsigned FR64[] = { 790 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 791 }; 792 793 // FR64 Bit set. 794 static const unsigned char FR64Bits[] = { 795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 796 }; 797 798 // CONTROL_REG Register Class... 799 static const unsigned CONTROL_REG[] = { 800 X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15, 801 }; 802 803 // CONTROL_REG Bit set. 804 static const unsigned char CONTROL_REGBits[] = { 805 0x00, 0xf8, 0xff, 0x07, 806 }; 807 808 // VR128 Register Class... 809 static const unsigned VR128[] = { 810 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 811 }; 812 813 // VR128 Bit set. 814 static const unsigned char VR128Bits[] = { 815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 816 }; 817 818 // VR256 Register Class... 819 static const unsigned VR256[] = { 820 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 821 }; 822 823 // VR256 Bit set. 824 static const unsigned char VR256Bits[] = { 825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 826 }; 827 828 // GR32_NOSP Register Class... 829 static const unsigned GR32_NOSP[] = { 830 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 831 }; 832 833 // GR32_NOSP Bit set. 834 static const unsigned char GR32_NOSPBits[] = { 835 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x21, 0x00, 0x00, 0x88, 0x88, 0x88, 0x88, 836 }; 837 838 // GR32_NOAX Register Class... 839 static const unsigned GR32_NOAX[] = { 840 X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 841 }; 842 843 // GR32_NOAX Bit set. 844 static const unsigned char GR32_NOAXBits[] = { 845 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x61, 0x00, 0x00, 0x88, 0x88, 0x88, 0x88, 846 }; 847 848 // GR64_NOSP Register Class... 849 static const unsigned GR64_NOSP[] = { 850 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, 851 }; 852 853 // GR64_NOSP Bit set. 854 static const unsigned char GR64_NOSPBits[] = { 855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x7e, 0x02, 856 }; 857 858 // GR64_TC Register Class... 859 static const unsigned GR64_TC[] = { 860 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, 861 }; 862 863 // GR64_TC Bit set. 864 static const unsigned char GR64_TCBits[] = { 865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x20, 0x00, 0x00, 0xf2, 0x02, 866 }; 867 868 // GR64_NOREX Register Class... 869 static const unsigned GR64_NOREX[] = { 870 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP, 871 }; 872 873 // GR64_NOREX Bit set. 874 static const unsigned char GR64_NOREXBits[] = { 875 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x06, 876 }; 877 878 // GR8_NOREX Register Class... 879 static const unsigned GR8_NOREX[] = { 880 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, 881 }; 882 883 // GR8_NOREX Bit set. 884 static const unsigned char GR8_NOREXBits[] = { 885 0x36, 0x06, 0x00, 0x20, 0x01, 886 }; 887 888 // GR16_NOREX Register Class... 889 static const unsigned GR16_NOREX[] = { 890 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 891 }; 892 893 // GR16_NOREX Bit set. 894 static const unsigned char GR16_NOREXBits[] = { 895 0x48, 0x01, 0x00, 0x50, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 896 }; 897 898 // GR32_NOREX Register Class... 899 static const unsigned GR32_NOREX[] = { 900 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 901 }; 902 903 // GR32_NOREX Bit set. 904 static const unsigned char GR32_NOREXBits[] = { 905 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x61, 906 }; 907 908 // DEBUG_REG Register Class... 909 static const unsigned DEBUG_REG[] = { 910 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, 911 }; 912 913 // DEBUG_REG Bit set. 914 static const unsigned char DEBUG_REGBits[] = { 915 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 916 }; 917 918 // VR64 Register Class... 919 static const unsigned VR64[] = { 920 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, 921 }; 922 923 // VR64 Bit set. 924 static const unsigned char VR64Bits[] = { 925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 926 }; 927 928 // GR64_TC_with_sub_8bit Register Class... 929 static const unsigned GR64_TC_with_sub_8bit[] = { 930 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, 931 }; 932 933 // GR64_TC_with_sub_8bit Bit set. 934 static const unsigned char GR64_TC_with_sub_8bitBits[] = { 935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x20, 0x00, 0x00, 0x72, 0x02, 936 }; 937 938 // GR64_NOREX_with_sub_8bit Register Class... 939 static const unsigned GR64_NOREX_with_sub_8bit[] = { 940 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, 941 }; 942 943 // GR64_NOREX_with_sub_8bit Bit set. 944 static const unsigned char GR64_NOREX_with_sub_8bitBits[] = { 945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x06, 946 }; 947 948 // RST Register Class... 949 static const unsigned RST[] = { 950 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 951 }; 952 953 // RST Bit set. 954 static const unsigned char RSTBits[] = { 955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 956 }; 957 958 // RFP32 Register Class... 959 static const unsigned RFP32[] = { 960 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 961 }; 962 963 // RFP32 Bit set. 964 static const unsigned char RFP32Bits[] = { 965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 966 }; 967 968 // GR32_NOREX_NOSP Register Class... 969 static const unsigned GR32_NOREX_NOSP[] = { 970 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 971 }; 972 973 // GR32_NOREX_NOSP Bit set. 974 static const unsigned char GR32_NOREX_NOSPBits[] = { 975 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x21, 976 }; 977 978 // RFP64 Register Class... 979 static const unsigned RFP64[] = { 980 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 981 }; 982 983 // RFP64 Bit set. 984 static const unsigned char RFP64Bits[] = { 985 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 986 }; 987 988 // GR64_NOREX_NOSP Register Class... 989 static const unsigned GR64_NOREX_NOSP[] = { 990 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, 991 }; 992 993 // GR64_NOREX_NOSP Bit set. 994 static const unsigned char GR64_NOREX_NOSPBits[] = { 995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x02, 996 }; 997 998 // RFP80 Register Class... 999 static const unsigned RFP80[] = { 1000 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 1001 }; 1002 1003 // RFP80 Bit set. 1004 static const unsigned char RFP80Bits[] = { 1005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 1006 }; 1007 1008 // SEGMENT_REG Register Class... 1009 static const unsigned SEGMENT_REG[] = { 1010 X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS, 1011 }; 1012 1013 // SEGMENT_REG Bit set. 1014 static const unsigned char SEGMENT_REGBits[] = { 1015 0x00, 0x00, 0x00, 0x08, 0x00, 0x02, 0x10, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 1016 }; 1017 1018 // GR64_TCW64 Register Class... 1019 static const unsigned GR64_TCW64[] = { 1020 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, 1021 }; 1022 1023 // GR64_TCW64 Bit set. 1024 static const unsigned char GR64_TCW64Bits[] = { 1025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x20, 0x00, 0x00, 0x52, 1026 }; 1027 1028 // GR8_ABCD_L Register Class... 1029 static const unsigned GR8_ABCD_L[] = { 1030 X86::AL, X86::CL, X86::DL, X86::BL, 1031 }; 1032 1033 // GR8_ABCD_L Bit set. 1034 static const unsigned char GR8_ABCD_LBits[] = { 1035 0x24, 0x04, 0x00, 0x00, 0x01, 1036 }; 1037 1038 // GR8_ABCD_H Register Class... 1039 static const unsigned GR8_ABCD_H[] = { 1040 X86::AH, X86::CH, X86::DH, X86::BH, 1041 }; 1042 1043 // GR8_ABCD_H Bit set. 1044 static const unsigned char GR8_ABCD_HBits[] = { 1045 0x12, 0x02, 0x00, 0x20, 1046 }; 1047 1048 // GR16_ABCD Register Class... 1049 static const unsigned GR16_ABCD[] = { 1050 X86::AX, X86::CX, X86::DX, X86::BX, 1051 }; 1052 1053 // GR16_ABCD Bit set. 1054 static const unsigned char GR16_ABCDBits[] = { 1055 0x08, 0x01, 0x00, 0x10, 0x00, 0x04, 1056 }; 1057 1058 // GR32_ABCD Register Class... 1059 static const unsigned GR32_ABCD[] = { 1060 X86::EAX, X86::ECX, X86::EDX, X86::EBX, 1061 }; 1062 1063 // GR32_ABCD Bit set. 1064 static const unsigned char GR32_ABCDBits[] = { 1065 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x01, 1066 }; 1067 1068 // GR64_ABCD Register Class... 1069 static const unsigned GR64_ABCD[] = { 1070 X86::RAX, X86::RCX, X86::RDX, X86::RBX, 1071 }; 1072 1073 // GR64_ABCD Bit set. 1074 static const unsigned char GR64_ABCDBits[] = { 1075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5a, 1076 }; 1077 1078 // GR32_TC Register Class... 1079 static const unsigned GR32_TC[] = { 1080 X86::EAX, X86::ECX, X86::EDX, 1081 }; 1082 1083 // GR32_TC Bit set. 1084 static const unsigned char GR32_TCBits[] = { 1085 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 1086 }; 1087 1088 // GR32_NOAX_with_sub_8bit_hi Register Class... 1089 static const unsigned GR32_NOAX_with_sub_8bit_hi[] = { 1090 X86::ECX, X86::EDX, X86::EBX, 1091 }; 1092 1093 // GR32_NOAX_with_sub_8bit_hi Bit set. 1094 static const unsigned char GR32_NOAX_with_sub_8bit_hiBits[] = { 1095 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, 1096 }; 1097 1098 // GR64_TC_with_sub_8bit_hi Register Class... 1099 static const unsigned GR64_TC_with_sub_8bit_hi[] = { 1100 X86::RAX, X86::RCX, X86::RDX, 1101 }; 1102 1103 // GR64_TC_with_sub_8bit_hi Bit set. 1104 static const unsigned char GR64_TC_with_sub_8bit_hiBits[] = { 1105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 1106 }; 1107 1108 // GR32_AD Register Class... 1109 static const unsigned GR32_AD[] = { 1110 X86::EAX, X86::EDX, 1111 }; 1112 1113 // GR32_AD Bit set. 1114 static const unsigned char GR32_ADBits[] = { 1115 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 1116 }; 1117 1118 // CCR Register Class... 1119 static const unsigned CCR[] = { 1120 X86::EFLAGS, 1121 }; 1122 1123 // CCR Bit set. 1124 static const unsigned char CCRBits[] = { 1125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 1126 }; 1127 1128} 1129 1130MCRegisterClass X86MCRegisterClasses[] = { 1131 MCRegisterClass(X86::GR8RegClassID, "GR8", 1, 1, 1, 1, GR8, GR8 + 20, GR8Bits, sizeof(GR8Bits)), 1132 MCRegisterClass(X86::GR64RegClassID, "GR64", 8, 8, 1, 1, GR64, GR64 + 17, GR64Bits, sizeof(GR64Bits)), 1133 MCRegisterClass(X86::GR16RegClassID, "GR16", 2, 2, 1, 1, GR16, GR16 + 16, GR16Bits, sizeof(GR16Bits)), 1134 MCRegisterClass(X86::GR32RegClassID, "GR32", 4, 4, 1, 1, GR32, GR32 + 16, GR32Bits, sizeof(GR32Bits)), 1135 MCRegisterClass(X86::FR32RegClassID, "FR32", 4, 4, 1, 1, FR32, FR32 + 16, FR32Bits, sizeof(FR32Bits)), 1136 MCRegisterClass(X86::GR64_with_sub_8bitRegClassID, "GR64_with_sub_8bit", 8, 8, 1, 1, GR64_with_sub_8bit, GR64_with_sub_8bit + 16, GR64_with_sub_8bitBits, sizeof(GR64_with_sub_8bitBits)), 1137 MCRegisterClass(X86::FR64RegClassID, "FR64", 8, 8, 1, 1, FR64, FR64 + 16, FR64Bits, sizeof(FR64Bits)), 1138 MCRegisterClass(X86::CONTROL_REGRegClassID, "CONTROL_REG", 8, 8, 1, 1, CONTROL_REG, CONTROL_REG + 16, CONTROL_REGBits, sizeof(CONTROL_REGBits)), 1139 MCRegisterClass(X86::VR128RegClassID, "VR128", 16, 16, 1, 1, VR128, VR128 + 16, VR128Bits, sizeof(VR128Bits)), 1140 MCRegisterClass(X86::VR256RegClassID, "VR256", 32, 32, 1, 1, VR256, VR256 + 16, VR256Bits, sizeof(VR256Bits)), 1141 MCRegisterClass(X86::GR32_NOSPRegClassID, "GR32_NOSP", 4, 4, 1, 1, GR32_NOSP, GR32_NOSP + 15, GR32_NOSPBits, sizeof(GR32_NOSPBits)), 1142 MCRegisterClass(X86::GR32_NOAXRegClassID, "GR32_NOAX", 4, 4, 1, 1, GR32_NOAX, GR32_NOAX + 15, GR32_NOAXBits, sizeof(GR32_NOAXBits)), 1143 MCRegisterClass(X86::GR64_NOSPRegClassID, "GR64_NOSP", 8, 8, 1, 1, GR64_NOSP, GR64_NOSP + 15, GR64_NOSPBits, sizeof(GR64_NOSPBits)), 1144 MCRegisterClass(X86::GR64_TCRegClassID, "GR64_TC", 8, 8, 1, 1, GR64_TC, GR64_TC + 9, GR64_TCBits, sizeof(GR64_TCBits)), 1145 MCRegisterClass(X86::GR64_NOREXRegClassID, "GR64_NOREX", 8, 8, 1, 1, GR64_NOREX, GR64_NOREX + 9, GR64_NOREXBits, sizeof(GR64_NOREXBits)), 1146 MCRegisterClass(X86::GR8_NOREXRegClassID, "GR8_NOREX", 1, 1, 1, 1, GR8_NOREX, GR8_NOREX + 8, GR8_NOREXBits, sizeof(GR8_NOREXBits)), 1147 MCRegisterClass(X86::GR16_NOREXRegClassID, "GR16_NOREX", 2, 2, 1, 1, GR16_NOREX, GR16_NOREX + 8, GR16_NOREXBits, sizeof(GR16_NOREXBits)), 1148 MCRegisterClass(X86::GR32_NOREXRegClassID, "GR32_NOREX", 4, 4, 1, 1, GR32_NOREX, GR32_NOREX + 8, GR32_NOREXBits, sizeof(GR32_NOREXBits)), 1149 MCRegisterClass(X86::DEBUG_REGRegClassID, "DEBUG_REG", 4, 4, 1, 1, DEBUG_REG, DEBUG_REG + 8, DEBUG_REGBits, sizeof(DEBUG_REGBits)), 1150 MCRegisterClass(X86::VR64RegClassID, "VR64", 8, 8, 1, 1, VR64, VR64 + 8, VR64Bits, sizeof(VR64Bits)), 1151 MCRegisterClass(X86::GR64_TC_with_sub_8bitRegClassID, "GR64_TC_with_sub_8bit", 8, 8, 1, 1, GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bit + 8, GR64_TC_with_sub_8bitBits, sizeof(GR64_TC_with_sub_8bitBits)), 1152 MCRegisterClass(X86::GR64_NOREX_with_sub_8bitRegClassID, "GR64_NOREX_with_sub_8bit", 8, 8, 1, 1, GR64_NOREX_with_sub_8bit, GR64_NOREX_with_sub_8bit + 8, GR64_NOREX_with_sub_8bitBits, sizeof(GR64_NOREX_with_sub_8bitBits)), 1153 MCRegisterClass(X86::RSTRegClassID, "RST", 10, 4, 1, 0, RST, RST + 8, RSTBits, sizeof(RSTBits)), 1154 MCRegisterClass(X86::RFP32RegClassID, "RFP32", 4, 4, 1, 1, RFP32, RFP32 + 7, RFP32Bits, sizeof(RFP32Bits)), 1155 MCRegisterClass(X86::GR32_NOREX_NOSPRegClassID, "GR32_NOREX_NOSP", 4, 4, 1, 1, GR32_NOREX_NOSP, GR32_NOREX_NOSP + 7, GR32_NOREX_NOSPBits, sizeof(GR32_NOREX_NOSPBits)), 1156 MCRegisterClass(X86::RFP64RegClassID, "RFP64", 8, 4, 1, 1, RFP64, RFP64 + 7, RFP64Bits, sizeof(RFP64Bits)), 1157 MCRegisterClass(X86::GR64_NOREX_NOSPRegClassID, "GR64_NOREX_NOSP", 8, 8, 1, 1, GR64_NOREX_NOSP, GR64_NOREX_NOSP + 7, GR64_NOREX_NOSPBits, sizeof(GR64_NOREX_NOSPBits)), 1158 MCRegisterClass(X86::RFP80RegClassID, "RFP80", 10, 4, 1, 1, RFP80, RFP80 + 7, RFP80Bits, sizeof(RFP80Bits)), 1159 MCRegisterClass(X86::SEGMENT_REGRegClassID, "SEGMENT_REG", 2, 2, 1, 1, SEGMENT_REG, SEGMENT_REG + 6, SEGMENT_REGBits, sizeof(SEGMENT_REGBits)), 1160 MCRegisterClass(X86::GR64_TCW64RegClassID, "GR64_TCW64", 8, 8, 1, 1, GR64_TCW64, GR64_TCW64 + 6, GR64_TCW64Bits, sizeof(GR64_TCW64Bits)), 1161 MCRegisterClass(X86::GR8_ABCD_LRegClassID, "GR8_ABCD_L", 1, 1, 1, 1, GR8_ABCD_L, GR8_ABCD_L + 4, GR8_ABCD_LBits, sizeof(GR8_ABCD_LBits)), 1162 MCRegisterClass(X86::GR8_ABCD_HRegClassID, "GR8_ABCD_H", 1, 1, 1, 1, GR8_ABCD_H, GR8_ABCD_H + 4, GR8_ABCD_HBits, sizeof(GR8_ABCD_HBits)), 1163 MCRegisterClass(X86::GR16_ABCDRegClassID, "GR16_ABCD", 2, 2, 1, 1, GR16_ABCD, GR16_ABCD + 4, GR16_ABCDBits, sizeof(GR16_ABCDBits)), 1164 MCRegisterClass(X86::GR32_ABCDRegClassID, "GR32_ABCD", 4, 4, 1, 1, GR32_ABCD, GR32_ABCD + 4, GR32_ABCDBits, sizeof(GR32_ABCDBits)), 1165 MCRegisterClass(X86::GR64_ABCDRegClassID, "GR64_ABCD", 8, 8, 1, 1, GR64_ABCD, GR64_ABCD + 4, GR64_ABCDBits, sizeof(GR64_ABCDBits)), 1166 MCRegisterClass(X86::GR32_TCRegClassID, "GR32_TC", 4, 4, 1, 1, GR32_TC, GR32_TC + 3, GR32_TCBits, sizeof(GR32_TCBits)), 1167 MCRegisterClass(X86::GR32_NOAX_with_sub_8bit_hiRegClassID, "GR32_NOAX_with_sub_8bit_hi", 4, 4, 1, 1, GR32_NOAX_with_sub_8bit_hi, GR32_NOAX_with_sub_8bit_hi + 3, GR32_NOAX_with_sub_8bit_hiBits, sizeof(GR32_NOAX_with_sub_8bit_hiBits)), 1168 MCRegisterClass(X86::GR64_TC_with_sub_8bit_hiRegClassID, "GR64_TC_with_sub_8bit_hi", 8, 8, 1, 1, GR64_TC_with_sub_8bit_hi, GR64_TC_with_sub_8bit_hi + 3, GR64_TC_with_sub_8bit_hiBits, sizeof(GR64_TC_with_sub_8bit_hiBits)), 1169 MCRegisterClass(X86::GR32_ADRegClassID, "GR32_AD", 4, 4, 1, 1, GR32_AD, GR32_AD + 2, GR32_ADBits, sizeof(GR32_ADBits)), 1170 MCRegisterClass(X86::CCRRegClassID, "CCR", 4, 4, -1, 0, CCR, CCR + 1, CCRBits, sizeof(CCRBits)), 1171}; 1172 1173static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) { 1174 RI->InitMCRegisterInfo(X86RegDesc, 160, RA, X86MCRegisterClasses, 40); 1175 1176 switch (DwarfFlavour) { 1177 default: 1178 assert(0 && "Unknown DWARF flavour"); 1179 break; 1180 case 0: 1181 RI->mapDwarfRegToLLVMReg(41, X86::MM0, false ); 1182 RI->mapDwarfRegToLLVMReg(42, X86::MM1, false ); 1183 RI->mapDwarfRegToLLVMReg(43, X86::MM2, false ); 1184 RI->mapDwarfRegToLLVMReg(44, X86::MM3, false ); 1185 RI->mapDwarfRegToLLVMReg(45, X86::MM4, false ); 1186 RI->mapDwarfRegToLLVMReg(46, X86::MM5, false ); 1187 RI->mapDwarfRegToLLVMReg(47, X86::MM6, false ); 1188 RI->mapDwarfRegToLLVMReg(48, X86::MM7, false ); 1189 RI->mapDwarfRegToLLVMReg(8, X86::R8, false ); 1190 RI->mapDwarfRegToLLVMReg(9, X86::R9, false ); 1191 RI->mapDwarfRegToLLVMReg(10, X86::R10, false ); 1192 RI->mapDwarfRegToLLVMReg(11, X86::R11, false ); 1193 RI->mapDwarfRegToLLVMReg(12, X86::R12, false ); 1194 RI->mapDwarfRegToLLVMReg(13, X86::R13, false ); 1195 RI->mapDwarfRegToLLVMReg(14, X86::R14, false ); 1196 RI->mapDwarfRegToLLVMReg(15, X86::R15, false ); 1197 RI->mapDwarfRegToLLVMReg(0, X86::RAX, false ); 1198 RI->mapDwarfRegToLLVMReg(6, X86::RBP, false ); 1199 RI->mapDwarfRegToLLVMReg(3, X86::RBX, false ); 1200 RI->mapDwarfRegToLLVMReg(2, X86::RCX, false ); 1201 RI->mapDwarfRegToLLVMReg(5, X86::RDI, false ); 1202 RI->mapDwarfRegToLLVMReg(1, X86::RDX, false ); 1203 RI->mapDwarfRegToLLVMReg(16, X86::RIP, false ); 1204 RI->mapDwarfRegToLLVMReg(4, X86::RSI, false ); 1205 RI->mapDwarfRegToLLVMReg(7, X86::RSP, false ); 1206 RI->mapDwarfRegToLLVMReg(33, X86::ST0, false ); 1207 RI->mapDwarfRegToLLVMReg(34, X86::ST1, false ); 1208 RI->mapDwarfRegToLLVMReg(35, X86::ST2, false ); 1209 RI->mapDwarfRegToLLVMReg(36, X86::ST3, false ); 1210 RI->mapDwarfRegToLLVMReg(37, X86::ST4, false ); 1211 RI->mapDwarfRegToLLVMReg(38, X86::ST5, false ); 1212 RI->mapDwarfRegToLLVMReg(39, X86::ST6, false ); 1213 RI->mapDwarfRegToLLVMReg(40, X86::ST7, false ); 1214 RI->mapDwarfRegToLLVMReg(17, X86::XMM0, false ); 1215 RI->mapDwarfRegToLLVMReg(18, X86::XMM1, false ); 1216 RI->mapDwarfRegToLLVMReg(19, X86::XMM2, false ); 1217 RI->mapDwarfRegToLLVMReg(20, X86::XMM3, false ); 1218 RI->mapDwarfRegToLLVMReg(21, X86::XMM4, false ); 1219 RI->mapDwarfRegToLLVMReg(22, X86::XMM5, false ); 1220 RI->mapDwarfRegToLLVMReg(23, X86::XMM6, false ); 1221 RI->mapDwarfRegToLLVMReg(24, X86::XMM7, false ); 1222 RI->mapDwarfRegToLLVMReg(25, X86::XMM8, false ); 1223 RI->mapDwarfRegToLLVMReg(26, X86::XMM9, false ); 1224 RI->mapDwarfRegToLLVMReg(27, X86::XMM10, false ); 1225 RI->mapDwarfRegToLLVMReg(28, X86::XMM11, false ); 1226 RI->mapDwarfRegToLLVMReg(29, X86::XMM12, false ); 1227 RI->mapDwarfRegToLLVMReg(30, X86::XMM13, false ); 1228 RI->mapDwarfRegToLLVMReg(31, X86::XMM14, false ); 1229 RI->mapDwarfRegToLLVMReg(32, X86::XMM15, false ); 1230 break; 1231 case 1: 1232 RI->mapDwarfRegToLLVMReg(0, X86::EAX, false ); 1233 RI->mapDwarfRegToLLVMReg(4, X86::EBP, false ); 1234 RI->mapDwarfRegToLLVMReg(3, X86::EBX, false ); 1235 RI->mapDwarfRegToLLVMReg(1, X86::ECX, false ); 1236 RI->mapDwarfRegToLLVMReg(7, X86::EDI, false ); 1237 RI->mapDwarfRegToLLVMReg(2, X86::EDX, false ); 1238 RI->mapDwarfRegToLLVMReg(8, X86::EIP, false ); 1239 RI->mapDwarfRegToLLVMReg(6, X86::ESI, false ); 1240 RI->mapDwarfRegToLLVMReg(5, X86::ESP, false ); 1241 RI->mapDwarfRegToLLVMReg(29, X86::MM0, false ); 1242 RI->mapDwarfRegToLLVMReg(30, X86::MM1, false ); 1243 RI->mapDwarfRegToLLVMReg(31, X86::MM2, false ); 1244 RI->mapDwarfRegToLLVMReg(32, X86::MM3, false ); 1245 RI->mapDwarfRegToLLVMReg(33, X86::MM4, false ); 1246 RI->mapDwarfRegToLLVMReg(34, X86::MM5, false ); 1247 RI->mapDwarfRegToLLVMReg(35, X86::MM6, false ); 1248 RI->mapDwarfRegToLLVMReg(36, X86::MM7, false ); 1249 RI->mapDwarfRegToLLVMReg(12, X86::ST0, false ); 1250 RI->mapDwarfRegToLLVMReg(13, X86::ST1, false ); 1251 RI->mapDwarfRegToLLVMReg(14, X86::ST2, false ); 1252 RI->mapDwarfRegToLLVMReg(15, X86::ST3, false ); 1253 RI->mapDwarfRegToLLVMReg(16, X86::ST4, false ); 1254 RI->mapDwarfRegToLLVMReg(17, X86::ST5, false ); 1255 RI->mapDwarfRegToLLVMReg(18, X86::ST6, false ); 1256 RI->mapDwarfRegToLLVMReg(19, X86::ST7, false ); 1257 RI->mapDwarfRegToLLVMReg(21, X86::XMM0, false ); 1258 RI->mapDwarfRegToLLVMReg(22, X86::XMM1, false ); 1259 RI->mapDwarfRegToLLVMReg(23, X86::XMM2, false ); 1260 RI->mapDwarfRegToLLVMReg(24, X86::XMM3, false ); 1261 RI->mapDwarfRegToLLVMReg(25, X86::XMM4, false ); 1262 RI->mapDwarfRegToLLVMReg(26, X86::XMM5, false ); 1263 RI->mapDwarfRegToLLVMReg(27, X86::XMM6, false ); 1264 RI->mapDwarfRegToLLVMReg(28, X86::XMM7, false ); 1265 break; 1266 case 2: 1267 RI->mapDwarfRegToLLVMReg(0, X86::EAX, false ); 1268 RI->mapDwarfRegToLLVMReg(5, X86::EBP, false ); 1269 RI->mapDwarfRegToLLVMReg(3, X86::EBX, false ); 1270 RI->mapDwarfRegToLLVMReg(1, X86::ECX, false ); 1271 RI->mapDwarfRegToLLVMReg(7, X86::EDI, false ); 1272 RI->mapDwarfRegToLLVMReg(2, X86::EDX, false ); 1273 RI->mapDwarfRegToLLVMReg(8, X86::EIP, false ); 1274 RI->mapDwarfRegToLLVMReg(6, X86::ESI, false ); 1275 RI->mapDwarfRegToLLVMReg(4, X86::ESP, false ); 1276 RI->mapDwarfRegToLLVMReg(29, X86::MM0, false ); 1277 RI->mapDwarfRegToLLVMReg(30, X86::MM1, false ); 1278 RI->mapDwarfRegToLLVMReg(31, X86::MM2, false ); 1279 RI->mapDwarfRegToLLVMReg(32, X86::MM3, false ); 1280 RI->mapDwarfRegToLLVMReg(33, X86::MM4, false ); 1281 RI->mapDwarfRegToLLVMReg(34, X86::MM5, false ); 1282 RI->mapDwarfRegToLLVMReg(35, X86::MM6, false ); 1283 RI->mapDwarfRegToLLVMReg(36, X86::MM7, false ); 1284 RI->mapDwarfRegToLLVMReg(11, X86::ST0, false ); 1285 RI->mapDwarfRegToLLVMReg(12, X86::ST1, false ); 1286 RI->mapDwarfRegToLLVMReg(13, X86::ST2, false ); 1287 RI->mapDwarfRegToLLVMReg(14, X86::ST3, false ); 1288 RI->mapDwarfRegToLLVMReg(15, X86::ST4, false ); 1289 RI->mapDwarfRegToLLVMReg(16, X86::ST5, false ); 1290 RI->mapDwarfRegToLLVMReg(17, X86::ST6, false ); 1291 RI->mapDwarfRegToLLVMReg(18, X86::ST7, false ); 1292 RI->mapDwarfRegToLLVMReg(21, X86::XMM0, false ); 1293 RI->mapDwarfRegToLLVMReg(22, X86::XMM1, false ); 1294 RI->mapDwarfRegToLLVMReg(23, X86::XMM2, false ); 1295 RI->mapDwarfRegToLLVMReg(24, X86::XMM3, false ); 1296 RI->mapDwarfRegToLLVMReg(25, X86::XMM4, false ); 1297 RI->mapDwarfRegToLLVMReg(26, X86::XMM5, false ); 1298 RI->mapDwarfRegToLLVMReg(27, X86::XMM6, false ); 1299 RI->mapDwarfRegToLLVMReg(28, X86::XMM7, false ); 1300 break; 1301 } 1302 switch (EHFlavour) { 1303 default: 1304 assert(0 && "Unknown DWARF flavour"); 1305 break; 1306 case 0: 1307 RI->mapDwarfRegToLLVMReg(41, X86::MM0, true ); 1308 RI->mapDwarfRegToLLVMReg(42, X86::MM1, true ); 1309 RI->mapDwarfRegToLLVMReg(43, X86::MM2, true ); 1310 RI->mapDwarfRegToLLVMReg(44, X86::MM3, true ); 1311 RI->mapDwarfRegToLLVMReg(45, X86::MM4, true ); 1312 RI->mapDwarfRegToLLVMReg(46, X86::MM5, true ); 1313 RI->mapDwarfRegToLLVMReg(47, X86::MM6, true ); 1314 RI->mapDwarfRegToLLVMReg(48, X86::MM7, true ); 1315 RI->mapDwarfRegToLLVMReg(8, X86::R8, true ); 1316 RI->mapDwarfRegToLLVMReg(9, X86::R9, true ); 1317 RI->mapDwarfRegToLLVMReg(10, X86::R10, true ); 1318 RI->mapDwarfRegToLLVMReg(11, X86::R11, true ); 1319 RI->mapDwarfRegToLLVMReg(12, X86::R12, true ); 1320 RI->mapDwarfRegToLLVMReg(13, X86::R13, true ); 1321 RI->mapDwarfRegToLLVMReg(14, X86::R14, true ); 1322 RI->mapDwarfRegToLLVMReg(15, X86::R15, true ); 1323 RI->mapDwarfRegToLLVMReg(0, X86::RAX, true ); 1324 RI->mapDwarfRegToLLVMReg(6, X86::RBP, true ); 1325 RI->mapDwarfRegToLLVMReg(3, X86::RBX, true ); 1326 RI->mapDwarfRegToLLVMReg(2, X86::RCX, true ); 1327 RI->mapDwarfRegToLLVMReg(5, X86::RDI, true ); 1328 RI->mapDwarfRegToLLVMReg(1, X86::RDX, true ); 1329 RI->mapDwarfRegToLLVMReg(16, X86::RIP, true ); 1330 RI->mapDwarfRegToLLVMReg(4, X86::RSI, true ); 1331 RI->mapDwarfRegToLLVMReg(7, X86::RSP, true ); 1332 RI->mapDwarfRegToLLVMReg(33, X86::ST0, true ); 1333 RI->mapDwarfRegToLLVMReg(34, X86::ST1, true ); 1334 RI->mapDwarfRegToLLVMReg(35, X86::ST2, true ); 1335 RI->mapDwarfRegToLLVMReg(36, X86::ST3, true ); 1336 RI->mapDwarfRegToLLVMReg(37, X86::ST4, true ); 1337 RI->mapDwarfRegToLLVMReg(38, X86::ST5, true ); 1338 RI->mapDwarfRegToLLVMReg(39, X86::ST6, true ); 1339 RI->mapDwarfRegToLLVMReg(40, X86::ST7, true ); 1340 RI->mapDwarfRegToLLVMReg(17, X86::XMM0, true ); 1341 RI->mapDwarfRegToLLVMReg(18, X86::XMM1, true ); 1342 RI->mapDwarfRegToLLVMReg(19, X86::XMM2, true ); 1343 RI->mapDwarfRegToLLVMReg(20, X86::XMM3, true ); 1344 RI->mapDwarfRegToLLVMReg(21, X86::XMM4, true ); 1345 RI->mapDwarfRegToLLVMReg(22, X86::XMM5, true ); 1346 RI->mapDwarfRegToLLVMReg(23, X86::XMM6, true ); 1347 RI->mapDwarfRegToLLVMReg(24, X86::XMM7, true ); 1348 RI->mapDwarfRegToLLVMReg(25, X86::XMM8, true ); 1349 RI->mapDwarfRegToLLVMReg(26, X86::XMM9, true ); 1350 RI->mapDwarfRegToLLVMReg(27, X86::XMM10, true ); 1351 RI->mapDwarfRegToLLVMReg(28, X86::XMM11, true ); 1352 RI->mapDwarfRegToLLVMReg(29, X86::XMM12, true ); 1353 RI->mapDwarfRegToLLVMReg(30, X86::XMM13, true ); 1354 RI->mapDwarfRegToLLVMReg(31, X86::XMM14, true ); 1355 RI->mapDwarfRegToLLVMReg(32, X86::XMM15, true ); 1356 break; 1357 case 1: 1358 RI->mapDwarfRegToLLVMReg(0, X86::EAX, true ); 1359 RI->mapDwarfRegToLLVMReg(4, X86::EBP, true ); 1360 RI->mapDwarfRegToLLVMReg(3, X86::EBX, true ); 1361 RI->mapDwarfRegToLLVMReg(1, X86::ECX, true ); 1362 RI->mapDwarfRegToLLVMReg(7, X86::EDI, true ); 1363 RI->mapDwarfRegToLLVMReg(2, X86::EDX, true ); 1364 RI->mapDwarfRegToLLVMReg(8, X86::EIP, true ); 1365 RI->mapDwarfRegToLLVMReg(6, X86::ESI, true ); 1366 RI->mapDwarfRegToLLVMReg(5, X86::ESP, true ); 1367 RI->mapDwarfRegToLLVMReg(29, X86::MM0, true ); 1368 RI->mapDwarfRegToLLVMReg(30, X86::MM1, true ); 1369 RI->mapDwarfRegToLLVMReg(31, X86::MM2, true ); 1370 RI->mapDwarfRegToLLVMReg(32, X86::MM3, true ); 1371 RI->mapDwarfRegToLLVMReg(33, X86::MM4, true ); 1372 RI->mapDwarfRegToLLVMReg(34, X86::MM5, true ); 1373 RI->mapDwarfRegToLLVMReg(35, X86::MM6, true ); 1374 RI->mapDwarfRegToLLVMReg(36, X86::MM7, true ); 1375 RI->mapDwarfRegToLLVMReg(12, X86::ST0, true ); 1376 RI->mapDwarfRegToLLVMReg(13, X86::ST1, true ); 1377 RI->mapDwarfRegToLLVMReg(14, X86::ST2, true ); 1378 RI->mapDwarfRegToLLVMReg(15, X86::ST3, true ); 1379 RI->mapDwarfRegToLLVMReg(16, X86::ST4, true ); 1380 RI->mapDwarfRegToLLVMReg(17, X86::ST5, true ); 1381 RI->mapDwarfRegToLLVMReg(18, X86::ST6, true ); 1382 RI->mapDwarfRegToLLVMReg(19, X86::ST7, true ); 1383 RI->mapDwarfRegToLLVMReg(21, X86::XMM0, true ); 1384 RI->mapDwarfRegToLLVMReg(22, X86::XMM1, true ); 1385 RI->mapDwarfRegToLLVMReg(23, X86::XMM2, true ); 1386 RI->mapDwarfRegToLLVMReg(24, X86::XMM3, true ); 1387 RI->mapDwarfRegToLLVMReg(25, X86::XMM4, true ); 1388 RI->mapDwarfRegToLLVMReg(26, X86::XMM5, true ); 1389 RI->mapDwarfRegToLLVMReg(27, X86::XMM6, true ); 1390 RI->mapDwarfRegToLLVMReg(28, X86::XMM7, true ); 1391 break; 1392 case 2: 1393 RI->mapDwarfRegToLLVMReg(0, X86::EAX, true ); 1394 RI->mapDwarfRegToLLVMReg(5, X86::EBP, true ); 1395 RI->mapDwarfRegToLLVMReg(3, X86::EBX, true ); 1396 RI->mapDwarfRegToLLVMReg(1, X86::ECX, true ); 1397 RI->mapDwarfRegToLLVMReg(7, X86::EDI, true ); 1398 RI->mapDwarfRegToLLVMReg(2, X86::EDX, true ); 1399 RI->mapDwarfRegToLLVMReg(8, X86::EIP, true ); 1400 RI->mapDwarfRegToLLVMReg(6, X86::ESI, true ); 1401 RI->mapDwarfRegToLLVMReg(4, X86::ESP, true ); 1402 RI->mapDwarfRegToLLVMReg(29, X86::MM0, true ); 1403 RI->mapDwarfRegToLLVMReg(30, X86::MM1, true ); 1404 RI->mapDwarfRegToLLVMReg(31, X86::MM2, true ); 1405 RI->mapDwarfRegToLLVMReg(32, X86::MM3, true ); 1406 RI->mapDwarfRegToLLVMReg(33, X86::MM4, true ); 1407 RI->mapDwarfRegToLLVMReg(34, X86::MM5, true ); 1408 RI->mapDwarfRegToLLVMReg(35, X86::MM6, true ); 1409 RI->mapDwarfRegToLLVMReg(36, X86::MM7, true ); 1410 RI->mapDwarfRegToLLVMReg(11, X86::ST0, true ); 1411 RI->mapDwarfRegToLLVMReg(12, X86::ST1, true ); 1412 RI->mapDwarfRegToLLVMReg(13, X86::ST2, true ); 1413 RI->mapDwarfRegToLLVMReg(14, X86::ST3, true ); 1414 RI->mapDwarfRegToLLVMReg(15, X86::ST4, true ); 1415 RI->mapDwarfRegToLLVMReg(16, X86::ST5, true ); 1416 RI->mapDwarfRegToLLVMReg(17, X86::ST6, true ); 1417 RI->mapDwarfRegToLLVMReg(18, X86::ST7, true ); 1418 RI->mapDwarfRegToLLVMReg(21, X86::XMM0, true ); 1419 RI->mapDwarfRegToLLVMReg(22, X86::XMM1, true ); 1420 RI->mapDwarfRegToLLVMReg(23, X86::XMM2, true ); 1421 RI->mapDwarfRegToLLVMReg(24, X86::XMM3, true ); 1422 RI->mapDwarfRegToLLVMReg(25, X86::XMM4, true ); 1423 RI->mapDwarfRegToLLVMReg(26, X86::XMM5, true ); 1424 RI->mapDwarfRegToLLVMReg(27, X86::XMM6, true ); 1425 RI->mapDwarfRegToLLVMReg(28, X86::XMM7, true ); 1426 break; 1427 } 1428 switch (DwarfFlavour) { 1429 default: 1430 assert(0 && "Unknown DWARF flavour"); 1431 break; 1432 case 0: 1433 RI->mapLLVMRegToDwarfReg(X86::AH, -1, false ); 1434 RI->mapLLVMRegToDwarfReg(X86::AL, -1, false ); 1435 RI->mapLLVMRegToDwarfReg(X86::AX, -1, false ); 1436 RI->mapLLVMRegToDwarfReg(X86::BH, -1, false ); 1437 RI->mapLLVMRegToDwarfReg(X86::BL, -1, false ); 1438 RI->mapLLVMRegToDwarfReg(X86::BP, -1, false ); 1439 RI->mapLLVMRegToDwarfReg(X86::BPL, -1, false ); 1440 RI->mapLLVMRegToDwarfReg(X86::BX, -1, false ); 1441 RI->mapLLVMRegToDwarfReg(X86::CH, -1, false ); 1442 RI->mapLLVMRegToDwarfReg(X86::CL, -1, false ); 1443 RI->mapLLVMRegToDwarfReg(X86::CR0, -1, false ); 1444 RI->mapLLVMRegToDwarfReg(X86::CR1, -1, false ); 1445 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, false ); 1446 RI->mapLLVMRegToDwarfReg(X86::CR3, -1, false ); 1447 RI->mapLLVMRegToDwarfReg(X86::CR4, -1, false ); 1448 RI->mapLLVMRegToDwarfReg(X86::CR5, -1, false ); 1449 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, false ); 1450 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, false ); 1451 RI->mapLLVMRegToDwarfReg(X86::CR8, -1, false ); 1452 RI->mapLLVMRegToDwarfReg(X86::CR9, -1, false ); 1453 RI->mapLLVMRegToDwarfReg(X86::CR10, -1, false ); 1454 RI->mapLLVMRegToDwarfReg(X86::CR11, -1, false ); 1455 RI->mapLLVMRegToDwarfReg(X86::CR12, -1, false ); 1456 RI->mapLLVMRegToDwarfReg(X86::CR13, -1, false ); 1457 RI->mapLLVMRegToDwarfReg(X86::CR14, -1, false ); 1458 RI->mapLLVMRegToDwarfReg(X86::CR15, -1, false ); 1459 RI->mapLLVMRegToDwarfReg(X86::CS, -1, false ); 1460 RI->mapLLVMRegToDwarfReg(X86::CX, -1, false ); 1461 RI->mapLLVMRegToDwarfReg(X86::DH, -1, false ); 1462 RI->mapLLVMRegToDwarfReg(X86::DI, -1, false ); 1463 RI->mapLLVMRegToDwarfReg(X86::DIL, -1, false ); 1464 RI->mapLLVMRegToDwarfReg(X86::DL, -1, false ); 1465 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, false ); 1466 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, false ); 1467 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, false ); 1468 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, false ); 1469 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, false ); 1470 RI->mapLLVMRegToDwarfReg(X86::DR5, -1, false ); 1471 RI->mapLLVMRegToDwarfReg(X86::DR6, -1, false ); 1472 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, false ); 1473 RI->mapLLVMRegToDwarfReg(X86::DS, -1, false ); 1474 RI->mapLLVMRegToDwarfReg(X86::DX, -1, false ); 1475 RI->mapLLVMRegToDwarfReg(X86::EAX, -2, false ); 1476 RI->mapLLVMRegToDwarfReg(X86::EBP, -2, false ); 1477 RI->mapLLVMRegToDwarfReg(X86::EBX, -2, false ); 1478 RI->mapLLVMRegToDwarfReg(X86::ECX, -2, false ); 1479 RI->mapLLVMRegToDwarfReg(X86::EDI, -2, false ); 1480 RI->mapLLVMRegToDwarfReg(X86::EDX, -2, false ); 1481 RI->mapLLVMRegToDwarfReg(X86::EFLAGS, -1, false ); 1482 RI->mapLLVMRegToDwarfReg(X86::EIP, -2, false ); 1483 RI->mapLLVMRegToDwarfReg(X86::EIZ, -1, false ); 1484 RI->mapLLVMRegToDwarfReg(X86::ES, -1, false ); 1485 RI->mapLLVMRegToDwarfReg(X86::ESI, -2, false ); 1486 RI->mapLLVMRegToDwarfReg(X86::ESP, -2, false ); 1487 RI->mapLLVMRegToDwarfReg(X86::FP0, -1, false ); 1488 RI->mapLLVMRegToDwarfReg(X86::FP1, -1, false ); 1489 RI->mapLLVMRegToDwarfReg(X86::FP2, -1, false ); 1490 RI->mapLLVMRegToDwarfReg(X86::FP3, -1, false ); 1491 RI->mapLLVMRegToDwarfReg(X86::FP4, -1, false ); 1492 RI->mapLLVMRegToDwarfReg(X86::FP5, -1, false ); 1493 RI->mapLLVMRegToDwarfReg(X86::FP6, -1, false ); 1494 RI->mapLLVMRegToDwarfReg(X86::FS, -1, false ); 1495 RI->mapLLVMRegToDwarfReg(X86::GS, -1, false ); 1496 RI->mapLLVMRegToDwarfReg(X86::IP, -1, false ); 1497 RI->mapLLVMRegToDwarfReg(X86::MM0, 41, false ); 1498 RI->mapLLVMRegToDwarfReg(X86::MM1, 42, false ); 1499 RI->mapLLVMRegToDwarfReg(X86::MM2, 43, false ); 1500 RI->mapLLVMRegToDwarfReg(X86::MM3, 44, false ); 1501 RI->mapLLVMRegToDwarfReg(X86::MM4, 45, false ); 1502 RI->mapLLVMRegToDwarfReg(X86::MM5, 46, false ); 1503 RI->mapLLVMRegToDwarfReg(X86::MM6, 47, false ); 1504 RI->mapLLVMRegToDwarfReg(X86::MM7, 48, false ); 1505 RI->mapLLVMRegToDwarfReg(X86::R8, 8, false ); 1506 RI->mapLLVMRegToDwarfReg(X86::R8B, -1, false ); 1507 RI->mapLLVMRegToDwarfReg(X86::R8D, -1, false ); 1508 RI->mapLLVMRegToDwarfReg(X86::R8W, -1, false ); 1509 RI->mapLLVMRegToDwarfReg(X86::R9, 9, false ); 1510 RI->mapLLVMRegToDwarfReg(X86::R9B, -1, false ); 1511 RI->mapLLVMRegToDwarfReg(X86::R9D, -1, false ); 1512 RI->mapLLVMRegToDwarfReg(X86::R9W, -1, false ); 1513 RI->mapLLVMRegToDwarfReg(X86::R10, 10, false ); 1514 RI->mapLLVMRegToDwarfReg(X86::R10B, -1, false ); 1515 RI->mapLLVMRegToDwarfReg(X86::R10D, -1, false ); 1516 RI->mapLLVMRegToDwarfReg(X86::R10W, -1, false ); 1517 RI->mapLLVMRegToDwarfReg(X86::R11, 11, false ); 1518 RI->mapLLVMRegToDwarfReg(X86::R11B, -1, false ); 1519 RI->mapLLVMRegToDwarfReg(X86::R11D, -1, false ); 1520 RI->mapLLVMRegToDwarfReg(X86::R11W, -1, false ); 1521 RI->mapLLVMRegToDwarfReg(X86::R12, 12, false ); 1522 RI->mapLLVMRegToDwarfReg(X86::R12B, -1, false ); 1523 RI->mapLLVMRegToDwarfReg(X86::R12D, -1, false ); 1524 RI->mapLLVMRegToDwarfReg(X86::R12W, -1, false ); 1525 RI->mapLLVMRegToDwarfReg(X86::R13, 13, false ); 1526 RI->mapLLVMRegToDwarfReg(X86::R13B, -1, false ); 1527 RI->mapLLVMRegToDwarfReg(X86::R13D, -1, false ); 1528 RI->mapLLVMRegToDwarfReg(X86::R13W, -1, false ); 1529 RI->mapLLVMRegToDwarfReg(X86::R14, 14, false ); 1530 RI->mapLLVMRegToDwarfReg(X86::R14B, -1, false ); 1531 RI->mapLLVMRegToDwarfReg(X86::R14D, -1, false ); 1532 RI->mapLLVMRegToDwarfReg(X86::R14W, -1, false ); 1533 RI->mapLLVMRegToDwarfReg(X86::R15, 15, false ); 1534 RI->mapLLVMRegToDwarfReg(X86::R15B, -1, false ); 1535 RI->mapLLVMRegToDwarfReg(X86::R15D, -1, false ); 1536 RI->mapLLVMRegToDwarfReg(X86::R15W, -1, false ); 1537 RI->mapLLVMRegToDwarfReg(X86::RAX, 0, false ); 1538 RI->mapLLVMRegToDwarfReg(X86::RBP, 6, false ); 1539 RI->mapLLVMRegToDwarfReg(X86::RBX, 3, false ); 1540 RI->mapLLVMRegToDwarfReg(X86::RCX, 2, false ); 1541 RI->mapLLVMRegToDwarfReg(X86::RDI, 5, false ); 1542 RI->mapLLVMRegToDwarfReg(X86::RDX, 1, false ); 1543 RI->mapLLVMRegToDwarfReg(X86::RIP, 16, false ); 1544 RI->mapLLVMRegToDwarfReg(X86::RIZ, -1, false ); 1545 RI->mapLLVMRegToDwarfReg(X86::RSI, 4, false ); 1546 RI->mapLLVMRegToDwarfReg(X86::RSP, 7, false ); 1547 RI->mapLLVMRegToDwarfReg(X86::SI, -1, false ); 1548 RI->mapLLVMRegToDwarfReg(X86::SIL, -1, false ); 1549 RI->mapLLVMRegToDwarfReg(X86::SP, -1, false ); 1550 RI->mapLLVMRegToDwarfReg(X86::SPL, -1, false ); 1551 RI->mapLLVMRegToDwarfReg(X86::SS, -1, false ); 1552 RI->mapLLVMRegToDwarfReg(X86::ST0, 33, false ); 1553 RI->mapLLVMRegToDwarfReg(X86::ST1, 34, false ); 1554 RI->mapLLVMRegToDwarfReg(X86::ST2, 35, false ); 1555 RI->mapLLVMRegToDwarfReg(X86::ST3, 36, false ); 1556 RI->mapLLVMRegToDwarfReg(X86::ST4, 37, false ); 1557 RI->mapLLVMRegToDwarfReg(X86::ST5, 38, false ); 1558 RI->mapLLVMRegToDwarfReg(X86::ST6, 39, false ); 1559 RI->mapLLVMRegToDwarfReg(X86::ST7, 40, false ); 1560 RI->mapLLVMRegToDwarfReg(X86::XMM0, 17, false ); 1561 RI->mapLLVMRegToDwarfReg(X86::XMM1, 18, false ); 1562 RI->mapLLVMRegToDwarfReg(X86::XMM2, 19, false ); 1563 RI->mapLLVMRegToDwarfReg(X86::XMM3, 20, false ); 1564 RI->mapLLVMRegToDwarfReg(X86::XMM4, 21, false ); 1565 RI->mapLLVMRegToDwarfReg(X86::XMM5, 22, false ); 1566 RI->mapLLVMRegToDwarfReg(X86::XMM6, 23, false ); 1567 RI->mapLLVMRegToDwarfReg(X86::XMM7, 24, false ); 1568 RI->mapLLVMRegToDwarfReg(X86::XMM8, 25, false ); 1569 RI->mapLLVMRegToDwarfReg(X86::XMM9, 26, false ); 1570 RI->mapLLVMRegToDwarfReg(X86::XMM10, 27, false ); 1571 RI->mapLLVMRegToDwarfReg(X86::XMM11, 28, false ); 1572 RI->mapLLVMRegToDwarfReg(X86::XMM12, 29, false ); 1573 RI->mapLLVMRegToDwarfReg(X86::XMM13, 30, false ); 1574 RI->mapLLVMRegToDwarfReg(X86::XMM14, 31, false ); 1575 RI->mapLLVMRegToDwarfReg(X86::XMM15, 32, false ); 1576 RI->mapLLVMRegToDwarfReg(X86::YMM0, 17, false ); 1577 RI->mapLLVMRegToDwarfReg(X86::YMM1, 18, false ); 1578 RI->mapLLVMRegToDwarfReg(X86::YMM2, 19, false ); 1579 RI->mapLLVMRegToDwarfReg(X86::YMM3, 20, false ); 1580 RI->mapLLVMRegToDwarfReg(X86::YMM4, 21, false ); 1581 RI->mapLLVMRegToDwarfReg(X86::YMM5, 22, false ); 1582 RI->mapLLVMRegToDwarfReg(X86::YMM6, 23, false ); 1583 RI->mapLLVMRegToDwarfReg(X86::YMM7, 24, false ); 1584 RI->mapLLVMRegToDwarfReg(X86::YMM8, 25, false ); 1585 RI->mapLLVMRegToDwarfReg(X86::YMM9, 26, false ); 1586 RI->mapLLVMRegToDwarfReg(X86::YMM10, 27, false ); 1587 RI->mapLLVMRegToDwarfReg(X86::YMM11, 28, false ); 1588 RI->mapLLVMRegToDwarfReg(X86::YMM12, 29, false ); 1589 RI->mapLLVMRegToDwarfReg(X86::YMM13, 30, false ); 1590 RI->mapLLVMRegToDwarfReg(X86::YMM14, 31, false ); 1591 RI->mapLLVMRegToDwarfReg(X86::YMM15, 32, false ); 1592 break; 1593 case 1: 1594 RI->mapLLVMRegToDwarfReg(X86::AH, -1, false ); 1595 RI->mapLLVMRegToDwarfReg(X86::AL, -1, false ); 1596 RI->mapLLVMRegToDwarfReg(X86::AX, -1, false ); 1597 RI->mapLLVMRegToDwarfReg(X86::BH, -1, false ); 1598 RI->mapLLVMRegToDwarfReg(X86::BL, -1, false ); 1599 RI->mapLLVMRegToDwarfReg(X86::BP, -1, false ); 1600 RI->mapLLVMRegToDwarfReg(X86::BPL, -1, false ); 1601 RI->mapLLVMRegToDwarfReg(X86::BX, -1, false ); 1602 RI->mapLLVMRegToDwarfReg(X86::CH, -1, false ); 1603 RI->mapLLVMRegToDwarfReg(X86::CL, -1, false ); 1604 RI->mapLLVMRegToDwarfReg(X86::CR0, -1, false ); 1605 RI->mapLLVMRegToDwarfReg(X86::CR1, -1, false ); 1606 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, false ); 1607 RI->mapLLVMRegToDwarfReg(X86::CR3, -1, false ); 1608 RI->mapLLVMRegToDwarfReg(X86::CR4, -1, false ); 1609 RI->mapLLVMRegToDwarfReg(X86::CR5, -1, false ); 1610 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, false ); 1611 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, false ); 1612 RI->mapLLVMRegToDwarfReg(X86::CR8, -1, false ); 1613 RI->mapLLVMRegToDwarfReg(X86::CR9, -1, false ); 1614 RI->mapLLVMRegToDwarfReg(X86::CR10, -1, false ); 1615 RI->mapLLVMRegToDwarfReg(X86::CR11, -1, false ); 1616 RI->mapLLVMRegToDwarfReg(X86::CR12, -1, false ); 1617 RI->mapLLVMRegToDwarfReg(X86::CR13, -1, false ); 1618 RI->mapLLVMRegToDwarfReg(X86::CR14, -1, false ); 1619 RI->mapLLVMRegToDwarfReg(X86::CR15, -1, false ); 1620 RI->mapLLVMRegToDwarfReg(X86::CS, -1, false ); 1621 RI->mapLLVMRegToDwarfReg(X86::CX, -1, false ); 1622 RI->mapLLVMRegToDwarfReg(X86::DH, -1, false ); 1623 RI->mapLLVMRegToDwarfReg(X86::DI, -1, false ); 1624 RI->mapLLVMRegToDwarfReg(X86::DIL, -1, false ); 1625 RI->mapLLVMRegToDwarfReg(X86::DL, -1, false ); 1626 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, false ); 1627 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, false ); 1628 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, false ); 1629 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, false ); 1630 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, false ); 1631 RI->mapLLVMRegToDwarfReg(X86::DR5, -1, false ); 1632 RI->mapLLVMRegToDwarfReg(X86::DR6, -1, false ); 1633 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, false ); 1634 RI->mapLLVMRegToDwarfReg(X86::DS, -1, false ); 1635 RI->mapLLVMRegToDwarfReg(X86::DX, -1, false ); 1636 RI->mapLLVMRegToDwarfReg(X86::EAX, 0, false ); 1637 RI->mapLLVMRegToDwarfReg(X86::EBP, 4, false ); 1638 RI->mapLLVMRegToDwarfReg(X86::EBX, 3, false ); 1639 RI->mapLLVMRegToDwarfReg(X86::ECX, 1, false ); 1640 RI->mapLLVMRegToDwarfReg(X86::EDI, 7, false ); 1641 RI->mapLLVMRegToDwarfReg(X86::EDX, 2, false ); 1642 RI->mapLLVMRegToDwarfReg(X86::EFLAGS, -1, false ); 1643 RI->mapLLVMRegToDwarfReg(X86::EIP, 8, false ); 1644 RI->mapLLVMRegToDwarfReg(X86::EIZ, -1, false ); 1645 RI->mapLLVMRegToDwarfReg(X86::ES, -1, false ); 1646 RI->mapLLVMRegToDwarfReg(X86::ESI, 6, false ); 1647 RI->mapLLVMRegToDwarfReg(X86::ESP, 5, false ); 1648 RI->mapLLVMRegToDwarfReg(X86::FP0, -1, false ); 1649 RI->mapLLVMRegToDwarfReg(X86::FP1, -1, false ); 1650 RI->mapLLVMRegToDwarfReg(X86::FP2, -1, false ); 1651 RI->mapLLVMRegToDwarfReg(X86::FP3, -1, false ); 1652 RI->mapLLVMRegToDwarfReg(X86::FP4, -1, false ); 1653 RI->mapLLVMRegToDwarfReg(X86::FP5, -1, false ); 1654 RI->mapLLVMRegToDwarfReg(X86::FP6, -1, false ); 1655 RI->mapLLVMRegToDwarfReg(X86::FS, -1, false ); 1656 RI->mapLLVMRegToDwarfReg(X86::GS, -1, false ); 1657 RI->mapLLVMRegToDwarfReg(X86::IP, -1, false ); 1658 RI->mapLLVMRegToDwarfReg(X86::MM0, 29, false ); 1659 RI->mapLLVMRegToDwarfReg(X86::MM1, 30, false ); 1660 RI->mapLLVMRegToDwarfReg(X86::MM2, 31, false ); 1661 RI->mapLLVMRegToDwarfReg(X86::MM3, 32, false ); 1662 RI->mapLLVMRegToDwarfReg(X86::MM4, 33, false ); 1663 RI->mapLLVMRegToDwarfReg(X86::MM5, 34, false ); 1664 RI->mapLLVMRegToDwarfReg(X86::MM6, 35, false ); 1665 RI->mapLLVMRegToDwarfReg(X86::MM7, 36, false ); 1666 RI->mapLLVMRegToDwarfReg(X86::R8, -2, false ); 1667 RI->mapLLVMRegToDwarfReg(X86::R8B, -1, false ); 1668 RI->mapLLVMRegToDwarfReg(X86::R8D, -1, false ); 1669 RI->mapLLVMRegToDwarfReg(X86::R8W, -1, false ); 1670 RI->mapLLVMRegToDwarfReg(X86::R9, -2, false ); 1671 RI->mapLLVMRegToDwarfReg(X86::R9B, -1, false ); 1672 RI->mapLLVMRegToDwarfReg(X86::R9D, -1, false ); 1673 RI->mapLLVMRegToDwarfReg(X86::R9W, -1, false ); 1674 RI->mapLLVMRegToDwarfReg(X86::R10, -2, false ); 1675 RI->mapLLVMRegToDwarfReg(X86::R10B, -1, false ); 1676 RI->mapLLVMRegToDwarfReg(X86::R10D, -1, false ); 1677 RI->mapLLVMRegToDwarfReg(X86::R10W, -1, false ); 1678 RI->mapLLVMRegToDwarfReg(X86::R11, -2, false ); 1679 RI->mapLLVMRegToDwarfReg(X86::R11B, -1, false ); 1680 RI->mapLLVMRegToDwarfReg(X86::R11D, -1, false ); 1681 RI->mapLLVMRegToDwarfReg(X86::R11W, -1, false ); 1682 RI->mapLLVMRegToDwarfReg(X86::R12, -2, false ); 1683 RI->mapLLVMRegToDwarfReg(X86::R12B, -1, false ); 1684 RI->mapLLVMRegToDwarfReg(X86::R12D, -1, false ); 1685 RI->mapLLVMRegToDwarfReg(X86::R12W, -1, false ); 1686 RI->mapLLVMRegToDwarfReg(X86::R13, -2, false ); 1687 RI->mapLLVMRegToDwarfReg(X86::R13B, -1, false ); 1688 RI->mapLLVMRegToDwarfReg(X86::R13D, -1, false ); 1689 RI->mapLLVMRegToDwarfReg(X86::R13W, -1, false ); 1690 RI->mapLLVMRegToDwarfReg(X86::R14, -2, false ); 1691 RI->mapLLVMRegToDwarfReg(X86::R14B, -1, false ); 1692 RI->mapLLVMRegToDwarfReg(X86::R14D, -1, false ); 1693 RI->mapLLVMRegToDwarfReg(X86::R14W, -1, false ); 1694 RI->mapLLVMRegToDwarfReg(X86::R15, -2, false ); 1695 RI->mapLLVMRegToDwarfReg(X86::R15B, -1, false ); 1696 RI->mapLLVMRegToDwarfReg(X86::R15D, -1, false ); 1697 RI->mapLLVMRegToDwarfReg(X86::R15W, -1, false ); 1698 RI->mapLLVMRegToDwarfReg(X86::RAX, -2, false ); 1699 RI->mapLLVMRegToDwarfReg(X86::RBP, -2, false ); 1700 RI->mapLLVMRegToDwarfReg(X86::RBX, -2, false ); 1701 RI->mapLLVMRegToDwarfReg(X86::RCX, -2, false ); 1702 RI->mapLLVMRegToDwarfReg(X86::RDI, -2, false ); 1703 RI->mapLLVMRegToDwarfReg(X86::RDX, -2, false ); 1704 RI->mapLLVMRegToDwarfReg(X86::RIP, -2, false ); 1705 RI->mapLLVMRegToDwarfReg(X86::RIZ, -1, false ); 1706 RI->mapLLVMRegToDwarfReg(X86::RSI, -2, false ); 1707 RI->mapLLVMRegToDwarfReg(X86::RSP, -2, false ); 1708 RI->mapLLVMRegToDwarfReg(X86::SI, -1, false ); 1709 RI->mapLLVMRegToDwarfReg(X86::SIL, -1, false ); 1710 RI->mapLLVMRegToDwarfReg(X86::SP, -1, false ); 1711 RI->mapLLVMRegToDwarfReg(X86::SPL, -1, false ); 1712 RI->mapLLVMRegToDwarfReg(X86::SS, -1, false ); 1713 RI->mapLLVMRegToDwarfReg(X86::ST0, 12, false ); 1714 RI->mapLLVMRegToDwarfReg(X86::ST1, 13, false ); 1715 RI->mapLLVMRegToDwarfReg(X86::ST2, 14, false ); 1716 RI->mapLLVMRegToDwarfReg(X86::ST3, 15, false ); 1717 RI->mapLLVMRegToDwarfReg(X86::ST4, 16, false ); 1718 RI->mapLLVMRegToDwarfReg(X86::ST5, 17, false ); 1719 RI->mapLLVMRegToDwarfReg(X86::ST6, 18, false ); 1720 RI->mapLLVMRegToDwarfReg(X86::ST7, 19, false ); 1721 RI->mapLLVMRegToDwarfReg(X86::XMM0, 21, false ); 1722 RI->mapLLVMRegToDwarfReg(X86::XMM1, 22, false ); 1723 RI->mapLLVMRegToDwarfReg(X86::XMM2, 23, false ); 1724 RI->mapLLVMRegToDwarfReg(X86::XMM3, 24, false ); 1725 RI->mapLLVMRegToDwarfReg(X86::XMM4, 25, false ); 1726 RI->mapLLVMRegToDwarfReg(X86::XMM5, 26, false ); 1727 RI->mapLLVMRegToDwarfReg(X86::XMM6, 27, false ); 1728 RI->mapLLVMRegToDwarfReg(X86::XMM7, 28, false ); 1729 RI->mapLLVMRegToDwarfReg(X86::XMM8, -2, false ); 1730 RI->mapLLVMRegToDwarfReg(X86::XMM9, -2, false ); 1731 RI->mapLLVMRegToDwarfReg(X86::XMM10, -2, false ); 1732 RI->mapLLVMRegToDwarfReg(X86::XMM11, -2, false ); 1733 RI->mapLLVMRegToDwarfReg(X86::XMM12, -2, false ); 1734 RI->mapLLVMRegToDwarfReg(X86::XMM13, -2, false ); 1735 RI->mapLLVMRegToDwarfReg(X86::XMM14, -2, false ); 1736 RI->mapLLVMRegToDwarfReg(X86::XMM15, -2, false ); 1737 RI->mapLLVMRegToDwarfReg(X86::YMM0, 21, false ); 1738 RI->mapLLVMRegToDwarfReg(X86::YMM1, 22, false ); 1739 RI->mapLLVMRegToDwarfReg(X86::YMM2, 23, false ); 1740 RI->mapLLVMRegToDwarfReg(X86::YMM3, 24, false ); 1741 RI->mapLLVMRegToDwarfReg(X86::YMM4, 25, false ); 1742 RI->mapLLVMRegToDwarfReg(X86::YMM5, 26, false ); 1743 RI->mapLLVMRegToDwarfReg(X86::YMM6, 27, false ); 1744 RI->mapLLVMRegToDwarfReg(X86::YMM7, 28, false ); 1745 RI->mapLLVMRegToDwarfReg(X86::YMM8, -2, false ); 1746 RI->mapLLVMRegToDwarfReg(X86::YMM9, -2, false ); 1747 RI->mapLLVMRegToDwarfReg(X86::YMM10, -2, false ); 1748 RI->mapLLVMRegToDwarfReg(X86::YMM11, -2, false ); 1749 RI->mapLLVMRegToDwarfReg(X86::YMM12, -2, false ); 1750 RI->mapLLVMRegToDwarfReg(X86::YMM13, -2, false ); 1751 RI->mapLLVMRegToDwarfReg(X86::YMM14, -2, false ); 1752 RI->mapLLVMRegToDwarfReg(X86::YMM15, -2, false ); 1753 break; 1754 case 2: 1755 RI->mapLLVMRegToDwarfReg(X86::AH, -1, false ); 1756 RI->mapLLVMRegToDwarfReg(X86::AL, -1, false ); 1757 RI->mapLLVMRegToDwarfReg(X86::AX, -1, false ); 1758 RI->mapLLVMRegToDwarfReg(X86::BH, -1, false ); 1759 RI->mapLLVMRegToDwarfReg(X86::BL, -1, false ); 1760 RI->mapLLVMRegToDwarfReg(X86::BP, -1, false ); 1761 RI->mapLLVMRegToDwarfReg(X86::BPL, -1, false ); 1762 RI->mapLLVMRegToDwarfReg(X86::BX, -1, false ); 1763 RI->mapLLVMRegToDwarfReg(X86::CH, -1, false ); 1764 RI->mapLLVMRegToDwarfReg(X86::CL, -1, false ); 1765 RI->mapLLVMRegToDwarfReg(X86::CR0, -1, false ); 1766 RI->mapLLVMRegToDwarfReg(X86::CR1, -1, false ); 1767 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, false ); 1768 RI->mapLLVMRegToDwarfReg(X86::CR3, -1, false ); 1769 RI->mapLLVMRegToDwarfReg(X86::CR4, -1, false ); 1770 RI->mapLLVMRegToDwarfReg(X86::CR5, -1, false ); 1771 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, false ); 1772 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, false ); 1773 RI->mapLLVMRegToDwarfReg(X86::CR8, -1, false ); 1774 RI->mapLLVMRegToDwarfReg(X86::CR9, -1, false ); 1775 RI->mapLLVMRegToDwarfReg(X86::CR10, -1, false ); 1776 RI->mapLLVMRegToDwarfReg(X86::CR11, -1, false ); 1777 RI->mapLLVMRegToDwarfReg(X86::CR12, -1, false ); 1778 RI->mapLLVMRegToDwarfReg(X86::CR13, -1, false ); 1779 RI->mapLLVMRegToDwarfReg(X86::CR14, -1, false ); 1780 RI->mapLLVMRegToDwarfReg(X86::CR15, -1, false ); 1781 RI->mapLLVMRegToDwarfReg(X86::CS, -1, false ); 1782 RI->mapLLVMRegToDwarfReg(X86::CX, -1, false ); 1783 RI->mapLLVMRegToDwarfReg(X86::DH, -1, false ); 1784 RI->mapLLVMRegToDwarfReg(X86::DI, -1, false ); 1785 RI->mapLLVMRegToDwarfReg(X86::DIL, -1, false ); 1786 RI->mapLLVMRegToDwarfReg(X86::DL, -1, false ); 1787 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, false ); 1788 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, false ); 1789 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, false ); 1790 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, false ); 1791 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, false ); 1792 RI->mapLLVMRegToDwarfReg(X86::DR5, -1, false ); 1793 RI->mapLLVMRegToDwarfReg(X86::DR6, -1, false ); 1794 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, false ); 1795 RI->mapLLVMRegToDwarfReg(X86::DS, -1, false ); 1796 RI->mapLLVMRegToDwarfReg(X86::DX, -1, false ); 1797 RI->mapLLVMRegToDwarfReg(X86::EAX, 0, false ); 1798 RI->mapLLVMRegToDwarfReg(X86::EBP, 5, false ); 1799 RI->mapLLVMRegToDwarfReg(X86::EBX, 3, false ); 1800 RI->mapLLVMRegToDwarfReg(X86::ECX, 1, false ); 1801 RI->mapLLVMRegToDwarfReg(X86::EDI, 7, false ); 1802 RI->mapLLVMRegToDwarfReg(X86::EDX, 2, false ); 1803 RI->mapLLVMRegToDwarfReg(X86::EFLAGS, -1, false ); 1804 RI->mapLLVMRegToDwarfReg(X86::EIP, 8, false ); 1805 RI->mapLLVMRegToDwarfReg(X86::EIZ, -1, false ); 1806 RI->mapLLVMRegToDwarfReg(X86::ES, -1, false ); 1807 RI->mapLLVMRegToDwarfReg(X86::ESI, 6, false ); 1808 RI->mapLLVMRegToDwarfReg(X86::ESP, 4, false ); 1809 RI->mapLLVMRegToDwarfReg(X86::FP0, -1, false ); 1810 RI->mapLLVMRegToDwarfReg(X86::FP1, -1, false ); 1811 RI->mapLLVMRegToDwarfReg(X86::FP2, -1, false ); 1812 RI->mapLLVMRegToDwarfReg(X86::FP3, -1, false ); 1813 RI->mapLLVMRegToDwarfReg(X86::FP4, -1, false ); 1814 RI->mapLLVMRegToDwarfReg(X86::FP5, -1, false ); 1815 RI->mapLLVMRegToDwarfReg(X86::FP6, -1, false ); 1816 RI->mapLLVMRegToDwarfReg(X86::FS, -1, false ); 1817 RI->mapLLVMRegToDwarfReg(X86::GS, -1, false ); 1818 RI->mapLLVMRegToDwarfReg(X86::IP, -1, false ); 1819 RI->mapLLVMRegToDwarfReg(X86::MM0, 29, false ); 1820 RI->mapLLVMRegToDwarfReg(X86::MM1, 30, false ); 1821 RI->mapLLVMRegToDwarfReg(X86::MM2, 31, false ); 1822 RI->mapLLVMRegToDwarfReg(X86::MM3, 32, false ); 1823 RI->mapLLVMRegToDwarfReg(X86::MM4, 33, false ); 1824 RI->mapLLVMRegToDwarfReg(X86::MM5, 34, false ); 1825 RI->mapLLVMRegToDwarfReg(X86::MM6, 35, false ); 1826 RI->mapLLVMRegToDwarfReg(X86::MM7, 36, false ); 1827 RI->mapLLVMRegToDwarfReg(X86::R8, -2, false ); 1828 RI->mapLLVMRegToDwarfReg(X86::R8B, -1, false ); 1829 RI->mapLLVMRegToDwarfReg(X86::R8D, -1, false ); 1830 RI->mapLLVMRegToDwarfReg(X86::R8W, -1, false ); 1831 RI->mapLLVMRegToDwarfReg(X86::R9, -2, false ); 1832 RI->mapLLVMRegToDwarfReg(X86::R9B, -1, false ); 1833 RI->mapLLVMRegToDwarfReg(X86::R9D, -1, false ); 1834 RI->mapLLVMRegToDwarfReg(X86::R9W, -1, false ); 1835 RI->mapLLVMRegToDwarfReg(X86::R10, -2, false ); 1836 RI->mapLLVMRegToDwarfReg(X86::R10B, -1, false ); 1837 RI->mapLLVMRegToDwarfReg(X86::R10D, -1, false ); 1838 RI->mapLLVMRegToDwarfReg(X86::R10W, -1, false ); 1839 RI->mapLLVMRegToDwarfReg(X86::R11, -2, false ); 1840 RI->mapLLVMRegToDwarfReg(X86::R11B, -1, false ); 1841 RI->mapLLVMRegToDwarfReg(X86::R11D, -1, false ); 1842 RI->mapLLVMRegToDwarfReg(X86::R11W, -1, false ); 1843 RI->mapLLVMRegToDwarfReg(X86::R12, -2, false ); 1844 RI->mapLLVMRegToDwarfReg(X86::R12B, -1, false ); 1845 RI->mapLLVMRegToDwarfReg(X86::R12D, -1, false ); 1846 RI->mapLLVMRegToDwarfReg(X86::R12W, -1, false ); 1847 RI->mapLLVMRegToDwarfReg(X86::R13, -2, false ); 1848 RI->mapLLVMRegToDwarfReg(X86::R13B, -1, false ); 1849 RI->mapLLVMRegToDwarfReg(X86::R13D, -1, false ); 1850 RI->mapLLVMRegToDwarfReg(X86::R13W, -1, false ); 1851 RI->mapLLVMRegToDwarfReg(X86::R14, -2, false ); 1852 RI->mapLLVMRegToDwarfReg(X86::R14B, -1, false ); 1853 RI->mapLLVMRegToDwarfReg(X86::R14D, -1, false ); 1854 RI->mapLLVMRegToDwarfReg(X86::R14W, -1, false ); 1855 RI->mapLLVMRegToDwarfReg(X86::R15, -2, false ); 1856 RI->mapLLVMRegToDwarfReg(X86::R15B, -1, false ); 1857 RI->mapLLVMRegToDwarfReg(X86::R15D, -1, false ); 1858 RI->mapLLVMRegToDwarfReg(X86::R15W, -1, false ); 1859 RI->mapLLVMRegToDwarfReg(X86::RAX, -2, false ); 1860 RI->mapLLVMRegToDwarfReg(X86::RBP, -2, false ); 1861 RI->mapLLVMRegToDwarfReg(X86::RBX, -2, false ); 1862 RI->mapLLVMRegToDwarfReg(X86::RCX, -2, false ); 1863 RI->mapLLVMRegToDwarfReg(X86::RDI, -2, false ); 1864 RI->mapLLVMRegToDwarfReg(X86::RDX, -2, false ); 1865 RI->mapLLVMRegToDwarfReg(X86::RIP, -2, false ); 1866 RI->mapLLVMRegToDwarfReg(X86::RIZ, -1, false ); 1867 RI->mapLLVMRegToDwarfReg(X86::RSI, -2, false ); 1868 RI->mapLLVMRegToDwarfReg(X86::RSP, -2, false ); 1869 RI->mapLLVMRegToDwarfReg(X86::SI, -1, false ); 1870 RI->mapLLVMRegToDwarfReg(X86::SIL, -1, false ); 1871 RI->mapLLVMRegToDwarfReg(X86::SP, -1, false ); 1872 RI->mapLLVMRegToDwarfReg(X86::SPL, -1, false ); 1873 RI->mapLLVMRegToDwarfReg(X86::SS, -1, false ); 1874 RI->mapLLVMRegToDwarfReg(X86::ST0, 11, false ); 1875 RI->mapLLVMRegToDwarfReg(X86::ST1, 12, false ); 1876 RI->mapLLVMRegToDwarfReg(X86::ST2, 13, false ); 1877 RI->mapLLVMRegToDwarfReg(X86::ST3, 14, false ); 1878 RI->mapLLVMRegToDwarfReg(X86::ST4, 15, false ); 1879 RI->mapLLVMRegToDwarfReg(X86::ST5, 16, false ); 1880 RI->mapLLVMRegToDwarfReg(X86::ST6, 17, false ); 1881 RI->mapLLVMRegToDwarfReg(X86::ST7, 18, false ); 1882 RI->mapLLVMRegToDwarfReg(X86::XMM0, 21, false ); 1883 RI->mapLLVMRegToDwarfReg(X86::XMM1, 22, false ); 1884 RI->mapLLVMRegToDwarfReg(X86::XMM2, 23, false ); 1885 RI->mapLLVMRegToDwarfReg(X86::XMM3, 24, false ); 1886 RI->mapLLVMRegToDwarfReg(X86::XMM4, 25, false ); 1887 RI->mapLLVMRegToDwarfReg(X86::XMM5, 26, false ); 1888 RI->mapLLVMRegToDwarfReg(X86::XMM6, 27, false ); 1889 RI->mapLLVMRegToDwarfReg(X86::XMM7, 28, false ); 1890 RI->mapLLVMRegToDwarfReg(X86::XMM8, -2, false ); 1891 RI->mapLLVMRegToDwarfReg(X86::XMM9, -2, false ); 1892 RI->mapLLVMRegToDwarfReg(X86::XMM10, -2, false ); 1893 RI->mapLLVMRegToDwarfReg(X86::XMM11, -2, false ); 1894 RI->mapLLVMRegToDwarfReg(X86::XMM12, -2, false ); 1895 RI->mapLLVMRegToDwarfReg(X86::XMM13, -2, false ); 1896 RI->mapLLVMRegToDwarfReg(X86::XMM14, -2, false ); 1897 RI->mapLLVMRegToDwarfReg(X86::XMM15, -2, false ); 1898 RI->mapLLVMRegToDwarfReg(X86::YMM0, 21, false ); 1899 RI->mapLLVMRegToDwarfReg(X86::YMM1, 22, false ); 1900 RI->mapLLVMRegToDwarfReg(X86::YMM2, 23, false ); 1901 RI->mapLLVMRegToDwarfReg(X86::YMM3, 24, false ); 1902 RI->mapLLVMRegToDwarfReg(X86::YMM4, 25, false ); 1903 RI->mapLLVMRegToDwarfReg(X86::YMM5, 26, false ); 1904 RI->mapLLVMRegToDwarfReg(X86::YMM6, 27, false ); 1905 RI->mapLLVMRegToDwarfReg(X86::YMM7, 28, false ); 1906 RI->mapLLVMRegToDwarfReg(X86::YMM8, -2, false ); 1907 RI->mapLLVMRegToDwarfReg(X86::YMM9, -2, false ); 1908 RI->mapLLVMRegToDwarfReg(X86::YMM10, -2, false ); 1909 RI->mapLLVMRegToDwarfReg(X86::YMM11, -2, false ); 1910 RI->mapLLVMRegToDwarfReg(X86::YMM12, -2, false ); 1911 RI->mapLLVMRegToDwarfReg(X86::YMM13, -2, false ); 1912 RI->mapLLVMRegToDwarfReg(X86::YMM14, -2, false ); 1913 RI->mapLLVMRegToDwarfReg(X86::YMM15, -2, false ); 1914 break; 1915 } 1916 switch (EHFlavour) { 1917 default: 1918 assert(0 && "Unknown DWARF flavour"); 1919 break; 1920 case 0: 1921 RI->mapLLVMRegToDwarfReg(X86::AH, -1, true ); 1922 RI->mapLLVMRegToDwarfReg(X86::AL, -1, true ); 1923 RI->mapLLVMRegToDwarfReg(X86::AX, -1, true ); 1924 RI->mapLLVMRegToDwarfReg(X86::BH, -1, true ); 1925 RI->mapLLVMRegToDwarfReg(X86::BL, -1, true ); 1926 RI->mapLLVMRegToDwarfReg(X86::BP, -1, true ); 1927 RI->mapLLVMRegToDwarfReg(X86::BPL, -1, true ); 1928 RI->mapLLVMRegToDwarfReg(X86::BX, -1, true ); 1929 RI->mapLLVMRegToDwarfReg(X86::CH, -1, true ); 1930 RI->mapLLVMRegToDwarfReg(X86::CL, -1, true ); 1931 RI->mapLLVMRegToDwarfReg(X86::CR0, -1, true ); 1932 RI->mapLLVMRegToDwarfReg(X86::CR1, -1, true ); 1933 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, true ); 1934 RI->mapLLVMRegToDwarfReg(X86::CR3, -1, true ); 1935 RI->mapLLVMRegToDwarfReg(X86::CR4, -1, true ); 1936 RI->mapLLVMRegToDwarfReg(X86::CR5, -1, true ); 1937 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, true ); 1938 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, true ); 1939 RI->mapLLVMRegToDwarfReg(X86::CR8, -1, true ); 1940 RI->mapLLVMRegToDwarfReg(X86::CR9, -1, true ); 1941 RI->mapLLVMRegToDwarfReg(X86::CR10, -1, true ); 1942 RI->mapLLVMRegToDwarfReg(X86::CR11, -1, true ); 1943 RI->mapLLVMRegToDwarfReg(X86::CR12, -1, true ); 1944 RI->mapLLVMRegToDwarfReg(X86::CR13, -1, true ); 1945 RI->mapLLVMRegToDwarfReg(X86::CR14, -1, true ); 1946 RI->mapLLVMRegToDwarfReg(X86::CR15, -1, true ); 1947 RI->mapLLVMRegToDwarfReg(X86::CS, -1, true ); 1948 RI->mapLLVMRegToDwarfReg(X86::CX, -1, true ); 1949 RI->mapLLVMRegToDwarfReg(X86::DH, -1, true ); 1950 RI->mapLLVMRegToDwarfReg(X86::DI, -1, true ); 1951 RI->mapLLVMRegToDwarfReg(X86::DIL, -1, true ); 1952 RI->mapLLVMRegToDwarfReg(X86::DL, -1, true ); 1953 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, true ); 1954 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, true ); 1955 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, true ); 1956 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, true ); 1957 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, true ); 1958 RI->mapLLVMRegToDwarfReg(X86::DR5, -1, true ); 1959 RI->mapLLVMRegToDwarfReg(X86::DR6, -1, true ); 1960 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, true ); 1961 RI->mapLLVMRegToDwarfReg(X86::DS, -1, true ); 1962 RI->mapLLVMRegToDwarfReg(X86::DX, -1, true ); 1963 RI->mapLLVMRegToDwarfReg(X86::EAX, -2, true ); 1964 RI->mapLLVMRegToDwarfReg(X86::EBP, -2, true ); 1965 RI->mapLLVMRegToDwarfReg(X86::EBX, -2, true ); 1966 RI->mapLLVMRegToDwarfReg(X86::ECX, -2, true ); 1967 RI->mapLLVMRegToDwarfReg(X86::EDI, -2, true ); 1968 RI->mapLLVMRegToDwarfReg(X86::EDX, -2, true ); 1969 RI->mapLLVMRegToDwarfReg(X86::EFLAGS, -1, true ); 1970 RI->mapLLVMRegToDwarfReg(X86::EIP, -2, true ); 1971 RI->mapLLVMRegToDwarfReg(X86::EIZ, -1, true ); 1972 RI->mapLLVMRegToDwarfReg(X86::ES, -1, true ); 1973 RI->mapLLVMRegToDwarfReg(X86::ESI, -2, true ); 1974 RI->mapLLVMRegToDwarfReg(X86::ESP, -2, true ); 1975 RI->mapLLVMRegToDwarfReg(X86::FP0, -1, true ); 1976 RI->mapLLVMRegToDwarfReg(X86::FP1, -1, true ); 1977 RI->mapLLVMRegToDwarfReg(X86::FP2, -1, true ); 1978 RI->mapLLVMRegToDwarfReg(X86::FP3, -1, true ); 1979 RI->mapLLVMRegToDwarfReg(X86::FP4, -1, true ); 1980 RI->mapLLVMRegToDwarfReg(X86::FP5, -1, true ); 1981 RI->mapLLVMRegToDwarfReg(X86::FP6, -1, true ); 1982 RI->mapLLVMRegToDwarfReg(X86::FS, -1, true ); 1983 RI->mapLLVMRegToDwarfReg(X86::GS, -1, true ); 1984 RI->mapLLVMRegToDwarfReg(X86::IP, -1, true ); 1985 RI->mapLLVMRegToDwarfReg(X86::MM0, 41, true ); 1986 RI->mapLLVMRegToDwarfReg(X86::MM1, 42, true ); 1987 RI->mapLLVMRegToDwarfReg(X86::MM2, 43, true ); 1988 RI->mapLLVMRegToDwarfReg(X86::MM3, 44, true ); 1989 RI->mapLLVMRegToDwarfReg(X86::MM4, 45, true ); 1990 RI->mapLLVMRegToDwarfReg(X86::MM5, 46, true ); 1991 RI->mapLLVMRegToDwarfReg(X86::MM6, 47, true ); 1992 RI->mapLLVMRegToDwarfReg(X86::MM7, 48, true ); 1993 RI->mapLLVMRegToDwarfReg(X86::R8, 8, true ); 1994 RI->mapLLVMRegToDwarfReg(X86::R8B, -1, true ); 1995 RI->mapLLVMRegToDwarfReg(X86::R8D, -1, true ); 1996 RI->mapLLVMRegToDwarfReg(X86::R8W, -1, true ); 1997 RI->mapLLVMRegToDwarfReg(X86::R9, 9, true ); 1998 RI->mapLLVMRegToDwarfReg(X86::R9B, -1, true ); 1999 RI->mapLLVMRegToDwarfReg(X86::R9D, -1, true ); 2000 RI->mapLLVMRegToDwarfReg(X86::R9W, -1, true ); 2001 RI->mapLLVMRegToDwarfReg(X86::R10, 10, true ); 2002 RI->mapLLVMRegToDwarfReg(X86::R10B, -1, true ); 2003 RI->mapLLVMRegToDwarfReg(X86::R10D, -1, true ); 2004 RI->mapLLVMRegToDwarfReg(X86::R10W, -1, true ); 2005 RI->mapLLVMRegToDwarfReg(X86::R11, 11, true ); 2006 RI->mapLLVMRegToDwarfReg(X86::R11B, -1, true ); 2007 RI->mapLLVMRegToDwarfReg(X86::R11D, -1, true ); 2008 RI->mapLLVMRegToDwarfReg(X86::R11W, -1, true ); 2009 RI->mapLLVMRegToDwarfReg(X86::R12, 12, true ); 2010 RI->mapLLVMRegToDwarfReg(X86::R12B, -1, true ); 2011 RI->mapLLVMRegToDwarfReg(X86::R12D, -1, true ); 2012 RI->mapLLVMRegToDwarfReg(X86::R12W, -1, true ); 2013 RI->mapLLVMRegToDwarfReg(X86::R13, 13, true ); 2014 RI->mapLLVMRegToDwarfReg(X86::R13B, -1, true ); 2015 RI->mapLLVMRegToDwarfReg(X86::R13D, -1, true ); 2016 RI->mapLLVMRegToDwarfReg(X86::R13W, -1, true ); 2017 RI->mapLLVMRegToDwarfReg(X86::R14, 14, true ); 2018 RI->mapLLVMRegToDwarfReg(X86::R14B, -1, true ); 2019 RI->mapLLVMRegToDwarfReg(X86::R14D, -1, true ); 2020 RI->mapLLVMRegToDwarfReg(X86::R14W, -1, true ); 2021 RI->mapLLVMRegToDwarfReg(X86::R15, 15, true ); 2022 RI->mapLLVMRegToDwarfReg(X86::R15B, -1, true ); 2023 RI->mapLLVMRegToDwarfReg(X86::R15D, -1, true ); 2024 RI->mapLLVMRegToDwarfReg(X86::R15W, -1, true ); 2025 RI->mapLLVMRegToDwarfReg(X86::RAX, 0, true ); 2026 RI->mapLLVMRegToDwarfReg(X86::RBP, 6, true ); 2027 RI->mapLLVMRegToDwarfReg(X86::RBX, 3, true ); 2028 RI->mapLLVMRegToDwarfReg(X86::RCX, 2, true ); 2029 RI->mapLLVMRegToDwarfReg(X86::RDI, 5, true ); 2030 RI->mapLLVMRegToDwarfReg(X86::RDX, 1, true ); 2031 RI->mapLLVMRegToDwarfReg(X86::RIP, 16, true ); 2032 RI->mapLLVMRegToDwarfReg(X86::RIZ, -1, true ); 2033 RI->mapLLVMRegToDwarfReg(X86::RSI, 4, true ); 2034 RI->mapLLVMRegToDwarfReg(X86::RSP, 7, true ); 2035 RI->mapLLVMRegToDwarfReg(X86::SI, -1, true ); 2036 RI->mapLLVMRegToDwarfReg(X86::SIL, -1, true ); 2037 RI->mapLLVMRegToDwarfReg(X86::SP, -1, true ); 2038 RI->mapLLVMRegToDwarfReg(X86::SPL, -1, true ); 2039 RI->mapLLVMRegToDwarfReg(X86::SS, -1, true ); 2040 RI->mapLLVMRegToDwarfReg(X86::ST0, 33, true ); 2041 RI->mapLLVMRegToDwarfReg(X86::ST1, 34, true ); 2042 RI->mapLLVMRegToDwarfReg(X86::ST2, 35, true ); 2043 RI->mapLLVMRegToDwarfReg(X86::ST3, 36, true ); 2044 RI->mapLLVMRegToDwarfReg(X86::ST4, 37, true ); 2045 RI->mapLLVMRegToDwarfReg(X86::ST5, 38, true ); 2046 RI->mapLLVMRegToDwarfReg(X86::ST6, 39, true ); 2047 RI->mapLLVMRegToDwarfReg(X86::ST7, 40, true ); 2048 RI->mapLLVMRegToDwarfReg(X86::XMM0, 17, true ); 2049 RI->mapLLVMRegToDwarfReg(X86::XMM1, 18, true ); 2050 RI->mapLLVMRegToDwarfReg(X86::XMM2, 19, true ); 2051 RI->mapLLVMRegToDwarfReg(X86::XMM3, 20, true ); 2052 RI->mapLLVMRegToDwarfReg(X86::XMM4, 21, true ); 2053 RI->mapLLVMRegToDwarfReg(X86::XMM5, 22, true ); 2054 RI->mapLLVMRegToDwarfReg(X86::XMM6, 23, true ); 2055 RI->mapLLVMRegToDwarfReg(X86::XMM7, 24, true ); 2056 RI->mapLLVMRegToDwarfReg(X86::XMM8, 25, true ); 2057 RI->mapLLVMRegToDwarfReg(X86::XMM9, 26, true ); 2058 RI->mapLLVMRegToDwarfReg(X86::XMM10, 27, true ); 2059 RI->mapLLVMRegToDwarfReg(X86::XMM11, 28, true ); 2060 RI->mapLLVMRegToDwarfReg(X86::XMM12, 29, true ); 2061 RI->mapLLVMRegToDwarfReg(X86::XMM13, 30, true ); 2062 RI->mapLLVMRegToDwarfReg(X86::XMM14, 31, true ); 2063 RI->mapLLVMRegToDwarfReg(X86::XMM15, 32, true ); 2064 RI->mapLLVMRegToDwarfReg(X86::YMM0, 17, true ); 2065 RI->mapLLVMRegToDwarfReg(X86::YMM1, 18, true ); 2066 RI->mapLLVMRegToDwarfReg(X86::YMM2, 19, true ); 2067 RI->mapLLVMRegToDwarfReg(X86::YMM3, 20, true ); 2068 RI->mapLLVMRegToDwarfReg(X86::YMM4, 21, true ); 2069 RI->mapLLVMRegToDwarfReg(X86::YMM5, 22, true ); 2070 RI->mapLLVMRegToDwarfReg(X86::YMM6, 23, true ); 2071 RI->mapLLVMRegToDwarfReg(X86::YMM7, 24, true ); 2072 RI->mapLLVMRegToDwarfReg(X86::YMM8, 25, true ); 2073 RI->mapLLVMRegToDwarfReg(X86::YMM9, 26, true ); 2074 RI->mapLLVMRegToDwarfReg(X86::YMM10, 27, true ); 2075 RI->mapLLVMRegToDwarfReg(X86::YMM11, 28, true ); 2076 RI->mapLLVMRegToDwarfReg(X86::YMM12, 29, true ); 2077 RI->mapLLVMRegToDwarfReg(X86::YMM13, 30, true ); 2078 RI->mapLLVMRegToDwarfReg(X86::YMM14, 31, true ); 2079 RI->mapLLVMRegToDwarfReg(X86::YMM15, 32, true ); 2080 break; 2081 case 1: 2082 RI->mapLLVMRegToDwarfReg(X86::AH, -1, true ); 2083 RI->mapLLVMRegToDwarfReg(X86::AL, -1, true ); 2084 RI->mapLLVMRegToDwarfReg(X86::AX, -1, true ); 2085 RI->mapLLVMRegToDwarfReg(X86::BH, -1, true ); 2086 RI->mapLLVMRegToDwarfReg(X86::BL, -1, true ); 2087 RI->mapLLVMRegToDwarfReg(X86::BP, -1, true ); 2088 RI->mapLLVMRegToDwarfReg(X86::BPL, -1, true ); 2089 RI->mapLLVMRegToDwarfReg(X86::BX, -1, true ); 2090 RI->mapLLVMRegToDwarfReg(X86::CH, -1, true ); 2091 RI->mapLLVMRegToDwarfReg(X86::CL, -1, true ); 2092 RI->mapLLVMRegToDwarfReg(X86::CR0, -1, true ); 2093 RI->mapLLVMRegToDwarfReg(X86::CR1, -1, true ); 2094 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, true ); 2095 RI->mapLLVMRegToDwarfReg(X86::CR3, -1, true ); 2096 RI->mapLLVMRegToDwarfReg(X86::CR4, -1, true ); 2097 RI->mapLLVMRegToDwarfReg(X86::CR5, -1, true ); 2098 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, true ); 2099 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, true ); 2100 RI->mapLLVMRegToDwarfReg(X86::CR8, -1, true ); 2101 RI->mapLLVMRegToDwarfReg(X86::CR9, -1, true ); 2102 RI->mapLLVMRegToDwarfReg(X86::CR10, -1, true ); 2103 RI->mapLLVMRegToDwarfReg(X86::CR11, -1, true ); 2104 RI->mapLLVMRegToDwarfReg(X86::CR12, -1, true ); 2105 RI->mapLLVMRegToDwarfReg(X86::CR13, -1, true ); 2106 RI->mapLLVMRegToDwarfReg(X86::CR14, -1, true ); 2107 RI->mapLLVMRegToDwarfReg(X86::CR15, -1, true ); 2108 RI->mapLLVMRegToDwarfReg(X86::CS, -1, true ); 2109 RI->mapLLVMRegToDwarfReg(X86::CX, -1, true ); 2110 RI->mapLLVMRegToDwarfReg(X86::DH, -1, true ); 2111 RI->mapLLVMRegToDwarfReg(X86::DI, -1, true ); 2112 RI->mapLLVMRegToDwarfReg(X86::DIL, -1, true ); 2113 RI->mapLLVMRegToDwarfReg(X86::DL, -1, true ); 2114 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, true ); 2115 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, true ); 2116 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, true ); 2117 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, true ); 2118 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, true ); 2119 RI->mapLLVMRegToDwarfReg(X86::DR5, -1, true ); 2120 RI->mapLLVMRegToDwarfReg(X86::DR6, -1, true ); 2121 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, true ); 2122 RI->mapLLVMRegToDwarfReg(X86::DS, -1, true ); 2123 RI->mapLLVMRegToDwarfReg(X86::DX, -1, true ); 2124 RI->mapLLVMRegToDwarfReg(X86::EAX, 0, true ); 2125 RI->mapLLVMRegToDwarfReg(X86::EBP, 4, true ); 2126 RI->mapLLVMRegToDwarfReg(X86::EBX, 3, true ); 2127 RI->mapLLVMRegToDwarfReg(X86::ECX, 1, true ); 2128 RI->mapLLVMRegToDwarfReg(X86::EDI, 7, true ); 2129 RI->mapLLVMRegToDwarfReg(X86::EDX, 2, true ); 2130 RI->mapLLVMRegToDwarfReg(X86::EFLAGS, -1, true ); 2131 RI->mapLLVMRegToDwarfReg(X86::EIP, 8, true ); 2132 RI->mapLLVMRegToDwarfReg(X86::EIZ, -1, true ); 2133 RI->mapLLVMRegToDwarfReg(X86::ES, -1, true ); 2134 RI->mapLLVMRegToDwarfReg(X86::ESI, 6, true ); 2135 RI->mapLLVMRegToDwarfReg(X86::ESP, 5, true ); 2136 RI->mapLLVMRegToDwarfReg(X86::FP0, -1, true ); 2137 RI->mapLLVMRegToDwarfReg(X86::FP1, -1, true ); 2138 RI->mapLLVMRegToDwarfReg(X86::FP2, -1, true ); 2139 RI->mapLLVMRegToDwarfReg(X86::FP3, -1, true ); 2140 RI->mapLLVMRegToDwarfReg(X86::FP4, -1, true ); 2141 RI->mapLLVMRegToDwarfReg(X86::FP5, -1, true ); 2142 RI->mapLLVMRegToDwarfReg(X86::FP6, -1, true ); 2143 RI->mapLLVMRegToDwarfReg(X86::FS, -1, true ); 2144 RI->mapLLVMRegToDwarfReg(X86::GS, -1, true ); 2145 RI->mapLLVMRegToDwarfReg(X86::IP, -1, true ); 2146 RI->mapLLVMRegToDwarfReg(X86::MM0, 29, true ); 2147 RI->mapLLVMRegToDwarfReg(X86::MM1, 30, true ); 2148 RI->mapLLVMRegToDwarfReg(X86::MM2, 31, true ); 2149 RI->mapLLVMRegToDwarfReg(X86::MM3, 32, true ); 2150 RI->mapLLVMRegToDwarfReg(X86::MM4, 33, true ); 2151 RI->mapLLVMRegToDwarfReg(X86::MM5, 34, true ); 2152 RI->mapLLVMRegToDwarfReg(X86::MM6, 35, true ); 2153 RI->mapLLVMRegToDwarfReg(X86::MM7, 36, true ); 2154 RI->mapLLVMRegToDwarfReg(X86::R8, -2, true ); 2155 RI->mapLLVMRegToDwarfReg(X86::R8B, -1, true ); 2156 RI->mapLLVMRegToDwarfReg(X86::R8D, -1, true ); 2157 RI->mapLLVMRegToDwarfReg(X86::R8W, -1, true ); 2158 RI->mapLLVMRegToDwarfReg(X86::R9, -2, true ); 2159 RI->mapLLVMRegToDwarfReg(X86::R9B, -1, true ); 2160 RI->mapLLVMRegToDwarfReg(X86::R9D, -1, true ); 2161 RI->mapLLVMRegToDwarfReg(X86::R9W, -1, true ); 2162 RI->mapLLVMRegToDwarfReg(X86::R10, -2, true ); 2163 RI->mapLLVMRegToDwarfReg(X86::R10B, -1, true ); 2164 RI->mapLLVMRegToDwarfReg(X86::R10D, -1, true ); 2165 RI->mapLLVMRegToDwarfReg(X86::R10W, -1, true ); 2166 RI->mapLLVMRegToDwarfReg(X86::R11, -2, true ); 2167 RI->mapLLVMRegToDwarfReg(X86::R11B, -1, true ); 2168 RI->mapLLVMRegToDwarfReg(X86::R11D, -1, true ); 2169 RI->mapLLVMRegToDwarfReg(X86::R11W, -1, true ); 2170 RI->mapLLVMRegToDwarfReg(X86::R12, -2, true ); 2171 RI->mapLLVMRegToDwarfReg(X86::R12B, -1, true ); 2172 RI->mapLLVMRegToDwarfReg(X86::R12D, -1, true ); 2173 RI->mapLLVMRegToDwarfReg(X86::R12W, -1, true ); 2174 RI->mapLLVMRegToDwarfReg(X86::R13, -2, true ); 2175 RI->mapLLVMRegToDwarfReg(X86::R13B, -1, true ); 2176 RI->mapLLVMRegToDwarfReg(X86::R13D, -1, true ); 2177 RI->mapLLVMRegToDwarfReg(X86::R13W, -1, true ); 2178 RI->mapLLVMRegToDwarfReg(X86::R14, -2, true ); 2179 RI->mapLLVMRegToDwarfReg(X86::R14B, -1, true ); 2180 RI->mapLLVMRegToDwarfReg(X86::R14D, -1, true ); 2181 RI->mapLLVMRegToDwarfReg(X86::R14W, -1, true ); 2182 RI->mapLLVMRegToDwarfReg(X86::R15, -2, true ); 2183 RI->mapLLVMRegToDwarfReg(X86::R15B, -1, true ); 2184 RI->mapLLVMRegToDwarfReg(X86::R15D, -1, true ); 2185 RI->mapLLVMRegToDwarfReg(X86::R15W, -1, true ); 2186 RI->mapLLVMRegToDwarfReg(X86::RAX, -2, true ); 2187 RI->mapLLVMRegToDwarfReg(X86::RBP, -2, true ); 2188 RI->mapLLVMRegToDwarfReg(X86::RBX, -2, true ); 2189 RI->mapLLVMRegToDwarfReg(X86::RCX, -2, true ); 2190 RI->mapLLVMRegToDwarfReg(X86::RDI, -2, true ); 2191 RI->mapLLVMRegToDwarfReg(X86::RDX, -2, true ); 2192 RI->mapLLVMRegToDwarfReg(X86::RIP, -2, true ); 2193 RI->mapLLVMRegToDwarfReg(X86::RIZ, -1, true ); 2194 RI->mapLLVMRegToDwarfReg(X86::RSI, -2, true ); 2195 RI->mapLLVMRegToDwarfReg(X86::RSP, -2, true ); 2196 RI->mapLLVMRegToDwarfReg(X86::SI, -1, true ); 2197 RI->mapLLVMRegToDwarfReg(X86::SIL, -1, true ); 2198 RI->mapLLVMRegToDwarfReg(X86::SP, -1, true ); 2199 RI->mapLLVMRegToDwarfReg(X86::SPL, -1, true ); 2200 RI->mapLLVMRegToDwarfReg(X86::SS, -1, true ); 2201 RI->mapLLVMRegToDwarfReg(X86::ST0, 12, true ); 2202 RI->mapLLVMRegToDwarfReg(X86::ST1, 13, true ); 2203 RI->mapLLVMRegToDwarfReg(X86::ST2, 14, true ); 2204 RI->mapLLVMRegToDwarfReg(X86::ST3, 15, true ); 2205 RI->mapLLVMRegToDwarfReg(X86::ST4, 16, true ); 2206 RI->mapLLVMRegToDwarfReg(X86::ST5, 17, true ); 2207 RI->mapLLVMRegToDwarfReg(X86::ST6, 18, true ); 2208 RI->mapLLVMRegToDwarfReg(X86::ST7, 19, true ); 2209 RI->mapLLVMRegToDwarfReg(X86::XMM0, 21, true ); 2210 RI->mapLLVMRegToDwarfReg(X86::XMM1, 22, true ); 2211 RI->mapLLVMRegToDwarfReg(X86::XMM2, 23, true ); 2212 RI->mapLLVMRegToDwarfReg(X86::XMM3, 24, true ); 2213 RI->mapLLVMRegToDwarfReg(X86::XMM4, 25, true ); 2214 RI->mapLLVMRegToDwarfReg(X86::XMM5, 26, true ); 2215 RI->mapLLVMRegToDwarfReg(X86::XMM6, 27, true ); 2216 RI->mapLLVMRegToDwarfReg(X86::XMM7, 28, true ); 2217 RI->mapLLVMRegToDwarfReg(X86::XMM8, -2, true ); 2218 RI->mapLLVMRegToDwarfReg(X86::XMM9, -2, true ); 2219 RI->mapLLVMRegToDwarfReg(X86::XMM10, -2, true ); 2220 RI->mapLLVMRegToDwarfReg(X86::XMM11, -2, true ); 2221 RI->mapLLVMRegToDwarfReg(X86::XMM12, -2, true ); 2222 RI->mapLLVMRegToDwarfReg(X86::XMM13, -2, true ); 2223 RI->mapLLVMRegToDwarfReg(X86::XMM14, -2, true ); 2224 RI->mapLLVMRegToDwarfReg(X86::XMM15, -2, true ); 2225 RI->mapLLVMRegToDwarfReg(X86::YMM0, 21, true ); 2226 RI->mapLLVMRegToDwarfReg(X86::YMM1, 22, true ); 2227 RI->mapLLVMRegToDwarfReg(X86::YMM2, 23, true ); 2228 RI->mapLLVMRegToDwarfReg(X86::YMM3, 24, true ); 2229 RI->mapLLVMRegToDwarfReg(X86::YMM4, 25, true ); 2230 RI->mapLLVMRegToDwarfReg(X86::YMM5, 26, true ); 2231 RI->mapLLVMRegToDwarfReg(X86::YMM6, 27, true ); 2232 RI->mapLLVMRegToDwarfReg(X86::YMM7, 28, true ); 2233 RI->mapLLVMRegToDwarfReg(X86::YMM8, -2, true ); 2234 RI->mapLLVMRegToDwarfReg(X86::YMM9, -2, true ); 2235 RI->mapLLVMRegToDwarfReg(X86::YMM10, -2, true ); 2236 RI->mapLLVMRegToDwarfReg(X86::YMM11, -2, true ); 2237 RI->mapLLVMRegToDwarfReg(X86::YMM12, -2, true ); 2238 RI->mapLLVMRegToDwarfReg(X86::YMM13, -2, true ); 2239 RI->mapLLVMRegToDwarfReg(X86::YMM14, -2, true ); 2240 RI->mapLLVMRegToDwarfReg(X86::YMM15, -2, true ); 2241 break; 2242 case 2: 2243 RI->mapLLVMRegToDwarfReg(X86::AH, -1, true ); 2244 RI->mapLLVMRegToDwarfReg(X86::AL, -1, true ); 2245 RI->mapLLVMRegToDwarfReg(X86::AX, -1, true ); 2246 RI->mapLLVMRegToDwarfReg(X86::BH, -1, true ); 2247 RI->mapLLVMRegToDwarfReg(X86::BL, -1, true ); 2248 RI->mapLLVMRegToDwarfReg(X86::BP, -1, true ); 2249 RI->mapLLVMRegToDwarfReg(X86::BPL, -1, true ); 2250 RI->mapLLVMRegToDwarfReg(X86::BX, -1, true ); 2251 RI->mapLLVMRegToDwarfReg(X86::CH, -1, true ); 2252 RI->mapLLVMRegToDwarfReg(X86::CL, -1, true ); 2253 RI->mapLLVMRegToDwarfReg(X86::CR0, -1, true ); 2254 RI->mapLLVMRegToDwarfReg(X86::CR1, -1, true ); 2255 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, true ); 2256 RI->mapLLVMRegToDwarfReg(X86::CR3, -1, true ); 2257 RI->mapLLVMRegToDwarfReg(X86::CR4, -1, true ); 2258 RI->mapLLVMRegToDwarfReg(X86::CR5, -1, true ); 2259 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, true ); 2260 RI->mapLLVMRegToDwarfReg(X86::CR7, -1, true ); 2261 RI->mapLLVMRegToDwarfReg(X86::CR8, -1, true ); 2262 RI->mapLLVMRegToDwarfReg(X86::CR9, -1, true ); 2263 RI->mapLLVMRegToDwarfReg(X86::CR10, -1, true ); 2264 RI->mapLLVMRegToDwarfReg(X86::CR11, -1, true ); 2265 RI->mapLLVMRegToDwarfReg(X86::CR12, -1, true ); 2266 RI->mapLLVMRegToDwarfReg(X86::CR13, -1, true ); 2267 RI->mapLLVMRegToDwarfReg(X86::CR14, -1, true ); 2268 RI->mapLLVMRegToDwarfReg(X86::CR15, -1, true ); 2269 RI->mapLLVMRegToDwarfReg(X86::CS, -1, true ); 2270 RI->mapLLVMRegToDwarfReg(X86::CX, -1, true ); 2271 RI->mapLLVMRegToDwarfReg(X86::DH, -1, true ); 2272 RI->mapLLVMRegToDwarfReg(X86::DI, -1, true ); 2273 RI->mapLLVMRegToDwarfReg(X86::DIL, -1, true ); 2274 RI->mapLLVMRegToDwarfReg(X86::DL, -1, true ); 2275 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, true ); 2276 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, true ); 2277 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, true ); 2278 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, true ); 2279 RI->mapLLVMRegToDwarfReg(X86::DR4, -1, true ); 2280 RI->mapLLVMRegToDwarfReg(X86::DR5, -1, true ); 2281 RI->mapLLVMRegToDwarfReg(X86::DR6, -1, true ); 2282 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, true ); 2283 RI->mapLLVMRegToDwarfReg(X86::DS, -1, true ); 2284 RI->mapLLVMRegToDwarfReg(X86::DX, -1, true ); 2285 RI->mapLLVMRegToDwarfReg(X86::EAX, 0, true ); 2286 RI->mapLLVMRegToDwarfReg(X86::EBP, 5, true ); 2287 RI->mapLLVMRegToDwarfReg(X86::EBX, 3, true ); 2288 RI->mapLLVMRegToDwarfReg(X86::ECX, 1, true ); 2289 RI->mapLLVMRegToDwarfReg(X86::EDI, 7, true ); 2290 RI->mapLLVMRegToDwarfReg(X86::EDX, 2, true ); 2291 RI->mapLLVMRegToDwarfReg(X86::EFLAGS, -1, true ); 2292 RI->mapLLVMRegToDwarfReg(X86::EIP, 8, true ); 2293 RI->mapLLVMRegToDwarfReg(X86::EIZ, -1, true ); 2294 RI->mapLLVMRegToDwarfReg(X86::ES, -1, true ); 2295 RI->mapLLVMRegToDwarfReg(X86::ESI, 6, true ); 2296 RI->mapLLVMRegToDwarfReg(X86::ESP, 4, true ); 2297 RI->mapLLVMRegToDwarfReg(X86::FP0, -1, true ); 2298 RI->mapLLVMRegToDwarfReg(X86::FP1, -1, true ); 2299 RI->mapLLVMRegToDwarfReg(X86::FP2, -1, true ); 2300 RI->mapLLVMRegToDwarfReg(X86::FP3, -1, true ); 2301 RI->mapLLVMRegToDwarfReg(X86::FP4, -1, true ); 2302 RI->mapLLVMRegToDwarfReg(X86::FP5, -1, true ); 2303 RI->mapLLVMRegToDwarfReg(X86::FP6, -1, true ); 2304 RI->mapLLVMRegToDwarfReg(X86::FS, -1, true ); 2305 RI->mapLLVMRegToDwarfReg(X86::GS, -1, true ); 2306 RI->mapLLVMRegToDwarfReg(X86::IP, -1, true ); 2307 RI->mapLLVMRegToDwarfReg(X86::MM0, 29, true ); 2308 RI->mapLLVMRegToDwarfReg(X86::MM1, 30, true ); 2309 RI->mapLLVMRegToDwarfReg(X86::MM2, 31, true ); 2310 RI->mapLLVMRegToDwarfReg(X86::MM3, 32, true ); 2311 RI->mapLLVMRegToDwarfReg(X86::MM4, 33, true ); 2312 RI->mapLLVMRegToDwarfReg(X86::MM5, 34, true ); 2313 RI->mapLLVMRegToDwarfReg(X86::MM6, 35, true ); 2314 RI->mapLLVMRegToDwarfReg(X86::MM7, 36, true ); 2315 RI->mapLLVMRegToDwarfReg(X86::R8, -2, true ); 2316 RI->mapLLVMRegToDwarfReg(X86::R8B, -1, true ); 2317 RI->mapLLVMRegToDwarfReg(X86::R8D, -1, true ); 2318 RI->mapLLVMRegToDwarfReg(X86::R8W, -1, true ); 2319 RI->mapLLVMRegToDwarfReg(X86::R9, -2, true ); 2320 RI->mapLLVMRegToDwarfReg(X86::R9B, -1, true ); 2321 RI->mapLLVMRegToDwarfReg(X86::R9D, -1, true ); 2322 RI->mapLLVMRegToDwarfReg(X86::R9W, -1, true ); 2323 RI->mapLLVMRegToDwarfReg(X86::R10, -2, true ); 2324 RI->mapLLVMRegToDwarfReg(X86::R10B, -1, true ); 2325 RI->mapLLVMRegToDwarfReg(X86::R10D, -1, true ); 2326 RI->mapLLVMRegToDwarfReg(X86::R10W, -1, true ); 2327 RI->mapLLVMRegToDwarfReg(X86::R11, -2, true ); 2328 RI->mapLLVMRegToDwarfReg(X86::R11B, -1, true ); 2329 RI->mapLLVMRegToDwarfReg(X86::R11D, -1, true ); 2330 RI->mapLLVMRegToDwarfReg(X86::R11W, -1, true ); 2331 RI->mapLLVMRegToDwarfReg(X86::R12, -2, true ); 2332 RI->mapLLVMRegToDwarfReg(X86::R12B, -1, true ); 2333 RI->mapLLVMRegToDwarfReg(X86::R12D, -1, true ); 2334 RI->mapLLVMRegToDwarfReg(X86::R12W, -1, true ); 2335 RI->mapLLVMRegToDwarfReg(X86::R13, -2, true ); 2336 RI->mapLLVMRegToDwarfReg(X86::R13B, -1, true ); 2337 RI->mapLLVMRegToDwarfReg(X86::R13D, -1, true ); 2338 RI->mapLLVMRegToDwarfReg(X86::R13W, -1, true ); 2339 RI->mapLLVMRegToDwarfReg(X86::R14, -2, true ); 2340 RI->mapLLVMRegToDwarfReg(X86::R14B, -1, true ); 2341 RI->mapLLVMRegToDwarfReg(X86::R14D, -1, true ); 2342 RI->mapLLVMRegToDwarfReg(X86::R14W, -1, true ); 2343 RI->mapLLVMRegToDwarfReg(X86::R15, -2, true ); 2344 RI->mapLLVMRegToDwarfReg(X86::R15B, -1, true ); 2345 RI->mapLLVMRegToDwarfReg(X86::R15D, -1, true ); 2346 RI->mapLLVMRegToDwarfReg(X86::R15W, -1, true ); 2347 RI->mapLLVMRegToDwarfReg(X86::RAX, -2, true ); 2348 RI->mapLLVMRegToDwarfReg(X86::RBP, -2, true ); 2349 RI->mapLLVMRegToDwarfReg(X86::RBX, -2, true ); 2350 RI->mapLLVMRegToDwarfReg(X86::RCX, -2, true ); 2351 RI->mapLLVMRegToDwarfReg(X86::RDI, -2, true ); 2352 RI->mapLLVMRegToDwarfReg(X86::RDX, -2, true ); 2353 RI->mapLLVMRegToDwarfReg(X86::RIP, -2, true ); 2354 RI->mapLLVMRegToDwarfReg(X86::RIZ, -1, true ); 2355 RI->mapLLVMRegToDwarfReg(X86::RSI, -2, true ); 2356 RI->mapLLVMRegToDwarfReg(X86::RSP, -2, true ); 2357 RI->mapLLVMRegToDwarfReg(X86::SI, -1, true ); 2358 RI->mapLLVMRegToDwarfReg(X86::SIL, -1, true ); 2359 RI->mapLLVMRegToDwarfReg(X86::SP, -1, true ); 2360 RI->mapLLVMRegToDwarfReg(X86::SPL, -1, true ); 2361 RI->mapLLVMRegToDwarfReg(X86::SS, -1, true ); 2362 RI->mapLLVMRegToDwarfReg(X86::ST0, 11, true ); 2363 RI->mapLLVMRegToDwarfReg(X86::ST1, 12, true ); 2364 RI->mapLLVMRegToDwarfReg(X86::ST2, 13, true ); 2365 RI->mapLLVMRegToDwarfReg(X86::ST3, 14, true ); 2366 RI->mapLLVMRegToDwarfReg(X86::ST4, 15, true ); 2367 RI->mapLLVMRegToDwarfReg(X86::ST5, 16, true ); 2368 RI->mapLLVMRegToDwarfReg(X86::ST6, 17, true ); 2369 RI->mapLLVMRegToDwarfReg(X86::ST7, 18, true ); 2370 RI->mapLLVMRegToDwarfReg(X86::XMM0, 21, true ); 2371 RI->mapLLVMRegToDwarfReg(X86::XMM1, 22, true ); 2372 RI->mapLLVMRegToDwarfReg(X86::XMM2, 23, true ); 2373 RI->mapLLVMRegToDwarfReg(X86::XMM3, 24, true ); 2374 RI->mapLLVMRegToDwarfReg(X86::XMM4, 25, true ); 2375 RI->mapLLVMRegToDwarfReg(X86::XMM5, 26, true ); 2376 RI->mapLLVMRegToDwarfReg(X86::XMM6, 27, true ); 2377 RI->mapLLVMRegToDwarfReg(X86::XMM7, 28, true ); 2378 RI->mapLLVMRegToDwarfReg(X86::XMM8, -2, true ); 2379 RI->mapLLVMRegToDwarfReg(X86::XMM9, -2, true ); 2380 RI->mapLLVMRegToDwarfReg(X86::XMM10, -2, true ); 2381 RI->mapLLVMRegToDwarfReg(X86::XMM11, -2, true ); 2382 RI->mapLLVMRegToDwarfReg(X86::XMM12, -2, true ); 2383 RI->mapLLVMRegToDwarfReg(X86::XMM13, -2, true ); 2384 RI->mapLLVMRegToDwarfReg(X86::XMM14, -2, true ); 2385 RI->mapLLVMRegToDwarfReg(X86::XMM15, -2, true ); 2386 RI->mapLLVMRegToDwarfReg(X86::YMM0, 21, true ); 2387 RI->mapLLVMRegToDwarfReg(X86::YMM1, 22, true ); 2388 RI->mapLLVMRegToDwarfReg(X86::YMM2, 23, true ); 2389 RI->mapLLVMRegToDwarfReg(X86::YMM3, 24, true ); 2390 RI->mapLLVMRegToDwarfReg(X86::YMM4, 25, true ); 2391 RI->mapLLVMRegToDwarfReg(X86::YMM5, 26, true ); 2392 RI->mapLLVMRegToDwarfReg(X86::YMM6, 27, true ); 2393 RI->mapLLVMRegToDwarfReg(X86::YMM7, 28, true ); 2394 RI->mapLLVMRegToDwarfReg(X86::YMM8, -2, true ); 2395 RI->mapLLVMRegToDwarfReg(X86::YMM9, -2, true ); 2396 RI->mapLLVMRegToDwarfReg(X86::YMM10, -2, true ); 2397 RI->mapLLVMRegToDwarfReg(X86::YMM11, -2, true ); 2398 RI->mapLLVMRegToDwarfReg(X86::YMM12, -2, true ); 2399 RI->mapLLVMRegToDwarfReg(X86::YMM13, -2, true ); 2400 RI->mapLLVMRegToDwarfReg(X86::YMM14, -2, true ); 2401 RI->mapLLVMRegToDwarfReg(X86::YMM15, -2, true ); 2402 break; 2403 } 2404} 2405 2406} // End llvm namespace 2407#endif // GET_REGINFO_MC_DESC 2408 2409//===- TableGen'erated file -------------------------------------*- C++ -*-===// 2410// 2411// Register Information Header Fragment 2412// 2413// Automatically generated file, do not edit! 2414// 2415//===----------------------------------------------------------------------===// 2416 2417 2418#ifdef GET_REGINFO_HEADER 2419#undef GET_REGINFO_HEADER 2420#include "llvm/Target/TargetRegisterInfo.h" 2421#include <string> 2422 2423namespace llvm { 2424 2425struct X86GenRegisterInfo : public TargetRegisterInfo { 2426 explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0); 2427 virtual bool needsStackRealignment(const MachineFunction &) const 2428 { return false; } 2429 unsigned getSubReg(unsigned RegNo, unsigned Index) const; 2430 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; 2431 unsigned composeSubRegIndices(unsigned, unsigned) const; 2432 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const; 2433}; 2434 2435 2436// Subregister indices 2437namespace X86 { 2438enum { 2439 NoSubRegister, 2440 sub_8bit, // 1 2441 sub_8bit_hi, // 2 2442 sub_16bit, // 3 2443 sub_32bit, // 4 2444 sub_sd, // 5 2445 sub_ss, // 6 2446 sub_xmm, // 7 2447 NUM_TARGET_NAMED_SUBREGS = 8 2448}; 2449} 2450namespace X86 { // Register classes 2451 struct GR8Class : public TargetRegisterClass { 2452 GR8Class(); 2453 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const; 2454 }; 2455 extern GR8Class GR8RegClass; 2456 static TargetRegisterClass * const GR8RegisterClass = &GR8RegClass; 2457 struct GR64Class : public TargetRegisterClass { 2458 GR64Class(); 2459 }; 2460 extern GR64Class GR64RegClass; 2461 static TargetRegisterClass * const GR64RegisterClass = &GR64RegClass; 2462 struct GR16Class : public TargetRegisterClass { 2463 GR16Class(); 2464 }; 2465 extern GR16Class GR16RegClass; 2466 static TargetRegisterClass * const GR16RegisterClass = &GR16RegClass; 2467 struct GR32Class : public TargetRegisterClass { 2468 GR32Class(); 2469 }; 2470 extern GR32Class GR32RegClass; 2471 static TargetRegisterClass * const GR32RegisterClass = &GR32RegClass; 2472 struct FR32Class : public TargetRegisterClass { 2473 FR32Class(); 2474 }; 2475 extern FR32Class FR32RegClass; 2476 static TargetRegisterClass * const FR32RegisterClass = &FR32RegClass; 2477 struct GR64_with_sub_8bitClass : public TargetRegisterClass { 2478 GR64_with_sub_8bitClass(); 2479 }; 2480 extern GR64_with_sub_8bitClass GR64_with_sub_8bitRegClass; 2481 static TargetRegisterClass * const GR64_with_sub_8bitRegisterClass = &GR64_with_sub_8bitRegClass; 2482 struct FR64Class : public TargetRegisterClass { 2483 FR64Class(); 2484 }; 2485 extern FR64Class FR64RegClass; 2486 static TargetRegisterClass * const FR64RegisterClass = &FR64RegClass; 2487 struct CONTROL_REGClass : public TargetRegisterClass { 2488 CONTROL_REGClass(); 2489 }; 2490 extern CONTROL_REGClass CONTROL_REGRegClass; 2491 static TargetRegisterClass * const CONTROL_REGRegisterClass = &CONTROL_REGRegClass; 2492 struct VR128Class : public TargetRegisterClass { 2493 VR128Class(); 2494 }; 2495 extern VR128Class VR128RegClass; 2496 static TargetRegisterClass * const VR128RegisterClass = &VR128RegClass; 2497 struct VR256Class : public TargetRegisterClass { 2498 VR256Class(); 2499 }; 2500 extern VR256Class VR256RegClass; 2501 static TargetRegisterClass * const VR256RegisterClass = &VR256RegClass; 2502 struct GR32_NOSPClass : public TargetRegisterClass { 2503 GR32_NOSPClass(); 2504 }; 2505 extern GR32_NOSPClass GR32_NOSPRegClass; 2506 static TargetRegisterClass * const GR32_NOSPRegisterClass = &GR32_NOSPRegClass; 2507 struct GR32_NOAXClass : public TargetRegisterClass { 2508 GR32_NOAXClass(); 2509 }; 2510 extern GR32_NOAXClass GR32_NOAXRegClass; 2511 static TargetRegisterClass * const GR32_NOAXRegisterClass = &GR32_NOAXRegClass; 2512 struct GR64_NOSPClass : public TargetRegisterClass { 2513 GR64_NOSPClass(); 2514 }; 2515 extern GR64_NOSPClass GR64_NOSPRegClass; 2516 static TargetRegisterClass * const GR64_NOSPRegisterClass = &GR64_NOSPRegClass; 2517 struct GR64_TCClass : public TargetRegisterClass { 2518 GR64_TCClass(); 2519 }; 2520 extern GR64_TCClass GR64_TCRegClass; 2521 static TargetRegisterClass * const GR64_TCRegisterClass = &GR64_TCRegClass; 2522 struct GR64_NOREXClass : public TargetRegisterClass { 2523 GR64_NOREXClass(); 2524 }; 2525 extern GR64_NOREXClass GR64_NOREXRegClass; 2526 static TargetRegisterClass * const GR64_NOREXRegisterClass = &GR64_NOREXRegClass; 2527 struct GR8_NOREXClass : public TargetRegisterClass { 2528 GR8_NOREXClass(); 2529 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction&) const; 2530 }; 2531 extern GR8_NOREXClass GR8_NOREXRegClass; 2532 static TargetRegisterClass * const GR8_NOREXRegisterClass = &GR8_NOREXRegClass; 2533 struct GR16_NOREXClass : public TargetRegisterClass { 2534 GR16_NOREXClass(); 2535 }; 2536 extern GR16_NOREXClass GR16_NOREXRegClass; 2537 static TargetRegisterClass * const GR16_NOREXRegisterClass = &GR16_NOREXRegClass; 2538 struct GR32_NOREXClass : public TargetRegisterClass { 2539 GR32_NOREXClass(); 2540 }; 2541 extern GR32_NOREXClass GR32_NOREXRegClass; 2542 static TargetRegisterClass * const GR32_NOREXRegisterClass = &GR32_NOREXRegClass; 2543 struct DEBUG_REGClass : public TargetRegisterClass { 2544 DEBUG_REGClass(); 2545 }; 2546 extern DEBUG_REGClass DEBUG_REGRegClass; 2547 static TargetRegisterClass * const DEBUG_REGRegisterClass = &DEBUG_REGRegClass; 2548 struct VR64Class : public TargetRegisterClass { 2549 VR64Class(); 2550 }; 2551 extern VR64Class VR64RegClass; 2552 static TargetRegisterClass * const VR64RegisterClass = &VR64RegClass; 2553 struct GR64_TC_with_sub_8bitClass : public TargetRegisterClass { 2554 GR64_TC_with_sub_8bitClass(); 2555 }; 2556 extern GR64_TC_with_sub_8bitClass GR64_TC_with_sub_8bitRegClass; 2557 static TargetRegisterClass * const GR64_TC_with_sub_8bitRegisterClass = &GR64_TC_with_sub_8bitRegClass; 2558 struct GR64_NOREX_with_sub_8bitClass : public TargetRegisterClass { 2559 GR64_NOREX_with_sub_8bitClass(); 2560 }; 2561 extern GR64_NOREX_with_sub_8bitClass GR64_NOREX_with_sub_8bitRegClass; 2562 static TargetRegisterClass * const GR64_NOREX_with_sub_8bitRegisterClass = &GR64_NOREX_with_sub_8bitRegClass; 2563 struct RSTClass : public TargetRegisterClass { 2564 RSTClass(); 2565 }; 2566 extern RSTClass RSTRegClass; 2567 static TargetRegisterClass * const RSTRegisterClass = &RSTRegClass; 2568 struct RFP32Class : public TargetRegisterClass { 2569 RFP32Class(); 2570 }; 2571 extern RFP32Class RFP32RegClass; 2572 static TargetRegisterClass * const RFP32RegisterClass = &RFP32RegClass; 2573 struct GR32_NOREX_NOSPClass : public TargetRegisterClass { 2574 GR32_NOREX_NOSPClass(); 2575 }; 2576 extern GR32_NOREX_NOSPClass GR32_NOREX_NOSPRegClass; 2577 static TargetRegisterClass * const GR32_NOREX_NOSPRegisterClass = &GR32_NOREX_NOSPRegClass; 2578 struct RFP64Class : public TargetRegisterClass { 2579 RFP64Class(); 2580 }; 2581 extern RFP64Class RFP64RegClass; 2582 static TargetRegisterClass * const RFP64RegisterClass = &RFP64RegClass; 2583 struct GR64_NOREX_NOSPClass : public TargetRegisterClass { 2584 GR64_NOREX_NOSPClass(); 2585 }; 2586 extern GR64_NOREX_NOSPClass GR64_NOREX_NOSPRegClass; 2587 static TargetRegisterClass * const GR64_NOREX_NOSPRegisterClass = &GR64_NOREX_NOSPRegClass; 2588 struct RFP80Class : public TargetRegisterClass { 2589 RFP80Class(); 2590 }; 2591 extern RFP80Class RFP80RegClass; 2592 static TargetRegisterClass * const RFP80RegisterClass = &RFP80RegClass; 2593 struct SEGMENT_REGClass : public TargetRegisterClass { 2594 SEGMENT_REGClass(); 2595 }; 2596 extern SEGMENT_REGClass SEGMENT_REGRegClass; 2597 static TargetRegisterClass * const SEGMENT_REGRegisterClass = &SEGMENT_REGRegClass; 2598 struct GR64_TCW64Class : public TargetRegisterClass { 2599 GR64_TCW64Class(); 2600 }; 2601 extern GR64_TCW64Class GR64_TCW64RegClass; 2602 static TargetRegisterClass * const GR64_TCW64RegisterClass = &GR64_TCW64RegClass; 2603 struct GR8_ABCD_LClass : public TargetRegisterClass { 2604 GR8_ABCD_LClass(); 2605 }; 2606 extern GR8_ABCD_LClass GR8_ABCD_LRegClass; 2607 static TargetRegisterClass * const GR8_ABCD_LRegisterClass = &GR8_ABCD_LRegClass; 2608 struct GR8_ABCD_HClass : public TargetRegisterClass { 2609 GR8_ABCD_HClass(); 2610 }; 2611 extern GR8_ABCD_HClass GR8_ABCD_HRegClass; 2612 static TargetRegisterClass * const GR8_ABCD_HRegisterClass = &GR8_ABCD_HRegClass; 2613 struct GR16_ABCDClass : public TargetRegisterClass { 2614 GR16_ABCDClass(); 2615 }; 2616 extern GR16_ABCDClass GR16_ABCDRegClass; 2617 static TargetRegisterClass * const GR16_ABCDRegisterClass = &GR16_ABCDRegClass; 2618 struct GR32_ABCDClass : public TargetRegisterClass { 2619 GR32_ABCDClass(); 2620 }; 2621 extern GR32_ABCDClass GR32_ABCDRegClass; 2622 static TargetRegisterClass * const GR32_ABCDRegisterClass = &GR32_ABCDRegClass; 2623 struct GR64_ABCDClass : public TargetRegisterClass { 2624 GR64_ABCDClass(); 2625 }; 2626 extern GR64_ABCDClass GR64_ABCDRegClass; 2627 static TargetRegisterClass * const GR64_ABCDRegisterClass = &GR64_ABCDRegClass; 2628 struct GR32_TCClass : public TargetRegisterClass { 2629 GR32_TCClass(); 2630 }; 2631 extern GR32_TCClass GR32_TCRegClass; 2632 static TargetRegisterClass * const GR32_TCRegisterClass = &GR32_TCRegClass; 2633 struct GR32_NOAX_with_sub_8bit_hiClass : public TargetRegisterClass { 2634 GR32_NOAX_with_sub_8bit_hiClass(); 2635 }; 2636 extern GR32_NOAX_with_sub_8bit_hiClass GR32_NOAX_with_sub_8bit_hiRegClass; 2637 static TargetRegisterClass * const GR32_NOAX_with_sub_8bit_hiRegisterClass = &GR32_NOAX_with_sub_8bit_hiRegClass; 2638 struct GR64_TC_with_sub_8bit_hiClass : public TargetRegisterClass { 2639 GR64_TC_with_sub_8bit_hiClass(); 2640 }; 2641 extern GR64_TC_with_sub_8bit_hiClass GR64_TC_with_sub_8bit_hiRegClass; 2642 static TargetRegisterClass * const GR64_TC_with_sub_8bit_hiRegisterClass = &GR64_TC_with_sub_8bit_hiRegClass; 2643 struct GR32_ADClass : public TargetRegisterClass { 2644 GR32_ADClass(); 2645 }; 2646 extern GR32_ADClass GR32_ADRegClass; 2647 static TargetRegisterClass * const GR32_ADRegisterClass = &GR32_ADRegClass; 2648 struct CCRClass : public TargetRegisterClass { 2649 CCRClass(); 2650 }; 2651 extern CCRClass CCRRegClass; 2652 static TargetRegisterClass * const CCRRegisterClass = &CCRRegClass; 2653} // end of namespace X86 2654 2655} // End llvm namespace 2656#endif // GET_REGINFO_HEADER 2657 2658//===- TableGen'erated file -------------------------------------*- C++ -*-===// 2659// 2660// Target Register and Register Classes Information 2661// 2662// Automatically generated file, do not edit! 2663// 2664//===----------------------------------------------------------------------===// 2665 2666 2667#ifdef GET_REGINFO_TARGET_DESC 2668#undef GET_REGINFO_TARGET_DESC 2669namespace llvm { 2670 2671extern MCRegisterClass X86MCRegisterClasses[]; 2672namespace { // Register classes... 2673 // GR8VTs Register Class Value Types... 2674 static const EVT GR8VTs[] = { 2675 MVT::i8, MVT::Other 2676 }; 2677 2678 // GR64VTs Register Class Value Types... 2679 static const EVT GR64VTs[] = { 2680 MVT::i64, MVT::Other 2681 }; 2682 2683 // GR16VTs Register Class Value Types... 2684 static const EVT GR16VTs[] = { 2685 MVT::i16, MVT::Other 2686 }; 2687 2688 // GR32VTs Register Class Value Types... 2689 static const EVT GR32VTs[] = { 2690 MVT::i32, MVT::Other 2691 }; 2692 2693 // FR32VTs Register Class Value Types... 2694 static const EVT FR32VTs[] = { 2695 MVT::f32, MVT::Other 2696 }; 2697 2698 // GR64_with_sub_8bitVTs Register Class Value Types... 2699 static const EVT GR64_with_sub_8bitVTs[] = { 2700 MVT::i64, MVT::Other 2701 }; 2702 2703 // FR64VTs Register Class Value Types... 2704 static const EVT FR64VTs[] = { 2705 MVT::f64, MVT::Other 2706 }; 2707 2708 // CONTROL_REGVTs Register Class Value Types... 2709 static const EVT CONTROL_REGVTs[] = { 2710 MVT::i64, MVT::Other 2711 }; 2712 2713 // VR128VTs Register Class Value Types... 2714 static const EVT VR128VTs[] = { 2715 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other 2716 }; 2717 2718 // VR256VTs Register Class Value Types... 2719 static const EVT VR256VTs[] = { 2720 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::v8f32, MVT::v4f64, MVT::Other 2721 }; 2722 2723 // GR32_NOSPVTs Register Class Value Types... 2724 static const EVT GR32_NOSPVTs[] = { 2725 MVT::i32, MVT::Other 2726 }; 2727 2728 // GR32_NOAXVTs Register Class Value Types... 2729 static const EVT GR32_NOAXVTs[] = { 2730 MVT::i32, MVT::Other 2731 }; 2732 2733 // GR64_NOSPVTs Register Class Value Types... 2734 static const EVT GR64_NOSPVTs[] = { 2735 MVT::i64, MVT::Other 2736 }; 2737 2738 // GR64_TCVTs Register Class Value Types... 2739 static const EVT GR64_TCVTs[] = { 2740 MVT::i64, MVT::Other 2741 }; 2742 2743 // GR64_NOREXVTs Register Class Value Types... 2744 static const EVT GR64_NOREXVTs[] = { 2745 MVT::i64, MVT::Other 2746 }; 2747 2748 // GR8_NOREXVTs Register Class Value Types... 2749 static const EVT GR8_NOREXVTs[] = { 2750 MVT::i8, MVT::Other 2751 }; 2752 2753 // GR16_NOREXVTs Register Class Value Types... 2754 static const EVT GR16_NOREXVTs[] = { 2755 MVT::i16, MVT::Other 2756 }; 2757 2758 // GR32_NOREXVTs Register Class Value Types... 2759 static const EVT GR32_NOREXVTs[] = { 2760 MVT::i32, MVT::Other 2761 }; 2762 2763 // DEBUG_REGVTs Register Class Value Types... 2764 static const EVT DEBUG_REGVTs[] = { 2765 MVT::i32, MVT::Other 2766 }; 2767 2768 // VR64VTs Register Class Value Types... 2769 static const EVT VR64VTs[] = { 2770 MVT::x86mmx, MVT::Other 2771 }; 2772 2773 // GR64_TC_with_sub_8bitVTs Register Class Value Types... 2774 static const EVT GR64_TC_with_sub_8bitVTs[] = { 2775 MVT::i64, MVT::Other 2776 }; 2777 2778 // GR64_NOREX_with_sub_8bitVTs Register Class Value Types... 2779 static const EVT GR64_NOREX_with_sub_8bitVTs[] = { 2780 MVT::i64, MVT::Other 2781 }; 2782 2783 // RSTVTs Register Class Value Types... 2784 static const EVT RSTVTs[] = { 2785 MVT::f80, MVT::f64, MVT::f32, MVT::Other 2786 }; 2787 2788 // RFP32VTs Register Class Value Types... 2789 static const EVT RFP32VTs[] = { 2790 MVT::f32, MVT::Other 2791 }; 2792 2793 // GR32_NOREX_NOSPVTs Register Class Value Types... 2794 static const EVT GR32_NOREX_NOSPVTs[] = { 2795 MVT::i32, MVT::Other 2796 }; 2797 2798 // RFP64VTs Register Class Value Types... 2799 static const EVT RFP64VTs[] = { 2800 MVT::f64, MVT::Other 2801 }; 2802 2803 // GR64_NOREX_NOSPVTs Register Class Value Types... 2804 static const EVT GR64_NOREX_NOSPVTs[] = { 2805 MVT::i64, MVT::Other 2806 }; 2807 2808 // RFP80VTs Register Class Value Types... 2809 static const EVT RFP80VTs[] = { 2810 MVT::f80, MVT::Other 2811 }; 2812 2813 // SEGMENT_REGVTs Register Class Value Types... 2814 static const EVT SEGMENT_REGVTs[] = { 2815 MVT::i16, MVT::Other 2816 }; 2817 2818 // GR64_TCW64VTs Register Class Value Types... 2819 static const EVT GR64_TCW64VTs[] = { 2820 MVT::i64, MVT::Other 2821 }; 2822 2823 // GR8_ABCD_LVTs Register Class Value Types... 2824 static const EVT GR8_ABCD_LVTs[] = { 2825 MVT::i8, MVT::Other 2826 }; 2827 2828 // GR8_ABCD_HVTs Register Class Value Types... 2829 static const EVT GR8_ABCD_HVTs[] = { 2830 MVT::i8, MVT::Other 2831 }; 2832 2833 // GR16_ABCDVTs Register Class Value Types... 2834 static const EVT GR16_ABCDVTs[] = { 2835 MVT::i16, MVT::Other 2836 }; 2837 2838 // GR32_ABCDVTs Register Class Value Types... 2839 static const EVT GR32_ABCDVTs[] = { 2840 MVT::i32, MVT::Other 2841 }; 2842 2843 // GR64_ABCDVTs Register Class Value Types... 2844 static const EVT GR64_ABCDVTs[] = { 2845 MVT::i64, MVT::Other 2846 }; 2847 2848 // GR32_TCVTs Register Class Value Types... 2849 static const EVT GR32_TCVTs[] = { 2850 MVT::i32, MVT::Other 2851 }; 2852 2853 // GR32_NOAX_with_sub_8bit_hiVTs Register Class Value Types... 2854 static const EVT GR32_NOAX_with_sub_8bit_hiVTs[] = { 2855 MVT::i32, MVT::Other 2856 }; 2857 2858 // GR64_TC_with_sub_8bit_hiVTs Register Class Value Types... 2859 static const EVT GR64_TC_with_sub_8bit_hiVTs[] = { 2860 MVT::i64, MVT::Other 2861 }; 2862 2863 // GR32_ADVTs Register Class Value Types... 2864 static const EVT GR32_ADVTs[] = { 2865 MVT::i32, MVT::Other 2866 }; 2867 2868 // CCRVTs Register Class Value Types... 2869 static const EVT CCRVTs[] = { 2870 MVT::i32, MVT::Other 2871 }; 2872 2873} // end anonymous namespace 2874 2875namespace X86 { // Register class instances 2876 GR8Class GR8RegClass; 2877 GR64Class GR64RegClass; 2878 GR16Class GR16RegClass; 2879 GR32Class GR32RegClass; 2880 FR32Class FR32RegClass; 2881 GR64_with_sub_8bitClass GR64_with_sub_8bitRegClass; 2882 FR64Class FR64RegClass; 2883 CONTROL_REGClass CONTROL_REGRegClass; 2884 VR128Class VR128RegClass; 2885 VR256Class VR256RegClass; 2886 GR32_NOSPClass GR32_NOSPRegClass; 2887 GR32_NOAXClass GR32_NOAXRegClass; 2888 GR64_NOSPClass GR64_NOSPRegClass; 2889 GR64_TCClass GR64_TCRegClass; 2890 GR64_NOREXClass GR64_NOREXRegClass; 2891 GR8_NOREXClass GR8_NOREXRegClass; 2892 GR16_NOREXClass GR16_NOREXRegClass; 2893 GR32_NOREXClass GR32_NOREXRegClass; 2894 DEBUG_REGClass DEBUG_REGRegClass; 2895 VR64Class VR64RegClass; 2896 GR64_TC_with_sub_8bitClass GR64_TC_with_sub_8bitRegClass; 2897 GR64_NOREX_with_sub_8bitClass GR64_NOREX_with_sub_8bitRegClass; 2898 RSTClass RSTRegClass; 2899 RFP32Class RFP32RegClass; 2900 GR32_NOREX_NOSPClass GR32_NOREX_NOSPRegClass; 2901 RFP64Class RFP64RegClass; 2902 GR64_NOREX_NOSPClass GR64_NOREX_NOSPRegClass; 2903 RFP80Class RFP80RegClass; 2904 SEGMENT_REGClass SEGMENT_REGRegClass; 2905 GR64_TCW64Class GR64_TCW64RegClass; 2906 GR8_ABCD_LClass GR8_ABCD_LRegClass; 2907 GR8_ABCD_HClass GR8_ABCD_HRegClass; 2908 GR16_ABCDClass GR16_ABCDRegClass; 2909 GR32_ABCDClass GR32_ABCDRegClass; 2910 GR64_ABCDClass GR64_ABCDRegClass; 2911 GR32_TCClass GR32_TCRegClass; 2912 GR32_NOAX_with_sub_8bit_hiClass GR32_NOAX_with_sub_8bit_hiRegClass; 2913 GR64_TC_with_sub_8bit_hiClass GR64_TC_with_sub_8bit_hiRegClass; 2914 GR32_ADClass GR32_ADRegClass; 2915 CCRClass CCRRegClass; 2916 2917 static const TargetRegisterClass* const NullRegClasses[] = { NULL }; 2918 2919 // GR8 Super-register Classes... 2920 static const TargetRegisterClass* const GR8SuperRegClasses[] = { 2921 &X86::GR64RegClass, &X86::GR16RegClass, &X86::GR32RegClass, &X86::GR32_NOSPRegClass, &X86::GR32_NOAXRegClass, &X86::GR64_NOSPRegClass, &X86::GR64_TCRegClass, &X86::GR32_TCRegClass, NULL 2922 }; 2923 2924 // GR64 Super-register Classes... 2925 static const TargetRegisterClass* const GR64SuperRegClasses[] = { 2926 NULL 2927 }; 2928 2929 // GR16 Super-register Classes... 2930 static const TargetRegisterClass* const GR16SuperRegClasses[] = { 2931 &X86::GR64RegClass, &X86::GR32RegClass, &X86::GR32_NOSPRegClass, &X86::GR32_NOAXRegClass, &X86::GR64_NOSPRegClass, &X86::GR64_TCRegClass, &X86::GR32_TCRegClass, NULL 2932 }; 2933 2934 // GR32 Super-register Classes... 2935 static const TargetRegisterClass* const GR32SuperRegClasses[] = { 2936 &X86::GR64RegClass, NULL 2937 }; 2938 2939 // FR32 Super-register Classes... 2940 static const TargetRegisterClass* const FR32SuperRegClasses[] = { 2941 &X86::VR128RegClass, &X86::VR256RegClass, NULL 2942 }; 2943 2944 // GR64_with_sub_8bit Super-register Classes... 2945 static const TargetRegisterClass* const GR64_with_sub_8bitSuperRegClasses[] = { 2946 NULL 2947 }; 2948 2949 // FR64 Super-register Classes... 2950 static const TargetRegisterClass* const FR64SuperRegClasses[] = { 2951 &X86::VR128RegClass, &X86::VR256RegClass, NULL 2952 }; 2953 2954 // CONTROL_REG Super-register Classes... 2955 static const TargetRegisterClass* const CONTROL_REGSuperRegClasses[] = { 2956 NULL 2957 }; 2958 2959 // VR128 Super-register Classes... 2960 static const TargetRegisterClass* const VR128SuperRegClasses[] = { 2961 &X86::VR256RegClass, NULL 2962 }; 2963 2964 // VR256 Super-register Classes... 2965 static const TargetRegisterClass* const VR256SuperRegClasses[] = { 2966 NULL 2967 }; 2968 2969 // GR32_NOSP Super-register Classes... 2970 static const TargetRegisterClass* const GR32_NOSPSuperRegClasses[] = { 2971 &X86::GR64_NOSPRegClass, NULL 2972 }; 2973 2974 // GR32_NOAX Super-register Classes... 2975 static const TargetRegisterClass* const GR32_NOAXSuperRegClasses[] = { 2976 NULL 2977 }; 2978 2979 // GR64_NOSP Super-register Classes... 2980 static const TargetRegisterClass* const GR64_NOSPSuperRegClasses[] = { 2981 NULL 2982 }; 2983 2984 // GR64_TC Super-register Classes... 2985 static const TargetRegisterClass* const GR64_TCSuperRegClasses[] = { 2986 NULL 2987 }; 2988 2989 // GR64_NOREX Super-register Classes... 2990 static const TargetRegisterClass* const GR64_NOREXSuperRegClasses[] = { 2991 NULL 2992 }; 2993 2994 // GR8_NOREX Super-register Classes... 2995 static const TargetRegisterClass* const GR8_NOREXSuperRegClasses[] = { 2996 &X86::GR64_NOREXRegClass, &X86::GR16_NOREXRegClass, &X86::GR32_NOREXRegClass, &X86::GR32_NOREX_NOSPRegClass, &X86::GR64_NOREX_NOSPRegClass, NULL 2997 }; 2998 2999 // GR16_NOREX Super-register Classes... 3000 static const TargetRegisterClass* const GR16_NOREXSuperRegClasses[] = { 3001 &X86::GR64_NOREXRegClass, &X86::GR32_NOREXRegClass, &X86::GR32_NOREX_NOSPRegClass, &X86::GR64_NOREX_NOSPRegClass, NULL 3002 }; 3003 3004 // GR32_NOREX Super-register Classes... 3005 static const TargetRegisterClass* const GR32_NOREXSuperRegClasses[] = { 3006 &X86::GR64_NOREXRegClass, NULL 3007 }; 3008 3009 // DEBUG_REG Super-register Classes... 3010 static const TargetRegisterClass* const DEBUG_REGSuperRegClasses[] = { 3011 NULL 3012 }; 3013 3014 // VR64 Super-register Classes... 3015 static const TargetRegisterClass* const VR64SuperRegClasses[] = { 3016 NULL 3017 }; 3018 3019 // GR64_TC_with_sub_8bit Super-register Classes... 3020 static const TargetRegisterClass* const GR64_TC_with_sub_8bitSuperRegClasses[] = { 3021 NULL 3022 }; 3023 3024 // GR64_NOREX_with_sub_8bit Super-register Classes... 3025 static const TargetRegisterClass* const GR64_NOREX_with_sub_8bitSuperRegClasses[] = { 3026 NULL 3027 }; 3028 3029 // RST Super-register Classes... 3030 static const TargetRegisterClass* const RSTSuperRegClasses[] = { 3031 NULL 3032 }; 3033 3034 // RFP32 Super-register Classes... 3035 static const TargetRegisterClass* const RFP32SuperRegClasses[] = { 3036 NULL 3037 }; 3038 3039 // GR32_NOREX_NOSP Super-register Classes... 3040 static const TargetRegisterClass* const GR32_NOREX_NOSPSuperRegClasses[] = { 3041 &X86::GR64_NOREX_NOSPRegClass, NULL 3042 }; 3043 3044 // RFP64 Super-register Classes... 3045 static const TargetRegisterClass* const RFP64SuperRegClasses[] = { 3046 NULL 3047 }; 3048 3049 // GR64_NOREX_NOSP Super-register Classes... 3050 static const TargetRegisterClass* const GR64_NOREX_NOSPSuperRegClasses[] = { 3051 NULL 3052 }; 3053 3054 // RFP80 Super-register Classes... 3055 static const TargetRegisterClass* const RFP80SuperRegClasses[] = { 3056 NULL 3057 }; 3058 3059 // SEGMENT_REG Super-register Classes... 3060 static const TargetRegisterClass* const SEGMENT_REGSuperRegClasses[] = { 3061 NULL 3062 }; 3063 3064 // GR64_TCW64 Super-register Classes... 3065 static const TargetRegisterClass* const GR64_TCW64SuperRegClasses[] = { 3066 NULL 3067 }; 3068 3069 // GR8_ABCD_L Super-register Classes... 3070 static const TargetRegisterClass* const GR8_ABCD_LSuperRegClasses[] = { 3071 &X86::GR16_ABCDRegClass, &X86::GR32_ABCDRegClass, &X86::GR64_ABCDRegClass, &X86::GR32_ADRegClass, NULL 3072 }; 3073 3074 // GR8_ABCD_H Super-register Classes... 3075 static const TargetRegisterClass* const GR8_ABCD_HSuperRegClasses[] = { 3076 &X86::GR16_ABCDRegClass, &X86::GR32_ABCDRegClass, &X86::GR64_ABCDRegClass, &X86::GR32_ADRegClass, NULL 3077 }; 3078 3079 // GR16_ABCD Super-register Classes... 3080 static const TargetRegisterClass* const GR16_ABCDSuperRegClasses[] = { 3081 &X86::GR32_ABCDRegClass, &X86::GR64_ABCDRegClass, &X86::GR32_ADRegClass, NULL 3082 }; 3083 3084 // GR32_ABCD Super-register Classes... 3085 static const TargetRegisterClass* const GR32_ABCDSuperRegClasses[] = { 3086 &X86::GR64_ABCDRegClass, NULL 3087 }; 3088 3089 // GR64_ABCD Super-register Classes... 3090 static const TargetRegisterClass* const GR64_ABCDSuperRegClasses[] = { 3091 NULL 3092 }; 3093 3094 // GR32_TC Super-register Classes... 3095 static const TargetRegisterClass* const GR32_TCSuperRegClasses[] = { 3096 &X86::GR64_TCRegClass, NULL 3097 }; 3098 3099 // GR32_NOAX_with_sub_8bit_hi Super-register Classes... 3100 static const TargetRegisterClass* const GR32_NOAX_with_sub_8bit_hiSuperRegClasses[] = { 3101 NULL 3102 }; 3103 3104 // GR64_TC_with_sub_8bit_hi Super-register Classes... 3105 static const TargetRegisterClass* const GR64_TC_with_sub_8bit_hiSuperRegClasses[] = { 3106 NULL 3107 }; 3108 3109 // GR32_AD Super-register Classes... 3110 static const TargetRegisterClass* const GR32_ADSuperRegClasses[] = { 3111 NULL 3112 }; 3113 3114 // CCR Super-register Classes... 3115 static const TargetRegisterClass* const CCRSuperRegClasses[] = { 3116 NULL 3117 }; 3118 3119 static const unsigned GR8SubclassMask[] = { 0xc0008001, 0x00000000, }; 3120 3121 static const unsigned GR64SubclassMask[] = { 0x24307022, 0x00000024, }; 3122 3123 static const unsigned GR16SubclassMask[] = { 0x00010004, 0x00000001, }; 3124 3125 static const unsigned GR32SubclassMask[] = { 0x01020c08, 0x0000005a, }; 3126 3127 static const unsigned FR32SubclassMask[] = { 0x00000150, 0x00000000, }; 3128 3129 static const unsigned GR64_with_sub_8bitSubclassMask[] = { 0x24301020, 0x00000024, }; 3130 3131 static const unsigned FR64SubclassMask[] = { 0x00000140, 0x00000000, }; 3132 3133 static const unsigned CONTROL_REGSubclassMask[] = { 0x00000080, 0x00000000, }; 3134 3135 static const unsigned VR128SubclassMask[] = { 0x00000100, 0x00000000, }; 3136 3137 static const unsigned VR256SubclassMask[] = { 0x00000200, 0x00000000, }; 3138 3139 static const unsigned GR32_NOSPSubclassMask[] = { 0x01000400, 0x0000005a, }; 3140 3141 static const unsigned GR32_NOAXSubclassMask[] = { 0x00000800, 0x00000010, }; 3142 3143 static const unsigned GR64_NOSPSubclassMask[] = { 0x24101000, 0x00000024, }; 3144 3145 static const unsigned GR64_TCSubclassMask[] = { 0x20102000, 0x00000020, }; 3146 3147 static const unsigned GR64_NOREXSubclassMask[] = { 0x04204000, 0x00000024, }; 3148 3149 static const unsigned GR8_NOREXSubclassMask[] = { 0xc0008000, 0x00000000, }; 3150 3151 static const unsigned GR16_NOREXSubclassMask[] = { 0x00010000, 0x00000001, }; 3152 3153 static const unsigned GR32_NOREXSubclassMask[] = { 0x01020000, 0x0000005a, }; 3154 3155 static const unsigned DEBUG_REGSubclassMask[] = { 0x00040000, 0x00000000, }; 3156 3157 static const unsigned VR64SubclassMask[] = { 0x00080000, 0x00000000, }; 3158 3159 static const unsigned GR64_TC_with_sub_8bitSubclassMask[] = { 0x20100000, 0x00000020, }; 3160 3161 static const unsigned GR64_NOREX_with_sub_8bitSubclassMask[] = { 0x04200000, 0x00000024, }; 3162 3163 static const unsigned RSTSubclassMask[] = { 0x00400000, 0x00000000, }; 3164 3165 static const unsigned RFP32SubclassMask[] = { 0x0a800000, 0x00000000, }; 3166 3167 static const unsigned GR32_NOREX_NOSPSubclassMask[] = { 0x01000000, 0x0000005a, }; 3168 3169 static const unsigned RFP64SubclassMask[] = { 0x0a000000, 0x00000000, }; 3170 3171 static const unsigned GR64_NOREX_NOSPSubclassMask[] = { 0x04000000, 0x00000024, }; 3172 3173 static const unsigned RFP80SubclassMask[] = { 0x08000000, 0x00000000, }; 3174 3175 static const unsigned SEGMENT_REGSubclassMask[] = { 0x10000000, 0x00000000, }; 3176 3177 static const unsigned GR64_TCW64SubclassMask[] = { 0x20000000, 0x00000020, }; 3178 3179 static const unsigned GR8_ABCD_LSubclassMask[] = { 0x40000000, 0x00000000, }; 3180 3181 static const unsigned GR8_ABCD_HSubclassMask[] = { 0x80000000, 0x00000000, }; 3182 3183 static const unsigned GR16_ABCDSubclassMask[] = { 0x00000000, 0x00000001, }; 3184 3185 static const unsigned GR32_ABCDSubclassMask[] = { 0x00000000, 0x0000005a, }; 3186 3187 static const unsigned GR64_ABCDSubclassMask[] = { 0x00000000, 0x00000024, }; 3188 3189 static const unsigned GR32_TCSubclassMask[] = { 0x00000000, 0x00000048, }; 3190 3191 static const unsigned GR32_NOAX_with_sub_8bit_hiSubclassMask[] = { 0x00000000, 0x00000010, }; 3192 3193 static const unsigned GR64_TC_with_sub_8bit_hiSubclassMask[] = { 0x00000000, 0x00000020, }; 3194 3195 static const unsigned GR32_ADSubclassMask[] = { 0x00000000, 0x00000040, }; 3196 3197 static const unsigned CCRSubclassMask[] = { 0x00000000, 0x00000080, }; 3198 3199 static const TargetRegisterClass* const GR64_with_sub_8bitSuperclasses[] = { 3200 &X86::GR64RegClass, 3201 NULL 3202 }; 3203 3204 static const TargetRegisterClass* const FR64Superclasses[] = { 3205 &X86::FR32RegClass, 3206 NULL 3207 }; 3208 3209 static const TargetRegisterClass* const VR128Superclasses[] = { 3210 &X86::FR32RegClass, 3211 &X86::FR64RegClass, 3212 NULL 3213 }; 3214 3215 static const TargetRegisterClass* const GR32_NOSPSuperclasses[] = { 3216 &X86::GR32RegClass, 3217 NULL 3218 }; 3219 3220 static const TargetRegisterClass* const GR32_NOAXSuperclasses[] = { 3221 &X86::GR32RegClass, 3222 NULL 3223 }; 3224 3225 static const TargetRegisterClass* const GR64_NOSPSuperclasses[] = { 3226 &X86::GR64RegClass, 3227 &X86::GR64_with_sub_8bitRegClass, 3228 NULL 3229 }; 3230 3231 static const TargetRegisterClass* const GR64_TCSuperclasses[] = { 3232 &X86::GR64RegClass, 3233 NULL 3234 }; 3235 3236 static const TargetRegisterClass* const GR64_NOREXSuperclasses[] = { 3237 &X86::GR64RegClass, 3238 NULL 3239 }; 3240 3241 static const TargetRegisterClass* const GR8_NOREXSuperclasses[] = { 3242 &X86::GR8RegClass, 3243 NULL 3244 }; 3245 3246 static const TargetRegisterClass* const GR16_NOREXSuperclasses[] = { 3247 &X86::GR16RegClass, 3248 NULL 3249 }; 3250 3251 static const TargetRegisterClass* const GR32_NOREXSuperclasses[] = { 3252 &X86::GR32RegClass, 3253 NULL 3254 }; 3255 3256 static const TargetRegisterClass* const GR64_TC_with_sub_8bitSuperclasses[] = { 3257 &X86::GR64RegClass, 3258 &X86::GR64_with_sub_8bitRegClass, 3259 &X86::GR64_NOSPRegClass, 3260 &X86::GR64_TCRegClass, 3261 NULL 3262 }; 3263 3264 static const TargetRegisterClass* const GR64_NOREX_with_sub_8bitSuperclasses[] = { 3265 &X86::GR64RegClass, 3266 &X86::GR64_with_sub_8bitRegClass, 3267 &X86::GR64_NOREXRegClass, 3268 NULL 3269 }; 3270 3271 static const TargetRegisterClass* const GR32_NOREX_NOSPSuperclasses[] = { 3272 &X86::GR32RegClass, 3273 &X86::GR32_NOSPRegClass, 3274 &X86::GR32_NOREXRegClass, 3275 NULL 3276 }; 3277 3278 static const TargetRegisterClass* const RFP64Superclasses[] = { 3279 &X86::RFP32RegClass, 3280 NULL 3281 }; 3282 3283 static const TargetRegisterClass* const GR64_NOREX_NOSPSuperclasses[] = { 3284 &X86::GR64RegClass, 3285 &X86::GR64_with_sub_8bitRegClass, 3286 &X86::GR64_NOSPRegClass, 3287 &X86::GR64_NOREXRegClass, 3288 &X86::GR64_NOREX_with_sub_8bitRegClass, 3289 NULL 3290 }; 3291 3292 static const TargetRegisterClass* const RFP80Superclasses[] = { 3293 &X86::RFP32RegClass, 3294 &X86::RFP64RegClass, 3295 NULL 3296 }; 3297 3298 static const TargetRegisterClass* const GR64_TCW64Superclasses[] = { 3299 &X86::GR64RegClass, 3300 &X86::GR64_with_sub_8bitRegClass, 3301 &X86::GR64_NOSPRegClass, 3302 &X86::GR64_TCRegClass, 3303 &X86::GR64_TC_with_sub_8bitRegClass, 3304 NULL 3305 }; 3306 3307 static const TargetRegisterClass* const GR8_ABCD_LSuperclasses[] = { 3308 &X86::GR8RegClass, 3309 &X86::GR8_NOREXRegClass, 3310 NULL 3311 }; 3312 3313 static const TargetRegisterClass* const GR8_ABCD_HSuperclasses[] = { 3314 &X86::GR8RegClass, 3315 &X86::GR8_NOREXRegClass, 3316 NULL 3317 }; 3318 3319 static const TargetRegisterClass* const GR16_ABCDSuperclasses[] = { 3320 &X86::GR16RegClass, 3321 &X86::GR16_NOREXRegClass, 3322 NULL 3323 }; 3324 3325 static const TargetRegisterClass* const GR32_ABCDSuperclasses[] = { 3326 &X86::GR32RegClass, 3327 &X86::GR32_NOSPRegClass, 3328 &X86::GR32_NOREXRegClass, 3329 &X86::GR32_NOREX_NOSPRegClass, 3330 NULL 3331 }; 3332 3333 static const TargetRegisterClass* const GR64_ABCDSuperclasses[] = { 3334 &X86::GR64RegClass, 3335 &X86::GR64_with_sub_8bitRegClass, 3336 &X86::GR64_NOSPRegClass, 3337 &X86::GR64_NOREXRegClass, 3338 &X86::GR64_NOREX_with_sub_8bitRegClass, 3339 &X86::GR64_NOREX_NOSPRegClass, 3340 NULL 3341 }; 3342 3343 static const TargetRegisterClass* const GR32_TCSuperclasses[] = { 3344 &X86::GR32RegClass, 3345 &X86::GR32_NOSPRegClass, 3346 &X86::GR32_NOREXRegClass, 3347 &X86::GR32_NOREX_NOSPRegClass, 3348 &X86::GR32_ABCDRegClass, 3349 NULL 3350 }; 3351 3352 static const TargetRegisterClass* const GR32_NOAX_with_sub_8bit_hiSuperclasses[] = { 3353 &X86::GR32RegClass, 3354 &X86::GR32_NOSPRegClass, 3355 &X86::GR32_NOAXRegClass, 3356 &X86::GR32_NOREXRegClass, 3357 &X86::GR32_NOREX_NOSPRegClass, 3358 &X86::GR32_ABCDRegClass, 3359 NULL 3360 }; 3361 3362 static const TargetRegisterClass* const GR64_TC_with_sub_8bit_hiSuperclasses[] = { 3363 &X86::GR64RegClass, 3364 &X86::GR64_with_sub_8bitRegClass, 3365 &X86::GR64_NOSPRegClass, 3366 &X86::GR64_TCRegClass, 3367 &X86::GR64_NOREXRegClass, 3368 &X86::GR64_TC_with_sub_8bitRegClass, 3369 &X86::GR64_NOREX_with_sub_8bitRegClass, 3370 &X86::GR64_NOREX_NOSPRegClass, 3371 &X86::GR64_TCW64RegClass, 3372 &X86::GR64_ABCDRegClass, 3373 NULL 3374 }; 3375 3376 static const TargetRegisterClass* const GR32_ADSuperclasses[] = { 3377 &X86::GR32RegClass, 3378 &X86::GR32_NOSPRegClass, 3379 &X86::GR32_NOREXRegClass, 3380 &X86::GR32_NOREX_NOSPRegClass, 3381 &X86::GR32_ABCDRegClass, 3382 &X86::GR32_TCRegClass, 3383 NULL 3384 }; 3385 3386GR8Class::GR8Class() : TargetRegisterClass(&X86MCRegisterClasses[GR8RegClassID], GR8VTs, GR8SubclassMask, NullRegClasses, GR8SuperRegClasses) {} 3387 3388static inline unsigned GR8AltOrderSelect(const MachineFunction &MF) { 3389 3390 return MF.getTarget().getSubtarget<X86Subtarget>().is64Bit(); 3391 3392 } 3393 3394ArrayRef<unsigned> GR8Class::getRawAllocationOrder(const MachineFunction &MF) const { 3395 static const unsigned AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B }; 3396 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID]; static const ArrayRef<unsigned> Order[] = { 3397 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 3398 makeArrayRef(AltOrder1) 3399 }; 3400 const unsigned Select = GR8AltOrderSelect(MF); 3401 assert(Select < 2); 3402 return Order[Select]; 3403} 3404GR64Class::GR64Class() : TargetRegisterClass(&X86MCRegisterClasses[GR64RegClassID], GR64VTs, GR64SubclassMask, NullRegClasses, GR64SuperRegClasses) {} 3405GR16Class::GR16Class() : TargetRegisterClass(&X86MCRegisterClasses[GR16RegClassID], GR16VTs, GR16SubclassMask, NullRegClasses, GR16SuperRegClasses) {} 3406GR32Class::GR32Class() : TargetRegisterClass(&X86MCRegisterClasses[GR32RegClassID], GR32VTs, GR32SubclassMask, NullRegClasses, GR32SuperRegClasses) {} 3407FR32Class::FR32Class() : TargetRegisterClass(&X86MCRegisterClasses[FR32RegClassID], FR32VTs, FR32SubclassMask, NullRegClasses, FR32SuperRegClasses) {} 3408GR64_with_sub_8bitClass::GR64_with_sub_8bitClass() : TargetRegisterClass(&X86MCRegisterClasses[GR64_with_sub_8bitRegClassID], GR64_with_sub_8bitVTs, GR64_with_sub_8bitSubclassMask, GR64_with_sub_8bitSuperclasses, GR64_with_sub_8bitSuperRegClasses) {} 3409FR64Class::FR64Class() : TargetRegisterClass(&X86MCRegisterClasses[FR64RegClassID], FR64VTs, FR64SubclassMask, FR64Superclasses, FR64SuperRegClasses) {} 3410CONTROL_REGClass::CONTROL_REGClass() : TargetRegisterClass(&X86MCRegisterClasses[CONTROL_REGRegClassID], CONTROL_REGVTs, CONTROL_REGSubclassMask, NullRegClasses, CONTROL_REGSuperRegClasses) {} 3411VR128Class::VR128Class() : TargetRegisterClass(&X86MCRegisterClasses[VR128RegClassID], VR128VTs, VR128SubclassMask, VR128Superclasses, VR128SuperRegClasses) {} 3412VR256Class::VR256Class() : TargetRegisterClass(&X86MCRegisterClasses[VR256RegClassID], VR256VTs, VR256SubclassMask, NullRegClasses, VR256SuperRegClasses) {} 3413GR32_NOSPClass::GR32_NOSPClass() : TargetRegisterClass(&X86MCRegisterClasses[GR32_NOSPRegClassID], GR32_NOSPVTs, GR32_NOSPSubclassMask, GR32_NOSPSuperclasses, GR32_NOSPSuperRegClasses) {} 3414GR32_NOAXClass::GR32_NOAXClass() : TargetRegisterClass(&X86MCRegisterClasses[GR32_NOAXRegClassID], GR32_NOAXVTs, GR32_NOAXSubclassMask, GR32_NOAXSuperclasses, GR32_NOAXSuperRegClasses) {} 3415GR64_NOSPClass::GR64_NOSPClass() : TargetRegisterClass(&X86MCRegisterClasses[GR64_NOSPRegClassID], GR64_NOSPVTs, GR64_NOSPSubclassMask, GR64_NOSPSuperclasses, GR64_NOSPSuperRegClasses) {} 3416GR64_TCClass::GR64_TCClass() : TargetRegisterClass(&X86MCRegisterClasses[GR64_TCRegClassID], GR64_TCVTs, GR64_TCSubclassMask, GR64_TCSuperclasses, GR64_TCSuperRegClasses) {} 3417GR64_NOREXClass::GR64_NOREXClass() : TargetRegisterClass(&X86MCRegisterClasses[GR64_NOREXRegClassID], GR64_NOREXVTs, GR64_NOREXSubclassMask, GR64_NOREXSuperclasses, GR64_NOREXSuperRegClasses) {} 3418GR8_NOREXClass::GR8_NOREXClass() : TargetRegisterClass(&X86MCRegisterClasses[GR8_NOREXRegClassID], GR8_NOREXVTs, GR8_NOREXSubclassMask, GR8_NOREXSuperclasses, GR8_NOREXSuperRegClasses) {} 3419 3420static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF) { 3421 3422 return MF.getTarget().getSubtarget<X86Subtarget>().is64Bit(); 3423 3424 } 3425 3426ArrayRef<unsigned> GR8_NOREXClass::getRawAllocationOrder(const MachineFunction &MF) const { 3427 static const unsigned AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL }; 3428 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID]; static const ArrayRef<unsigned> Order[] = { 3429 makeArrayRef(MCR.begin(), MCR.getNumRegs()), 3430 makeArrayRef(AltOrder1) 3431 }; 3432 const unsigned Select = GR8_NOREXAltOrderSelect(MF); 3433 assert(Select < 2); 3434 return Order[Select]; 3435} 3436GR16_NOREXClass::GR16_NOREXClass() : TargetRegisterClass(&X86MCRegisterClasses[GR16_NOREXRegClassID], GR16_NOREXVTs, GR16_NOREXSubclassMask, GR16_NOREXSuperclasses, GR16_NOREXSuperRegClasses) {} 3437GR32_NOREXClass::GR32_NOREXClass() : TargetRegisterClass(&X86MCRegisterClasses[GR32_NOREXRegClassID], GR32_NOREXVTs, GR32_NOREXSubclassMask, GR32_NOREXSuperclasses, GR32_NOREXSuperRegClasses) {} 3438DEBUG_REGClass::DEBUG_REGClass() : TargetRegisterClass(&X86MCRegisterClasses[DEBUG_REGRegClassID], DEBUG_REGVTs, DEBUG_REGSubclassMask, NullRegClasses, DEBUG_REGSuperRegClasses) {} 3439VR64Class::VR64Class() : TargetRegisterClass(&X86MCRegisterClasses[VR64RegClassID], VR64VTs, VR64SubclassMask, NullRegClasses, VR64SuperRegClasses) {} 3440GR64_TC_with_sub_8bitClass::GR64_TC_with_sub_8bitClass() : TargetRegisterClass(&X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID], GR64_TC_with_sub_8bitVTs, GR64_TC_with_sub_8bitSubclassMask, GR64_TC_with_sub_8bitSuperclasses, GR64_TC_with_sub_8bitSuperRegClasses) {} 3441GR64_NOREX_with_sub_8bitClass::GR64_NOREX_with_sub_8bitClass() : TargetRegisterClass(&X86MCRegisterClasses[GR64_NOREX_with_sub_8bitRegClassID], GR64_NOREX_with_sub_8bitVTs, GR64_NOREX_with_sub_8bitSubclassMask, GR64_NOREX_with_sub_8bitSuperclasses, GR64_NOREX_with_sub_8bitSuperRegClasses) {} 3442RSTClass::RSTClass() : TargetRegisterClass(&X86MCRegisterClasses[RSTRegClassID], RSTVTs, RSTSubclassMask, NullRegClasses, RSTSuperRegClasses) {} 3443RFP32Class::RFP32Class() : TargetRegisterClass(&X86MCRegisterClasses[RFP32RegClassID], RFP32VTs, RFP32SubclassMask, NullRegClasses, RFP32SuperRegClasses) {} 3444GR32_NOREX_NOSPClass::GR32_NOREX_NOSPClass() : TargetRegisterClass(&X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID], GR32_NOREX_NOSPVTs, GR32_NOREX_NOSPSubclassMask, GR32_NOREX_NOSPSuperclasses, GR32_NOREX_NOSPSuperRegClasses) {} 3445RFP64Class::RFP64Class() : TargetRegisterClass(&X86MCRegisterClasses[RFP64RegClassID], RFP64VTs, RFP64SubclassMask, RFP64Superclasses, RFP64SuperRegClasses) {} 3446GR64_NOREX_NOSPClass::GR64_NOREX_NOSPClass() : TargetRegisterClass(&X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID], GR64_NOREX_NOSPVTs, GR64_NOREX_NOSPSubclassMask, GR64_NOREX_NOSPSuperclasses, GR64_NOREX_NOSPSuperRegClasses) {} 3447RFP80Class::RFP80Class() : TargetRegisterClass(&X86MCRegisterClasses[RFP80RegClassID], RFP80VTs, RFP80SubclassMask, RFP80Superclasses, RFP80SuperRegClasses) {} 3448SEGMENT_REGClass::SEGMENT_REGClass() : TargetRegisterClass(&X86MCRegisterClasses[SEGMENT_REGRegClassID], SEGMENT_REGVTs, SEGMENT_REGSubclassMask, NullRegClasses, SEGMENT_REGSuperRegClasses) {} 3449GR64_TCW64Class::GR64_TCW64Class() : TargetRegisterClass(&X86MCRegisterClasses[GR64_TCW64RegClassID], GR64_TCW64VTs, GR64_TCW64SubclassMask, GR64_TCW64Superclasses, GR64_TCW64SuperRegClasses) {} 3450GR8_ABCD_LClass::GR8_ABCD_LClass() : TargetRegisterClass(&X86MCRegisterClasses[GR8_ABCD_LRegClassID], GR8_ABCD_LVTs, GR8_ABCD_LSubclassMask, GR8_ABCD_LSuperclasses, GR8_ABCD_LSuperRegClasses) {} 3451GR8_ABCD_HClass::GR8_ABCD_HClass() : TargetRegisterClass(&X86MCRegisterClasses[GR8_ABCD_HRegClassID], GR8_ABCD_HVTs, GR8_ABCD_HSubclassMask, GR8_ABCD_HSuperclasses, GR8_ABCD_HSuperRegClasses) {} 3452GR16_ABCDClass::GR16_ABCDClass() : TargetRegisterClass(&X86MCRegisterClasses[GR16_ABCDRegClassID], GR16_ABCDVTs, GR16_ABCDSubclassMask, GR16_ABCDSuperclasses, GR16_ABCDSuperRegClasses) {} 3453GR32_ABCDClass::GR32_ABCDClass() : TargetRegisterClass(&X86MCRegisterClasses[GR32_ABCDRegClassID], GR32_ABCDVTs, GR32_ABCDSubclassMask, GR32_ABCDSuperclasses, GR32_ABCDSuperRegClasses) {} 3454GR64_ABCDClass::GR64_ABCDClass() : TargetRegisterClass(&X86MCRegisterClasses[GR64_ABCDRegClassID], GR64_ABCDVTs, GR64_ABCDSubclassMask, GR64_ABCDSuperclasses, GR64_ABCDSuperRegClasses) {} 3455GR32_TCClass::GR32_TCClass() : TargetRegisterClass(&X86MCRegisterClasses[GR32_TCRegClassID], GR32_TCVTs, GR32_TCSubclassMask, GR32_TCSuperclasses, GR32_TCSuperRegClasses) {} 3456GR32_NOAX_with_sub_8bit_hiClass::GR32_NOAX_with_sub_8bit_hiClass() : TargetRegisterClass(&X86MCRegisterClasses[GR32_NOAX_with_sub_8bit_hiRegClassID], GR32_NOAX_with_sub_8bit_hiVTs, GR32_NOAX_with_sub_8bit_hiSubclassMask, GR32_NOAX_with_sub_8bit_hiSuperclasses, GR32_NOAX_with_sub_8bit_hiSuperRegClasses) {} 3457GR64_TC_with_sub_8bit_hiClass::GR64_TC_with_sub_8bit_hiClass() : TargetRegisterClass(&X86MCRegisterClasses[GR64_TC_with_sub_8bit_hiRegClassID], GR64_TC_with_sub_8bit_hiVTs, GR64_TC_with_sub_8bit_hiSubclassMask, GR64_TC_with_sub_8bit_hiSuperclasses, GR64_TC_with_sub_8bit_hiSuperRegClasses) {} 3458GR32_ADClass::GR32_ADClass() : TargetRegisterClass(&X86MCRegisterClasses[GR32_ADRegClassID], GR32_ADVTs, GR32_ADSubclassMask, GR32_ADSuperclasses, GR32_ADSuperRegClasses) {} 3459CCRClass::CCRClass() : TargetRegisterClass(&X86MCRegisterClasses[CCRRegClassID], CCRVTs, CCRSubclassMask, NullRegClasses, CCRSuperRegClasses) {} 3460} 3461 3462namespace { 3463 const TargetRegisterClass* const RegisterClasses[] = { 3464 &X86::GR8RegClass, 3465 &X86::GR64RegClass, 3466 &X86::GR16RegClass, 3467 &X86::GR32RegClass, 3468 &X86::FR32RegClass, 3469 &X86::GR64_with_sub_8bitRegClass, 3470 &X86::FR64RegClass, 3471 &X86::CONTROL_REGRegClass, 3472 &X86::VR128RegClass, 3473 &X86::VR256RegClass, 3474 &X86::GR32_NOSPRegClass, 3475 &X86::GR32_NOAXRegClass, 3476 &X86::GR64_NOSPRegClass, 3477 &X86::GR64_TCRegClass, 3478 &X86::GR64_NOREXRegClass, 3479 &X86::GR8_NOREXRegClass, 3480 &X86::GR16_NOREXRegClass, 3481 &X86::GR32_NOREXRegClass, 3482 &X86::DEBUG_REGRegClass, 3483 &X86::VR64RegClass, 3484 &X86::GR64_TC_with_sub_8bitRegClass, 3485 &X86::GR64_NOREX_with_sub_8bitRegClass, 3486 &X86::RSTRegClass, 3487 &X86::RFP32RegClass, 3488 &X86::GR32_NOREX_NOSPRegClass, 3489 &X86::RFP64RegClass, 3490 &X86::GR64_NOREX_NOSPRegClass, 3491 &X86::RFP80RegClass, 3492 &X86::SEGMENT_REGRegClass, 3493 &X86::GR64_TCW64RegClass, 3494 &X86::GR8_ABCD_LRegClass, 3495 &X86::GR8_ABCD_HRegClass, 3496 &X86::GR16_ABCDRegClass, 3497 &X86::GR32_ABCDRegClass, 3498 &X86::GR64_ABCDRegClass, 3499 &X86::GR32_TCRegClass, 3500 &X86::GR32_NOAX_with_sub_8bit_hiRegClass, 3501 &X86::GR64_TC_with_sub_8bit_hiRegClass, 3502 &X86::GR32_ADRegClass, 3503 &X86::CCRRegClass, 3504 }; 3505} 3506 3507 static const TargetRegisterInfoDesc X86RegInfoDesc[] = { // Extra Descriptors 3508 { 0, 0 }, 3509 { 0, 1 }, 3510 { 0, 1 }, 3511 { 0, 1 }, 3512 { 0, 1 }, 3513 { 0, 1 }, 3514 { 0, 1 }, 3515 { 1, 1 }, 3516 { 0, 1 }, 3517 { 0, 1 }, 3518 { 0, 1 }, 3519 { 0, 1 }, 3520 { 0, 1 }, 3521 { 0, 1 }, 3522 { 0, 1 }, 3523 { 0, 1 }, 3524 { 0, 1 }, 3525 { 0, 1 }, 3526 { 0, 1 }, 3527 { 0, 1 }, 3528 { 0, 1 }, 3529 { 0, 1 }, 3530 { 0, 1 }, 3531 { 0, 1 }, 3532 { 0, 1 }, 3533 { 0, 1 }, 3534 { 0, 1 }, 3535 { 0, 1 }, 3536 { 0, 1 }, 3537 { 0, 1 }, 3538 { 0, 1 }, 3539 { 1, 1 }, 3540 { 0, 1 }, 3541 { 0, 1 }, 3542 { 0, 1 }, 3543 { 0, 1 }, 3544 { 0, 1 }, 3545 { 0, 1 }, 3546 { 0, 1 }, 3547 { 0, 1 }, 3548 { 0, 1 }, 3549 { 0, 1 }, 3550 { 0, 1 }, 3551 { 0, 1 }, 3552 { 0, 1 }, 3553 { 0, 1 }, 3554 { 0, 1 }, 3555 { 0, 1 }, 3556 { 0, 1 }, 3557 { 0, 0 }, 3558 { 0, 0 }, 3559 { 0, 0 }, 3560 { 0, 1 }, 3561 { 0, 1 }, 3562 { 0, 1 }, 3563 { 0, 1 }, 3564 { 0, 1 }, 3565 { 0, 1 }, 3566 { 0, 1 }, 3567 { 0, 1 }, 3568 { 0, 1 }, 3569 { 0, 1 }, 3570 { 0, 1 }, 3571 { 0, 1 }, 3572 { 0, 0 }, 3573 { 0, 1 }, 3574 { 0, 1 }, 3575 { 0, 1 }, 3576 { 0, 1 }, 3577 { 0, 1 }, 3578 { 0, 1 }, 3579 { 0, 1 }, 3580 { 0, 1 }, 3581 { 1, 1 }, 3582 { 1, 1 }, 3583 { 1, 1 }, 3584 { 1, 1 }, 3585 { 1, 1 }, 3586 { 1, 1 }, 3587 { 1, 1 }, 3588 { 1, 1 }, 3589 { 1, 1 }, 3590 { 1, 1 }, 3591 { 1, 1 }, 3592 { 1, 1 }, 3593 { 1, 1 }, 3594 { 1, 1 }, 3595 { 1, 1 }, 3596 { 1, 1 }, 3597 { 1, 1 }, 3598 { 1, 1 }, 3599 { 1, 1 }, 3600 { 1, 1 }, 3601 { 1, 1 }, 3602 { 1, 1 }, 3603 { 1, 1 }, 3604 { 1, 1 }, 3605 { 1, 1 }, 3606 { 1, 1 }, 3607 { 1, 1 }, 3608 { 1, 1 }, 3609 { 1, 1 }, 3610 { 1, 1 }, 3611 { 1, 1 }, 3612 { 1, 1 }, 3613 { 0, 1 }, 3614 { 0, 1 }, 3615 { 0, 1 }, 3616 { 0, 1 }, 3617 { 0, 1 }, 3618 { 0, 1 }, 3619 { 1, 1 }, 3620 { 0, 0 }, 3621 { 0, 1 }, 3622 { 0, 1 }, 3623 { 0, 1 }, 3624 { 1, 1 }, 3625 { 0, 1 }, 3626 { 1, 1 }, 3627 { 0, 1 }, 3628 { 0, 0 }, 3629 { 0, 0 }, 3630 { 0, 0 }, 3631 { 0, 0 }, 3632 { 0, 0 }, 3633 { 0, 0 }, 3634 { 0, 0 }, 3635 { 0, 0 }, 3636 { 0, 1 }, 3637 { 0, 1 }, 3638 { 0, 1 }, 3639 { 0, 1 }, 3640 { 0, 1 }, 3641 { 0, 1 }, 3642 { 0, 1 }, 3643 { 0, 1 }, 3644 { 1, 1 }, 3645 { 1, 1 }, 3646 { 1, 1 }, 3647 { 1, 1 }, 3648 { 1, 1 }, 3649 { 1, 1 }, 3650 { 1, 1 }, 3651 { 1, 1 }, 3652 { 0, 1 }, 3653 { 0, 1 }, 3654 { 0, 1 }, 3655 { 0, 1 }, 3656 { 0, 1 }, 3657 { 0, 1 }, 3658 { 0, 1 }, 3659 { 0, 1 }, 3660 { 0, 1 }, 3661 { 0, 1 }, 3662 { 0, 1 }, 3663 { 0, 1 }, 3664 { 0, 1 }, 3665 { 0, 1 }, 3666 { 0, 1 }, 3667 { 0, 1 }, 3668 }; 3669 3670 static const char *const X86SubRegIndexTable[] = { "sub_8bit", "sub_8bit_hi", "sub_16bit", "sub_32bit", "sub_sd", "sub_ss", "sub_xmm" }; 3671 3672 3673unsigned X86GenRegisterInfo::getSubReg(unsigned RegNo, unsigned Index) const { 3674 switch (RegNo) { 3675 default: 3676 return 0; 3677 case X86::AX: 3678 switch (Index) { 3679 default: return 0; 3680 case X86::sub_8bit: return X86::AL; 3681 case X86::sub_8bit_hi: return X86::AH; 3682 }; 3683 break; 3684 case X86::BP: 3685 switch (Index) { 3686 default: return 0; 3687 case X86::sub_8bit: return X86::BPL; 3688 }; 3689 break; 3690 case X86::BX: 3691 switch (Index) { 3692 default: return 0; 3693 case X86::sub_8bit: return X86::BL; 3694 case X86::sub_8bit_hi: return X86::BH; 3695 }; 3696 break; 3697 case X86::CX: 3698 switch (Index) { 3699 default: return 0; 3700 case X86::sub_8bit: return X86::CL; 3701 case X86::sub_8bit_hi: return X86::CH; 3702 }; 3703 break; 3704 case X86::DI: 3705 switch (Index) { 3706 default: return 0; 3707 case X86::sub_8bit: return X86::DIL; 3708 }; 3709 break; 3710 case X86::DX: 3711 switch (Index) { 3712 default: return 0; 3713 case X86::sub_8bit: return X86::DL; 3714 case X86::sub_8bit_hi: return X86::DH; 3715 }; 3716 break; 3717 case X86::EAX: 3718 switch (Index) { 3719 default: return 0; 3720 case X86::sub_8bit: return X86::AL; 3721 case X86::sub_8bit_hi: return X86::AH; 3722 case X86::sub_16bit: return X86::AX; 3723 }; 3724 break; 3725 case X86::EBP: 3726 switch (Index) { 3727 default: return 0; 3728 case X86::sub_8bit: return X86::BPL; 3729 case X86::sub_16bit: return X86::BP; 3730 }; 3731 break; 3732 case X86::EBX: 3733 switch (Index) { 3734 default: return 0; 3735 case X86::sub_8bit: return X86::BL; 3736 case X86::sub_8bit_hi: return X86::BH; 3737 case X86::sub_16bit: return X86::BX; 3738 }; 3739 break; 3740 case X86::ECX: 3741 switch (Index) { 3742 default: return 0; 3743 case X86::sub_8bit: return X86::CL; 3744 case X86::sub_8bit_hi: return X86::CH; 3745 case X86::sub_16bit: return X86::CX; 3746 }; 3747 break; 3748 case X86::EDI: 3749 switch (Index) { 3750 default: return 0; 3751 case X86::sub_8bit: return X86::DIL; 3752 case X86::sub_16bit: return X86::DI; 3753 }; 3754 break; 3755 case X86::EDX: 3756 switch (Index) { 3757 default: return 0; 3758 case X86::sub_8bit: return X86::DL; 3759 case X86::sub_8bit_hi: return X86::DH; 3760 case X86::sub_16bit: return X86::DX; 3761 }; 3762 break; 3763 case X86::EIP: 3764 switch (Index) { 3765 default: return 0; 3766 case X86::sub_16bit: return X86::IP; 3767 }; 3768 break; 3769 case X86::ESI: 3770 switch (Index) { 3771 default: return 0; 3772 case X86::sub_8bit: return X86::SIL; 3773 case X86::sub_16bit: return X86::SI; 3774 }; 3775 break; 3776 case X86::ESP: 3777 switch (Index) { 3778 default: return 0; 3779 case X86::sub_8bit: return X86::SPL; 3780 case X86::sub_16bit: return X86::SP; 3781 }; 3782 break; 3783 case X86::R8: 3784 switch (Index) { 3785 default: return 0; 3786 case X86::sub_8bit: return X86::R8B; 3787 case X86::sub_16bit: return X86::R8W; 3788 case X86::sub_32bit: return X86::R8D; 3789 }; 3790 break; 3791 case X86::R8D: 3792 switch (Index) { 3793 default: return 0; 3794 case X86::sub_8bit: return X86::R8B; 3795 case X86::sub_16bit: return X86::R8W; 3796 }; 3797 break; 3798 case X86::R8W: 3799 switch (Index) { 3800 default: return 0; 3801 case X86::sub_8bit: return X86::R8B; 3802 }; 3803 break; 3804 case X86::R9: 3805 switch (Index) { 3806 default: return 0; 3807 case X86::sub_8bit: return X86::R9B; 3808 case X86::sub_16bit: return X86::R9W; 3809 case X86::sub_32bit: return X86::R9D; 3810 }; 3811 break; 3812 case X86::R9D: 3813 switch (Index) { 3814 default: return 0; 3815 case X86::sub_8bit: return X86::R9B; 3816 case X86::sub_16bit: return X86::R9W; 3817 }; 3818 break; 3819 case X86::R9W: 3820 switch (Index) { 3821 default: return 0; 3822 case X86::sub_8bit: return X86::R9B; 3823 }; 3824 break; 3825 case X86::R10: 3826 switch (Index) { 3827 default: return 0; 3828 case X86::sub_8bit: return X86::R10B; 3829 case X86::sub_16bit: return X86::R10W; 3830 case X86::sub_32bit: return X86::R10D; 3831 }; 3832 break; 3833 case X86::R10D: 3834 switch (Index) { 3835 default: return 0; 3836 case X86::sub_8bit: return X86::R10B; 3837 case X86::sub_16bit: return X86::R10W; 3838 }; 3839 break; 3840 case X86::R10W: 3841 switch (Index) { 3842 default: return 0; 3843 case X86::sub_8bit: return X86::R10B; 3844 }; 3845 break; 3846 case X86::R11: 3847 switch (Index) { 3848 default: return 0; 3849 case X86::sub_8bit: return X86::R11B; 3850 case X86::sub_16bit: return X86::R11W; 3851 case X86::sub_32bit: return X86::R11D; 3852 }; 3853 break; 3854 case X86::R11D: 3855 switch (Index) { 3856 default: return 0; 3857 case X86::sub_8bit: return X86::R11B; 3858 case X86::sub_16bit: return X86::R11W; 3859 }; 3860 break; 3861 case X86::R11W: 3862 switch (Index) { 3863 default: return 0; 3864 case X86::sub_8bit: return X86::R11B; 3865 }; 3866 break; 3867 case X86::R12: 3868 switch (Index) { 3869 default: return 0; 3870 case X86::sub_8bit: return X86::R12B; 3871 case X86::sub_16bit: return X86::R12W; 3872 case X86::sub_32bit: return X86::R12D; 3873 }; 3874 break; 3875 case X86::R12D: 3876 switch (Index) { 3877 default: return 0; 3878 case X86::sub_8bit: return X86::R12B; 3879 case X86::sub_16bit: return X86::R12W; 3880 }; 3881 break; 3882 case X86::R12W: 3883 switch (Index) { 3884 default: return 0; 3885 case X86::sub_8bit: return X86::R12B; 3886 }; 3887 break; 3888 case X86::R13: 3889 switch (Index) { 3890 default: return 0; 3891 case X86::sub_8bit: return X86::R13B; 3892 case X86::sub_16bit: return X86::R13W; 3893 case X86::sub_32bit: return X86::R13D; 3894 }; 3895 break; 3896 case X86::R13D: 3897 switch (Index) { 3898 default: return 0; 3899 case X86::sub_8bit: return X86::R13B; 3900 case X86::sub_16bit: return X86::R13W; 3901 }; 3902 break; 3903 case X86::R13W: 3904 switch (Index) { 3905 default: return 0; 3906 case X86::sub_8bit: return X86::R13B; 3907 }; 3908 break; 3909 case X86::R14: 3910 switch (Index) { 3911 default: return 0; 3912 case X86::sub_8bit: return X86::R14B; 3913 case X86::sub_16bit: return X86::R14W; 3914 case X86::sub_32bit: return X86::R14D; 3915 }; 3916 break; 3917 case X86::R14D: 3918 switch (Index) { 3919 default: return 0; 3920 case X86::sub_8bit: return X86::R14B; 3921 case X86::sub_16bit: return X86::R14W; 3922 }; 3923 break; 3924 case X86::R14W: 3925 switch (Index) { 3926 default: return 0; 3927 case X86::sub_8bit: return X86::R14B; 3928 }; 3929 break; 3930 case X86::R15: 3931 switch (Index) { 3932 default: return 0; 3933 case X86::sub_8bit: return X86::R15B; 3934 case X86::sub_16bit: return X86::R15W; 3935 case X86::sub_32bit: return X86::R15D; 3936 }; 3937 break; 3938 case X86::R15D: 3939 switch (Index) { 3940 default: return 0; 3941 case X86::sub_8bit: return X86::R15B; 3942 case X86::sub_16bit: return X86::R15W; 3943 }; 3944 break; 3945 case X86::R15W: 3946 switch (Index) { 3947 default: return 0; 3948 case X86::sub_8bit: return X86::R15B; 3949 }; 3950 break; 3951 case X86::RAX: 3952 switch (Index) { 3953 default: return 0; 3954 case X86::sub_8bit: return X86::AL; 3955 case X86::sub_8bit_hi: return X86::AH; 3956 case X86::sub_16bit: return X86::AX; 3957 case X86::sub_32bit: return X86::EAX; 3958 }; 3959 break; 3960 case X86::RBP: 3961 switch (Index) { 3962 default: return 0; 3963 case X86::sub_8bit: return X86::BPL; 3964 case X86::sub_16bit: return X86::BP; 3965 case X86::sub_32bit: return X86::EBP; 3966 }; 3967 break; 3968 case X86::RBX: 3969 switch (Index) { 3970 default: return 0; 3971 case X86::sub_8bit: return X86::BL; 3972 case X86::sub_8bit_hi: return X86::BH; 3973 case X86::sub_16bit: return X86::BX; 3974 case X86::sub_32bit: return X86::EBX; 3975 }; 3976 break; 3977 case X86::RCX: 3978 switch (Index) { 3979 default: return 0; 3980 case X86::sub_8bit: return X86::CL; 3981 case X86::sub_8bit_hi: return X86::CH; 3982 case X86::sub_16bit: return X86::CX; 3983 case X86::sub_32bit: return X86::ECX; 3984 }; 3985 break; 3986 case X86::RDI: 3987 switch (Index) { 3988 default: return 0; 3989 case X86::sub_8bit: return X86::DIL; 3990 case X86::sub_16bit: return X86::DI; 3991 case X86::sub_32bit: return X86::EDI; 3992 }; 3993 break; 3994 case X86::RDX: 3995 switch (Index) { 3996 default: return 0; 3997 case X86::sub_8bit: return X86::DL; 3998 case X86::sub_8bit_hi: return X86::DH; 3999 case X86::sub_16bit: return X86::DX; 4000 case X86::sub_32bit: return X86::EDX; 4001 }; 4002 break; 4003 case X86::RIP: 4004 switch (Index) { 4005 default: return 0; 4006 case X86::sub_16bit: return X86::IP; 4007 case X86::sub_32bit: return X86::EIP; 4008 }; 4009 break; 4010 case X86::RSI: 4011 switch (Index) { 4012 default: return 0; 4013 case X86::sub_8bit: return X86::SIL; 4014 case X86::sub_16bit: return X86::SI; 4015 case X86::sub_32bit: return X86::ESI; 4016 }; 4017 break; 4018 case X86::RSP: 4019 switch (Index) { 4020 default: return 0; 4021 case X86::sub_8bit: return X86::SPL; 4022 case X86::sub_16bit: return X86::SP; 4023 case X86::sub_32bit: return X86::ESP; 4024 }; 4025 break; 4026 case X86::SI: 4027 switch (Index) { 4028 default: return 0; 4029 case X86::sub_8bit: return X86::SIL; 4030 }; 4031 break; 4032 case X86::SP: 4033 switch (Index) { 4034 default: return 0; 4035 case X86::sub_8bit: return X86::SPL; 4036 }; 4037 break; 4038 case X86::XMM0: 4039 switch (Index) { 4040 default: return 0; 4041 case X86::sub_sd: return X86::XMM0; 4042 case X86::sub_ss: return X86::XMM0; 4043 }; 4044 break; 4045 case X86::XMM1: 4046 switch (Index) { 4047 default: return 0; 4048 case X86::sub_sd: return X86::XMM1; 4049 case X86::sub_ss: return X86::XMM1; 4050 }; 4051 break; 4052 case X86::XMM2: 4053 switch (Index) { 4054 default: return 0; 4055 case X86::sub_sd: return X86::XMM2; 4056 case X86::sub_ss: return X86::XMM2; 4057 }; 4058 break; 4059 case X86::XMM3: 4060 switch (Index) { 4061 default: return 0; 4062 case X86::sub_sd: return X86::XMM3; 4063 case X86::sub_ss: return X86::XMM3; 4064 }; 4065 break; 4066 case X86::XMM4: 4067 switch (Index) { 4068 default: return 0; 4069 case X86::sub_sd: return X86::XMM4; 4070 case X86::sub_ss: return X86::XMM4; 4071 }; 4072 break; 4073 case X86::XMM5: 4074 switch (Index) { 4075 default: return 0; 4076 case X86::sub_sd: return X86::XMM5; 4077 case X86::sub_ss: return X86::XMM5; 4078 }; 4079 break; 4080 case X86::XMM6: 4081 switch (Index) { 4082 default: return 0; 4083 case X86::sub_sd: return X86::XMM6; 4084 case X86::sub_ss: return X86::XMM6; 4085 }; 4086 break; 4087 case X86::XMM7: 4088 switch (Index) { 4089 default: return 0; 4090 case X86::sub_sd: return X86::XMM7; 4091 case X86::sub_ss: return X86::XMM7; 4092 }; 4093 break; 4094 case X86::XMM8: 4095 switch (Index) { 4096 default: return 0; 4097 case X86::sub_sd: return X86::XMM8; 4098 case X86::sub_ss: return X86::XMM8; 4099 }; 4100 break; 4101 case X86::XMM9: 4102 switch (Index) { 4103 default: return 0; 4104 case X86::sub_sd: return X86::XMM9; 4105 case X86::sub_ss: return X86::XMM9; 4106 }; 4107 break; 4108 case X86::XMM10: 4109 switch (Index) { 4110 default: return 0; 4111 case X86::sub_sd: return X86::XMM10; 4112 case X86::sub_ss: return X86::XMM10; 4113 }; 4114 break; 4115 case X86::XMM11: 4116 switch (Index) { 4117 default: return 0; 4118 case X86::sub_sd: return X86::XMM11; 4119 case X86::sub_ss: return X86::XMM11; 4120 }; 4121 break; 4122 case X86::XMM12: 4123 switch (Index) { 4124 default: return 0; 4125 case X86::sub_sd: return X86::XMM12; 4126 case X86::sub_ss: return X86::XMM12; 4127 }; 4128 break; 4129 case X86::XMM13: 4130 switch (Index) { 4131 default: return 0; 4132 case X86::sub_sd: return X86::XMM13; 4133 case X86::sub_ss: return X86::XMM13; 4134 }; 4135 break; 4136 case X86::XMM14: 4137 switch (Index) { 4138 default: return 0; 4139 case X86::sub_sd: return X86::XMM14; 4140 case X86::sub_ss: return X86::XMM14; 4141 }; 4142 break; 4143 case X86::XMM15: 4144 switch (Index) { 4145 default: return 0; 4146 case X86::sub_sd: return X86::XMM15; 4147 case X86::sub_ss: return X86::XMM15; 4148 }; 4149 break; 4150 case X86::YMM0: 4151 switch (Index) { 4152 default: return 0; 4153 case X86::sub_sd: return X86::XMM0; 4154 case X86::sub_ss: return X86::XMM0; 4155 case X86::sub_xmm: return X86::XMM0; 4156 }; 4157 break; 4158 case X86::YMM1: 4159 switch (Index) { 4160 default: return 0; 4161 case X86::sub_sd: return X86::XMM1; 4162 case X86::sub_ss: return X86::XMM1; 4163 case X86::sub_xmm: return X86::XMM1; 4164 }; 4165 break; 4166 case X86::YMM2: 4167 switch (Index) { 4168 default: return 0; 4169 case X86::sub_sd: return X86::XMM2; 4170 case X86::sub_ss: return X86::XMM2; 4171 case X86::sub_xmm: return X86::XMM2; 4172 }; 4173 break; 4174 case X86::YMM3: 4175 switch (Index) { 4176 default: return 0; 4177 case X86::sub_sd: return X86::XMM3; 4178 case X86::sub_ss: return X86::XMM3; 4179 case X86::sub_xmm: return X86::XMM3; 4180 }; 4181 break; 4182 case X86::YMM4: 4183 switch (Index) { 4184 default: return 0; 4185 case X86::sub_sd: return X86::XMM4; 4186 case X86::sub_ss: return X86::XMM4; 4187 case X86::sub_xmm: return X86::XMM4; 4188 }; 4189 break; 4190 case X86::YMM5: 4191 switch (Index) { 4192 default: return 0; 4193 case X86::sub_sd: return X86::XMM5; 4194 case X86::sub_ss: return X86::XMM5; 4195 case X86::sub_xmm: return X86::XMM5; 4196 }; 4197 break; 4198 case X86::YMM6: 4199 switch (Index) { 4200 default: return 0; 4201 case X86::sub_sd: return X86::XMM6; 4202 case X86::sub_ss: return X86::XMM6; 4203 case X86::sub_xmm: return X86::XMM6; 4204 }; 4205 break; 4206 case X86::YMM7: 4207 switch (Index) { 4208 default: return 0; 4209 case X86::sub_sd: return X86::XMM7; 4210 case X86::sub_ss: return X86::XMM7; 4211 case X86::sub_xmm: return X86::XMM7; 4212 }; 4213 break; 4214 case X86::YMM8: 4215 switch (Index) { 4216 default: return 0; 4217 case X86::sub_sd: return X86::XMM8; 4218 case X86::sub_ss: return X86::XMM8; 4219 case X86::sub_xmm: return X86::XMM8; 4220 }; 4221 break; 4222 case X86::YMM9: 4223 switch (Index) { 4224 default: return 0; 4225 case X86::sub_sd: return X86::XMM9; 4226 case X86::sub_ss: return X86::XMM9; 4227 case X86::sub_xmm: return X86::XMM9; 4228 }; 4229 break; 4230 case X86::YMM10: 4231 switch (Index) { 4232 default: return 0; 4233 case X86::sub_sd: return X86::XMM10; 4234 case X86::sub_ss: return X86::XMM10; 4235 case X86::sub_xmm: return X86::XMM10; 4236 }; 4237 break; 4238 case X86::YMM11: 4239 switch (Index) { 4240 default: return 0; 4241 case X86::sub_sd: return X86::XMM11; 4242 case X86::sub_ss: return X86::XMM11; 4243 case X86::sub_xmm: return X86::XMM11; 4244 }; 4245 break; 4246 case X86::YMM12: 4247 switch (Index) { 4248 default: return 0; 4249 case X86::sub_sd: return X86::XMM12; 4250 case X86::sub_ss: return X86::XMM12; 4251 case X86::sub_xmm: return X86::XMM12; 4252 }; 4253 break; 4254 case X86::YMM13: 4255 switch (Index) { 4256 default: return 0; 4257 case X86::sub_sd: return X86::XMM13; 4258 case X86::sub_ss: return X86::XMM13; 4259 case X86::sub_xmm: return X86::XMM13; 4260 }; 4261 break; 4262 case X86::YMM14: 4263 switch (Index) { 4264 default: return 0; 4265 case X86::sub_sd: return X86::XMM14; 4266 case X86::sub_ss: return X86::XMM14; 4267 case X86::sub_xmm: return X86::XMM14; 4268 }; 4269 break; 4270 case X86::YMM15: 4271 switch (Index) { 4272 default: return 0; 4273 case X86::sub_sd: return X86::XMM15; 4274 case X86::sub_ss: return X86::XMM15; 4275 case X86::sub_xmm: return X86::XMM15; 4276 }; 4277 break; 4278 }; 4279 return 0; 4280} 4281 4282unsigned X86GenRegisterInfo::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const { 4283 switch (RegNo) { 4284 default: 4285 return 0; 4286 case X86::AX: 4287 if (SubRegNo == X86::AL) return X86::sub_8bit; 4288 if (SubRegNo == X86::AH) return X86::sub_8bit_hi; 4289 return 0; 4290 case X86::BP: 4291 if (SubRegNo == X86::BPL) return X86::sub_8bit; 4292 return 0; 4293 case X86::BX: 4294 if (SubRegNo == X86::BL) return X86::sub_8bit; 4295 if (SubRegNo == X86::BH) return X86::sub_8bit_hi; 4296 return 0; 4297 case X86::CX: 4298 if (SubRegNo == X86::CL) return X86::sub_8bit; 4299 if (SubRegNo == X86::CH) return X86::sub_8bit_hi; 4300 return 0; 4301 case X86::DI: 4302 if (SubRegNo == X86::DIL) return X86::sub_8bit; 4303 return 0; 4304 case X86::DX: 4305 if (SubRegNo == X86::DL) return X86::sub_8bit; 4306 if (SubRegNo == X86::DH) return X86::sub_8bit_hi; 4307 return 0; 4308 case X86::EAX: 4309 if (SubRegNo == X86::AL) return X86::sub_8bit; 4310 if (SubRegNo == X86::AH) return X86::sub_8bit_hi; 4311 if (SubRegNo == X86::AX) return X86::sub_16bit; 4312 return 0; 4313 case X86::EBP: 4314 if (SubRegNo == X86::BPL) return X86::sub_8bit; 4315 if (SubRegNo == X86::BP) return X86::sub_16bit; 4316 return 0; 4317 case X86::EBX: 4318 if (SubRegNo == X86::BL) return X86::sub_8bit; 4319 if (SubRegNo == X86::BH) return X86::sub_8bit_hi; 4320 if (SubRegNo == X86::BX) return X86::sub_16bit; 4321 return 0; 4322 case X86::ECX: 4323 if (SubRegNo == X86::CL) return X86::sub_8bit; 4324 if (SubRegNo == X86::CH) return X86::sub_8bit_hi; 4325 if (SubRegNo == X86::CX) return X86::sub_16bit; 4326 return 0; 4327 case X86::EDI: 4328 if (SubRegNo == X86::DIL) return X86::sub_8bit; 4329 if (SubRegNo == X86::DI) return X86::sub_16bit; 4330 return 0; 4331 case X86::EDX: 4332 if (SubRegNo == X86::DL) return X86::sub_8bit; 4333 if (SubRegNo == X86::DH) return X86::sub_8bit_hi; 4334 if (SubRegNo == X86::DX) return X86::sub_16bit; 4335 return 0; 4336 case X86::EIP: 4337 if (SubRegNo == X86::IP) return X86::sub_16bit; 4338 return 0; 4339 case X86::ESI: 4340 if (SubRegNo == X86::SIL) return X86::sub_8bit; 4341 if (SubRegNo == X86::SI) return X86::sub_16bit; 4342 return 0; 4343 case X86::ESP: 4344 if (SubRegNo == X86::SPL) return X86::sub_8bit; 4345 if (SubRegNo == X86::SP) return X86::sub_16bit; 4346 return 0; 4347 case X86::R8: 4348 if (SubRegNo == X86::R8B) return X86::sub_8bit; 4349 if (SubRegNo == X86::R8W) return X86::sub_16bit; 4350 if (SubRegNo == X86::R8D) return X86::sub_32bit; 4351 return 0; 4352 case X86::R8D: 4353 if (SubRegNo == X86::R8B) return X86::sub_8bit; 4354 if (SubRegNo == X86::R8W) return X86::sub_16bit; 4355 return 0; 4356 case X86::R8W: 4357 if (SubRegNo == X86::R8B) return X86::sub_8bit; 4358 return 0; 4359 case X86::R9: 4360 if (SubRegNo == X86::R9B) return X86::sub_8bit; 4361 if (SubRegNo == X86::R9W) return X86::sub_16bit; 4362 if (SubRegNo == X86::R9D) return X86::sub_32bit; 4363 return 0; 4364 case X86::R9D: 4365 if (SubRegNo == X86::R9B) return X86::sub_8bit; 4366 if (SubRegNo == X86::R9W) return X86::sub_16bit; 4367 return 0; 4368 case X86::R9W: 4369 if (SubRegNo == X86::R9B) return X86::sub_8bit; 4370 return 0; 4371 case X86::R10: 4372 if (SubRegNo == X86::R10B) return X86::sub_8bit; 4373 if (SubRegNo == X86::R10W) return X86::sub_16bit; 4374 if (SubRegNo == X86::R10D) return X86::sub_32bit; 4375 return 0; 4376 case X86::R10D: 4377 if (SubRegNo == X86::R10B) return X86::sub_8bit; 4378 if (SubRegNo == X86::R10W) return X86::sub_16bit; 4379 return 0; 4380 case X86::R10W: 4381 if (SubRegNo == X86::R10B) return X86::sub_8bit; 4382 return 0; 4383 case X86::R11: 4384 if (SubRegNo == X86::R11B) return X86::sub_8bit; 4385 if (SubRegNo == X86::R11W) return X86::sub_16bit; 4386 if (SubRegNo == X86::R11D) return X86::sub_32bit; 4387 return 0; 4388 case X86::R11D: 4389 if (SubRegNo == X86::R11B) return X86::sub_8bit; 4390 if (SubRegNo == X86::R11W) return X86::sub_16bit; 4391 return 0; 4392 case X86::R11W: 4393 if (SubRegNo == X86::R11B) return X86::sub_8bit; 4394 return 0; 4395 case X86::R12: 4396 if (SubRegNo == X86::R12B) return X86::sub_8bit; 4397 if (SubRegNo == X86::R12W) return X86::sub_16bit; 4398 if (SubRegNo == X86::R12D) return X86::sub_32bit; 4399 return 0; 4400 case X86::R12D: 4401 if (SubRegNo == X86::R12B) return X86::sub_8bit; 4402 if (SubRegNo == X86::R12W) return X86::sub_16bit; 4403 return 0; 4404 case X86::R12W: 4405 if (SubRegNo == X86::R12B) return X86::sub_8bit; 4406 return 0; 4407 case X86::R13: 4408 if (SubRegNo == X86::R13B) return X86::sub_8bit; 4409 if (SubRegNo == X86::R13W) return X86::sub_16bit; 4410 if (SubRegNo == X86::R13D) return X86::sub_32bit; 4411 return 0; 4412 case X86::R13D: 4413 if (SubRegNo == X86::R13B) return X86::sub_8bit; 4414 if (SubRegNo == X86::R13W) return X86::sub_16bit; 4415 return 0; 4416 case X86::R13W: 4417 if (SubRegNo == X86::R13B) return X86::sub_8bit; 4418 return 0; 4419 case X86::R14: 4420 if (SubRegNo == X86::R14B) return X86::sub_8bit; 4421 if (SubRegNo == X86::R14W) return X86::sub_16bit; 4422 if (SubRegNo == X86::R14D) return X86::sub_32bit; 4423 return 0; 4424 case X86::R14D: 4425 if (SubRegNo == X86::R14B) return X86::sub_8bit; 4426 if (SubRegNo == X86::R14W) return X86::sub_16bit; 4427 return 0; 4428 case X86::R14W: 4429 if (SubRegNo == X86::R14B) return X86::sub_8bit; 4430 return 0; 4431 case X86::R15: 4432 if (SubRegNo == X86::R15B) return X86::sub_8bit; 4433 if (SubRegNo == X86::R15W) return X86::sub_16bit; 4434 if (SubRegNo == X86::R15D) return X86::sub_32bit; 4435 return 0; 4436 case X86::R15D: 4437 if (SubRegNo == X86::R15B) return X86::sub_8bit; 4438 if (SubRegNo == X86::R15W) return X86::sub_16bit; 4439 return 0; 4440 case X86::R15W: 4441 if (SubRegNo == X86::R15B) return X86::sub_8bit; 4442 return 0; 4443 case X86::RAX: 4444 if (SubRegNo == X86::AL) return X86::sub_8bit; 4445 if (SubRegNo == X86::AH) return X86::sub_8bit_hi; 4446 if (SubRegNo == X86::AX) return X86::sub_16bit; 4447 if (SubRegNo == X86::EAX) return X86::sub_32bit; 4448 return 0; 4449 case X86::RBP: 4450 if (SubRegNo == X86::BPL) return X86::sub_8bit; 4451 if (SubRegNo == X86::BP) return X86::sub_16bit; 4452 if (SubRegNo == X86::EBP) return X86::sub_32bit; 4453 return 0; 4454 case X86::RBX: 4455 if (SubRegNo == X86::BL) return X86::sub_8bit; 4456 if (SubRegNo == X86::BH) return X86::sub_8bit_hi; 4457 if (SubRegNo == X86::BX) return X86::sub_16bit; 4458 if (SubRegNo == X86::EBX) return X86::sub_32bit; 4459 return 0; 4460 case X86::RCX: 4461 if (SubRegNo == X86::CL) return X86::sub_8bit; 4462 if (SubRegNo == X86::CH) return X86::sub_8bit_hi; 4463 if (SubRegNo == X86::CX) return X86::sub_16bit; 4464 if (SubRegNo == X86::ECX) return X86::sub_32bit; 4465 return 0; 4466 case X86::RDI: 4467 if (SubRegNo == X86::DIL) return X86::sub_8bit; 4468 if (SubRegNo == X86::DI) return X86::sub_16bit; 4469 if (SubRegNo == X86::EDI) return X86::sub_32bit; 4470 return 0; 4471 case X86::RDX: 4472 if (SubRegNo == X86::DL) return X86::sub_8bit; 4473 if (SubRegNo == X86::DH) return X86::sub_8bit_hi; 4474 if (SubRegNo == X86::DX) return X86::sub_16bit; 4475 if (SubRegNo == X86::EDX) return X86::sub_32bit; 4476 return 0; 4477 case X86::RIP: 4478 if (SubRegNo == X86::IP) return X86::sub_16bit; 4479 if (SubRegNo == X86::EIP) return X86::sub_32bit; 4480 return 0; 4481 case X86::RSI: 4482 if (SubRegNo == X86::SIL) return X86::sub_8bit; 4483 if (SubRegNo == X86::SI) return X86::sub_16bit; 4484 if (SubRegNo == X86::ESI) return X86::sub_32bit; 4485 return 0; 4486 case X86::RSP: 4487 if (SubRegNo == X86::SPL) return X86::sub_8bit; 4488 if (SubRegNo == X86::SP) return X86::sub_16bit; 4489 if (SubRegNo == X86::ESP) return X86::sub_32bit; 4490 return 0; 4491 case X86::SI: 4492 if (SubRegNo == X86::SIL) return X86::sub_8bit; 4493 return 0; 4494 case X86::SP: 4495 if (SubRegNo == X86::SPL) return X86::sub_8bit; 4496 return 0; 4497 case X86::XMM0: 4498 if (SubRegNo == X86::XMM0) return X86::sub_sd; 4499 if (SubRegNo == X86::XMM0) return X86::sub_ss; 4500 return 0; 4501 case X86::XMM1: 4502 if (SubRegNo == X86::XMM1) return X86::sub_sd; 4503 if (SubRegNo == X86::XMM1) return X86::sub_ss; 4504 return 0; 4505 case X86::XMM2: 4506 if (SubRegNo == X86::XMM2) return X86::sub_sd; 4507 if (SubRegNo == X86::XMM2) return X86::sub_ss; 4508 return 0; 4509 case X86::XMM3: 4510 if (SubRegNo == X86::XMM3) return X86::sub_sd; 4511 if (SubRegNo == X86::XMM3) return X86::sub_ss; 4512 return 0; 4513 case X86::XMM4: 4514 if (SubRegNo == X86::XMM4) return X86::sub_sd; 4515 if (SubRegNo == X86::XMM4) return X86::sub_ss; 4516 return 0; 4517 case X86::XMM5: 4518 if (SubRegNo == X86::XMM5) return X86::sub_sd; 4519 if (SubRegNo == X86::XMM5) return X86::sub_ss; 4520 return 0; 4521 case X86::XMM6: 4522 if (SubRegNo == X86::XMM6) return X86::sub_sd; 4523 if (SubRegNo == X86::XMM6) return X86::sub_ss; 4524 return 0; 4525 case X86::XMM7: 4526 if (SubRegNo == X86::XMM7) return X86::sub_sd; 4527 if (SubRegNo == X86::XMM7) return X86::sub_ss; 4528 return 0; 4529 case X86::XMM8: 4530 if (SubRegNo == X86::XMM8) return X86::sub_sd; 4531 if (SubRegNo == X86::XMM8) return X86::sub_ss; 4532 return 0; 4533 case X86::XMM9: 4534 if (SubRegNo == X86::XMM9) return X86::sub_sd; 4535 if (SubRegNo == X86::XMM9) return X86::sub_ss; 4536 return 0; 4537 case X86::XMM10: 4538 if (SubRegNo == X86::XMM10) return X86::sub_sd; 4539 if (SubRegNo == X86::XMM10) return X86::sub_ss; 4540 return 0; 4541 case X86::XMM11: 4542 if (SubRegNo == X86::XMM11) return X86::sub_sd; 4543 if (SubRegNo == X86::XMM11) return X86::sub_ss; 4544 return 0; 4545 case X86::XMM12: 4546 if (SubRegNo == X86::XMM12) return X86::sub_sd; 4547 if (SubRegNo == X86::XMM12) return X86::sub_ss; 4548 return 0; 4549 case X86::XMM13: 4550 if (SubRegNo == X86::XMM13) return X86::sub_sd; 4551 if (SubRegNo == X86::XMM13) return X86::sub_ss; 4552 return 0; 4553 case X86::XMM14: 4554 if (SubRegNo == X86::XMM14) return X86::sub_sd; 4555 if (SubRegNo == X86::XMM14) return X86::sub_ss; 4556 return 0; 4557 case X86::XMM15: 4558 if (SubRegNo == X86::XMM15) return X86::sub_sd; 4559 if (SubRegNo == X86::XMM15) return X86::sub_ss; 4560 return 0; 4561 case X86::YMM0: 4562 if (SubRegNo == X86::XMM0) return X86::sub_sd; 4563 if (SubRegNo == X86::XMM0) return X86::sub_ss; 4564 if (SubRegNo == X86::XMM0) return X86::sub_xmm; 4565 return 0; 4566 case X86::YMM1: 4567 if (SubRegNo == X86::XMM1) return X86::sub_sd; 4568 if (SubRegNo == X86::XMM1) return X86::sub_ss; 4569 if (SubRegNo == X86::XMM1) return X86::sub_xmm; 4570 return 0; 4571 case X86::YMM2: 4572 if (SubRegNo == X86::XMM2) return X86::sub_sd; 4573 if (SubRegNo == X86::XMM2) return X86::sub_ss; 4574 if (SubRegNo == X86::XMM2) return X86::sub_xmm; 4575 return 0; 4576 case X86::YMM3: 4577 if (SubRegNo == X86::XMM3) return X86::sub_sd; 4578 if (SubRegNo == X86::XMM3) return X86::sub_ss; 4579 if (SubRegNo == X86::XMM3) return X86::sub_xmm; 4580 return 0; 4581 case X86::YMM4: 4582 if (SubRegNo == X86::XMM4) return X86::sub_sd; 4583 if (SubRegNo == X86::XMM4) return X86::sub_ss; 4584 if (SubRegNo == X86::XMM4) return X86::sub_xmm; 4585 return 0; 4586 case X86::YMM5: 4587 if (SubRegNo == X86::XMM5) return X86::sub_sd; 4588 if (SubRegNo == X86::XMM5) return X86::sub_ss; 4589 if (SubRegNo == X86::XMM5) return X86::sub_xmm; 4590 return 0; 4591 case X86::YMM6: 4592 if (SubRegNo == X86::XMM6) return X86::sub_sd; 4593 if (SubRegNo == X86::XMM6) return X86::sub_ss; 4594 if (SubRegNo == X86::XMM6) return X86::sub_xmm; 4595 return 0; 4596 case X86::YMM7: 4597 if (SubRegNo == X86::XMM7) return X86::sub_sd; 4598 if (SubRegNo == X86::XMM7) return X86::sub_ss; 4599 if (SubRegNo == X86::XMM7) return X86::sub_xmm; 4600 return 0; 4601 case X86::YMM8: 4602 if (SubRegNo == X86::XMM8) return X86::sub_sd; 4603 if (SubRegNo == X86::XMM8) return X86::sub_ss; 4604 if (SubRegNo == X86::XMM8) return X86::sub_xmm; 4605 return 0; 4606 case X86::YMM9: 4607 if (SubRegNo == X86::XMM9) return X86::sub_sd; 4608 if (SubRegNo == X86::XMM9) return X86::sub_ss; 4609 if (SubRegNo == X86::XMM9) return X86::sub_xmm; 4610 return 0; 4611 case X86::YMM10: 4612 if (SubRegNo == X86::XMM10) return X86::sub_sd; 4613 if (SubRegNo == X86::XMM10) return X86::sub_ss; 4614 if (SubRegNo == X86::XMM10) return X86::sub_xmm; 4615 return 0; 4616 case X86::YMM11: 4617 if (SubRegNo == X86::XMM11) return X86::sub_sd; 4618 if (SubRegNo == X86::XMM11) return X86::sub_ss; 4619 if (SubRegNo == X86::XMM11) return X86::sub_xmm; 4620 return 0; 4621 case X86::YMM12: 4622 if (SubRegNo == X86::XMM12) return X86::sub_sd; 4623 if (SubRegNo == X86::XMM12) return X86::sub_ss; 4624 if (SubRegNo == X86::XMM12) return X86::sub_xmm; 4625 return 0; 4626 case X86::YMM13: 4627 if (SubRegNo == X86::XMM13) return X86::sub_sd; 4628 if (SubRegNo == X86::XMM13) return X86::sub_ss; 4629 if (SubRegNo == X86::XMM13) return X86::sub_xmm; 4630 return 0; 4631 case X86::YMM14: 4632 if (SubRegNo == X86::XMM14) return X86::sub_sd; 4633 if (SubRegNo == X86::XMM14) return X86::sub_ss; 4634 if (SubRegNo == X86::XMM14) return X86::sub_xmm; 4635 return 0; 4636 case X86::YMM15: 4637 if (SubRegNo == X86::XMM15) return X86::sub_sd; 4638 if (SubRegNo == X86::XMM15) return X86::sub_ss; 4639 if (SubRegNo == X86::XMM15) return X86::sub_xmm; 4640 return 0; 4641 }; 4642 return 0; 4643} 4644 4645unsigned X86GenRegisterInfo::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const { 4646 switch (IdxA) { 4647 default: 4648 return IdxB; 4649 } 4650} 4651 4652const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 4653 static const uint8_t Table[40][7] = { 4654 { // GR8 4655 0, // sub_8bit 4656 0, // sub_8bit_hi 4657 0, // sub_16bit 4658 0, // sub_32bit 4659 0, // sub_sd 4660 0, // sub_ss 4661 0, // sub_xmm 4662 }, 4663 { // GR64 4664 6, // sub_8bit -> GR64_with_sub_8bit 4665 35, // sub_8bit_hi -> GR64_ABCD 4666 2, // sub_16bit -> GR64 4667 2, // sub_32bit -> GR64 4668 0, // sub_sd 4669 0, // sub_ss 4670 0, // sub_xmm 4671 }, 4672 { // GR16 4673 3, // sub_8bit -> GR16 4674 33, // sub_8bit_hi -> GR16_ABCD 4675 0, // sub_16bit 4676 0, // sub_32bit 4677 0, // sub_sd 4678 0, // sub_ss 4679 0, // sub_xmm 4680 }, 4681 { // GR32 4682 4, // sub_8bit -> GR32 4683 34, // sub_8bit_hi -> GR32_ABCD 4684 4, // sub_16bit -> GR32 4685 0, // sub_32bit 4686 0, // sub_sd 4687 0, // sub_ss 4688 0, // sub_xmm 4689 }, 4690 { // FR32 4691 0, // sub_8bit 4692 0, // sub_8bit_hi 4693 0, // sub_16bit 4694 0, // sub_32bit 4695 5, // sub_sd -> FR32 4696 5, // sub_ss -> FR32 4697 0, // sub_xmm 4698 }, 4699 { // GR64_with_sub_8bit 4700 6, // sub_8bit -> GR64_with_sub_8bit 4701 35, // sub_8bit_hi -> GR64_ABCD 4702 6, // sub_16bit -> GR64_with_sub_8bit 4703 6, // sub_32bit -> GR64_with_sub_8bit 4704 0, // sub_sd 4705 0, // sub_ss 4706 0, // sub_xmm 4707 }, 4708 { // FR64 4709 0, // sub_8bit 4710 0, // sub_8bit_hi 4711 0, // sub_16bit 4712 0, // sub_32bit 4713 7, // sub_sd -> FR64 4714 7, // sub_ss -> FR64 4715 0, // sub_xmm 4716 }, 4717 { // CONTROL_REG 4718 0, // sub_8bit 4719 0, // sub_8bit_hi 4720 0, // sub_16bit 4721 0, // sub_32bit 4722 0, // sub_sd 4723 0, // sub_ss 4724 0, // sub_xmm 4725 }, 4726 { // VR128 4727 0, // sub_8bit 4728 0, // sub_8bit_hi 4729 0, // sub_16bit 4730 0, // sub_32bit 4731 9, // sub_sd -> VR128 4732 9, // sub_ss -> VR128 4733 0, // sub_xmm 4734 }, 4735 { // VR256 4736 0, // sub_8bit 4737 0, // sub_8bit_hi 4738 0, // sub_16bit 4739 0, // sub_32bit 4740 10, // sub_sd -> VR256 4741 10, // sub_ss -> VR256 4742 10, // sub_xmm -> VR256 4743 }, 4744 { // GR32_NOSP 4745 11, // sub_8bit -> GR32_NOSP 4746 34, // sub_8bit_hi -> GR32_ABCD 4747 11, // sub_16bit -> GR32_NOSP 4748 0, // sub_32bit 4749 0, // sub_sd 4750 0, // sub_ss 4751 0, // sub_xmm 4752 }, 4753 { // GR32_NOAX 4754 12, // sub_8bit -> GR32_NOAX 4755 37, // sub_8bit_hi -> GR32_NOAX_with_sub_8bit_hi 4756 12, // sub_16bit -> GR32_NOAX 4757 0, // sub_32bit 4758 0, // sub_sd 4759 0, // sub_ss 4760 0, // sub_xmm 4761 }, 4762 { // GR64_NOSP 4763 13, // sub_8bit -> GR64_NOSP 4764 35, // sub_8bit_hi -> GR64_ABCD 4765 13, // sub_16bit -> GR64_NOSP 4766 13, // sub_32bit -> GR64_NOSP 4767 0, // sub_sd 4768 0, // sub_ss 4769 0, // sub_xmm 4770 }, 4771 { // GR64_TC 4772 21, // sub_8bit -> GR64_TC_with_sub_8bit 4773 38, // sub_8bit_hi -> GR64_TC_with_sub_8bit_hi 4774 14, // sub_16bit -> GR64_TC 4775 14, // sub_32bit -> GR64_TC 4776 0, // sub_sd 4777 0, // sub_ss 4778 0, // sub_xmm 4779 }, 4780 { // GR64_NOREX 4781 22, // sub_8bit -> GR64_NOREX_with_sub_8bit 4782 35, // sub_8bit_hi -> GR64_ABCD 4783 15, // sub_16bit -> GR64_NOREX 4784 15, // sub_32bit -> GR64_NOREX 4785 0, // sub_sd 4786 0, // sub_ss 4787 0, // sub_xmm 4788 }, 4789 { // GR8_NOREX 4790 0, // sub_8bit 4791 0, // sub_8bit_hi 4792 0, // sub_16bit 4793 0, // sub_32bit 4794 0, // sub_sd 4795 0, // sub_ss 4796 0, // sub_xmm 4797 }, 4798 { // GR16_NOREX 4799 17, // sub_8bit -> GR16_NOREX 4800 33, // sub_8bit_hi -> GR16_ABCD 4801 0, // sub_16bit 4802 0, // sub_32bit 4803 0, // sub_sd 4804 0, // sub_ss 4805 0, // sub_xmm 4806 }, 4807 { // GR32_NOREX 4808 18, // sub_8bit -> GR32_NOREX 4809 34, // sub_8bit_hi -> GR32_ABCD 4810 18, // sub_16bit -> GR32_NOREX 4811 0, // sub_32bit 4812 0, // sub_sd 4813 0, // sub_ss 4814 0, // sub_xmm 4815 }, 4816 { // DEBUG_REG 4817 0, // sub_8bit 4818 0, // sub_8bit_hi 4819 0, // sub_16bit 4820 0, // sub_32bit 4821 0, // sub_sd 4822 0, // sub_ss 4823 0, // sub_xmm 4824 }, 4825 { // VR64 4826 0, // sub_8bit 4827 0, // sub_8bit_hi 4828 0, // sub_16bit 4829 0, // sub_32bit 4830 0, // sub_sd 4831 0, // sub_ss 4832 0, // sub_xmm 4833 }, 4834 { // GR64_TC_with_sub_8bit 4835 21, // sub_8bit -> GR64_TC_with_sub_8bit 4836 38, // sub_8bit_hi -> GR64_TC_with_sub_8bit_hi 4837 21, // sub_16bit -> GR64_TC_with_sub_8bit 4838 21, // sub_32bit -> GR64_TC_with_sub_8bit 4839 0, // sub_sd 4840 0, // sub_ss 4841 0, // sub_xmm 4842 }, 4843 { // GR64_NOREX_with_sub_8bit 4844 22, // sub_8bit -> GR64_NOREX_with_sub_8bit 4845 35, // sub_8bit_hi -> GR64_ABCD 4846 22, // sub_16bit -> GR64_NOREX_with_sub_8bit 4847 22, // sub_32bit -> GR64_NOREX_with_sub_8bit 4848 0, // sub_sd 4849 0, // sub_ss 4850 0, // sub_xmm 4851 }, 4852 { // RST 4853 0, // sub_8bit 4854 0, // sub_8bit_hi 4855 0, // sub_16bit 4856 0, // sub_32bit 4857 0, // sub_sd 4858 0, // sub_ss 4859 0, // sub_xmm 4860 }, 4861 { // RFP32 4862 0, // sub_8bit 4863 0, // sub_8bit_hi 4864 0, // sub_16bit 4865 0, // sub_32bit 4866 0, // sub_sd 4867 0, // sub_ss 4868 0, // sub_xmm 4869 }, 4870 { // GR32_NOREX_NOSP 4871 25, // sub_8bit -> GR32_NOREX_NOSP 4872 34, // sub_8bit_hi -> GR32_ABCD 4873 25, // sub_16bit -> GR32_NOREX_NOSP 4874 0, // sub_32bit 4875 0, // sub_sd 4876 0, // sub_ss 4877 0, // sub_xmm 4878 }, 4879 { // RFP64 4880 0, // sub_8bit 4881 0, // sub_8bit_hi 4882 0, // sub_16bit 4883 0, // sub_32bit 4884 0, // sub_sd 4885 0, // sub_ss 4886 0, // sub_xmm 4887 }, 4888 { // GR64_NOREX_NOSP 4889 27, // sub_8bit -> GR64_NOREX_NOSP 4890 35, // sub_8bit_hi -> GR64_ABCD 4891 27, // sub_16bit -> GR64_NOREX_NOSP 4892 27, // sub_32bit -> GR64_NOREX_NOSP 4893 0, // sub_sd 4894 0, // sub_ss 4895 0, // sub_xmm 4896 }, 4897 { // RFP80 4898 0, // sub_8bit 4899 0, // sub_8bit_hi 4900 0, // sub_16bit 4901 0, // sub_32bit 4902 0, // sub_sd 4903 0, // sub_ss 4904 0, // sub_xmm 4905 }, 4906 { // SEGMENT_REG 4907 0, // sub_8bit 4908 0, // sub_8bit_hi 4909 0, // sub_16bit 4910 0, // sub_32bit 4911 0, // sub_sd 4912 0, // sub_ss 4913 0, // sub_xmm 4914 }, 4915 { // GR64_TCW64 4916 30, // sub_8bit -> GR64_TCW64 4917 38, // sub_8bit_hi -> GR64_TC_with_sub_8bit_hi 4918 30, // sub_16bit -> GR64_TCW64 4919 30, // sub_32bit -> GR64_TCW64 4920 0, // sub_sd 4921 0, // sub_ss 4922 0, // sub_xmm 4923 }, 4924 { // GR8_ABCD_L 4925 0, // sub_8bit 4926 0, // sub_8bit_hi 4927 0, // sub_16bit 4928 0, // sub_32bit 4929 0, // sub_sd 4930 0, // sub_ss 4931 0, // sub_xmm 4932 }, 4933 { // GR8_ABCD_H 4934 0, // sub_8bit 4935 0, // sub_8bit_hi 4936 0, // sub_16bit 4937 0, // sub_32bit 4938 0, // sub_sd 4939 0, // sub_ss 4940 0, // sub_xmm 4941 }, 4942 { // GR16_ABCD 4943 33, // sub_8bit -> GR16_ABCD 4944 33, // sub_8bit_hi -> GR16_ABCD 4945 0, // sub_16bit 4946 0, // sub_32bit 4947 0, // sub_sd 4948 0, // sub_ss 4949 0, // sub_xmm 4950 }, 4951 { // GR32_ABCD 4952 34, // sub_8bit -> GR32_ABCD 4953 34, // sub_8bit_hi -> GR32_ABCD 4954 34, // sub_16bit -> GR32_ABCD 4955 0, // sub_32bit 4956 0, // sub_sd 4957 0, // sub_ss 4958 0, // sub_xmm 4959 }, 4960 { // GR64_ABCD 4961 35, // sub_8bit -> GR64_ABCD 4962 35, // sub_8bit_hi -> GR64_ABCD 4963 35, // sub_16bit -> GR64_ABCD 4964 35, // sub_32bit -> GR64_ABCD 4965 0, // sub_sd 4966 0, // sub_ss 4967 0, // sub_xmm 4968 }, 4969 { // GR32_TC 4970 36, // sub_8bit -> GR32_TC 4971 36, // sub_8bit_hi -> GR32_TC 4972 36, // sub_16bit -> GR32_TC 4973 0, // sub_32bit 4974 0, // sub_sd 4975 0, // sub_ss 4976 0, // sub_xmm 4977 }, 4978 { // GR32_NOAX_with_sub_8bit_hi 4979 37, // sub_8bit -> GR32_NOAX_with_sub_8bit_hi 4980 37, // sub_8bit_hi -> GR32_NOAX_with_sub_8bit_hi 4981 37, // sub_16bit -> GR32_NOAX_with_sub_8bit_hi 4982 0, // sub_32bit 4983 0, // sub_sd 4984 0, // sub_ss 4985 0, // sub_xmm 4986 }, 4987 { // GR64_TC_with_sub_8bit_hi 4988 38, // sub_8bit -> GR64_TC_with_sub_8bit_hi 4989 38, // sub_8bit_hi -> GR64_TC_with_sub_8bit_hi 4990 38, // sub_16bit -> GR64_TC_with_sub_8bit_hi 4991 38, // sub_32bit -> GR64_TC_with_sub_8bit_hi 4992 0, // sub_sd 4993 0, // sub_ss 4994 0, // sub_xmm 4995 }, 4996 { // GR32_AD 4997 39, // sub_8bit -> GR32_AD 4998 39, // sub_8bit_hi -> GR32_AD 4999 39, // sub_16bit -> GR32_AD 5000 0, // sub_32bit 5001 0, // sub_sd 5002 0, // sub_ss 5003 0, // sub_xmm 5004 }, 5005 { // CCR 5006 0, // sub_8bit 5007 0, // sub_8bit_hi 5008 0, // sub_16bit 5009 0, // sub_32bit 5010 0, // sub_sd 5011 0, // sub_ss 5012 0, // sub_xmm 5013 }, 5014 }; 5015 assert(RC && "Missing regclass"); 5016 if (!Idx) return RC; 5017 --Idx; 5018 assert(Idx < 7 && "Bad subreg"); 5019 unsigned TV = Table[RC->getID()][Idx]; 5020 return TV ? getRegClass(TV - 1) : 0; 5021} 5022 5023extern MCRegisterDesc X86RegDesc[]; 5024X86GenRegisterInfo::X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour) 5025 : TargetRegisterInfo(X86RegInfoDesc, RegisterClasses, RegisterClasses+40, 5026 X86SubRegIndexTable) { 5027 InitMCRegisterInfo(X86RegDesc, 160, RA, X86MCRegisterClasses, 40); 5028 5029 switch (DwarfFlavour) { 5030 default: 5031 assert(0 && "Unknown DWARF flavour"); 5032 break; 5033 case 0: 5034 mapDwarfRegToLLVMReg(41, X86::MM0, false ); 5035 mapDwarfRegToLLVMReg(42, X86::MM1, false ); 5036 mapDwarfRegToLLVMReg(43, X86::MM2, false ); 5037 mapDwarfRegToLLVMReg(44, X86::MM3, false ); 5038 mapDwarfRegToLLVMReg(45, X86::MM4, false ); 5039 mapDwarfRegToLLVMReg(46, X86::MM5, false ); 5040 mapDwarfRegToLLVMReg(47, X86::MM6, false ); 5041 mapDwarfRegToLLVMReg(48, X86::MM7, false ); 5042 mapDwarfRegToLLVMReg(8, X86::R8, false ); 5043 mapDwarfRegToLLVMReg(9, X86::R9, false ); 5044 mapDwarfRegToLLVMReg(10, X86::R10, false ); 5045 mapDwarfRegToLLVMReg(11, X86::R11, false ); 5046 mapDwarfRegToLLVMReg(12, X86::R12, false ); 5047 mapDwarfRegToLLVMReg(13, X86::R13, false ); 5048 mapDwarfRegToLLVMReg(14, X86::R14, false ); 5049 mapDwarfRegToLLVMReg(15, X86::R15, false ); 5050 mapDwarfRegToLLVMReg(0, X86::RAX, false ); 5051 mapDwarfRegToLLVMReg(6, X86::RBP, false ); 5052 mapDwarfRegToLLVMReg(3, X86::RBX, false ); 5053 mapDwarfRegToLLVMReg(2, X86::RCX, false ); 5054 mapDwarfRegToLLVMReg(5, X86::RDI, false ); 5055 mapDwarfRegToLLVMReg(1, X86::RDX, false ); 5056 mapDwarfRegToLLVMReg(16, X86::RIP, false ); 5057 mapDwarfRegToLLVMReg(4, X86::RSI, false ); 5058 mapDwarfRegToLLVMReg(7, X86::RSP, false ); 5059 mapDwarfRegToLLVMReg(33, X86::ST0, false ); 5060 mapDwarfRegToLLVMReg(34, X86::ST1, false ); 5061 mapDwarfRegToLLVMReg(35, X86::ST2, false ); 5062 mapDwarfRegToLLVMReg(36, X86::ST3, false ); 5063 mapDwarfRegToLLVMReg(37, X86::ST4, false ); 5064 mapDwarfRegToLLVMReg(38, X86::ST5, false ); 5065 mapDwarfRegToLLVMReg(39, X86::ST6, false ); 5066 mapDwarfRegToLLVMReg(40, X86::ST7, false ); 5067 mapDwarfRegToLLVMReg(17, X86::XMM0, false ); 5068 mapDwarfRegToLLVMReg(18, X86::XMM1, false ); 5069 mapDwarfRegToLLVMReg(19, X86::XMM2, false ); 5070 mapDwarfRegToLLVMReg(20, X86::XMM3, false ); 5071 mapDwarfRegToLLVMReg(21, X86::XMM4, false ); 5072 mapDwarfRegToLLVMReg(22, X86::XMM5, false ); 5073 mapDwarfRegToLLVMReg(23, X86::XMM6, false ); 5074 mapDwarfRegToLLVMReg(24, X86::XMM7, false ); 5075 mapDwarfRegToLLVMReg(25, X86::XMM8, false ); 5076 mapDwarfRegToLLVMReg(26, X86::XMM9, false ); 5077 mapDwarfRegToLLVMReg(27, X86::XMM10, false ); 5078 mapDwarfRegToLLVMReg(28, X86::XMM11, false ); 5079 mapDwarfRegToLLVMReg(29, X86::XMM12, false ); 5080 mapDwarfRegToLLVMReg(30, X86::XMM13, false ); 5081 mapDwarfRegToLLVMReg(31, X86::XMM14, false ); 5082 mapDwarfRegToLLVMReg(32, X86::XMM15, false ); 5083 break; 5084 case 1: 5085 mapDwarfRegToLLVMReg(0, X86::EAX, false ); 5086 mapDwarfRegToLLVMReg(4, X86::EBP, false ); 5087 mapDwarfRegToLLVMReg(3, X86::EBX, false ); 5088 mapDwarfRegToLLVMReg(1, X86::ECX, false ); 5089 mapDwarfRegToLLVMReg(7, X86::EDI, false ); 5090 mapDwarfRegToLLVMReg(2, X86::EDX, false ); 5091 mapDwarfRegToLLVMReg(8, X86::EIP, false ); 5092 mapDwarfRegToLLVMReg(6, X86::ESI, false ); 5093 mapDwarfRegToLLVMReg(5, X86::ESP, false ); 5094 mapDwarfRegToLLVMReg(29, X86::MM0, false ); 5095 mapDwarfRegToLLVMReg(30, X86::MM1, false ); 5096 mapDwarfRegToLLVMReg(31, X86::MM2, false ); 5097 mapDwarfRegToLLVMReg(32, X86::MM3, false ); 5098 mapDwarfRegToLLVMReg(33, X86::MM4, false ); 5099 mapDwarfRegToLLVMReg(34, X86::MM5, false ); 5100 mapDwarfRegToLLVMReg(35, X86::MM6, false ); 5101 mapDwarfRegToLLVMReg(36, X86::MM7, false ); 5102 mapDwarfRegToLLVMReg(12, X86::ST0, false ); 5103 mapDwarfRegToLLVMReg(13, X86::ST1, false ); 5104 mapDwarfRegToLLVMReg(14, X86::ST2, false ); 5105 mapDwarfRegToLLVMReg(15, X86::ST3, false ); 5106 mapDwarfRegToLLVMReg(16, X86::ST4, false ); 5107 mapDwarfRegToLLVMReg(17, X86::ST5, false ); 5108 mapDwarfRegToLLVMReg(18, X86::ST6, false ); 5109 mapDwarfRegToLLVMReg(19, X86::ST7, false ); 5110 mapDwarfRegToLLVMReg(21, X86::XMM0, false ); 5111 mapDwarfRegToLLVMReg(22, X86::XMM1, false ); 5112 mapDwarfRegToLLVMReg(23, X86::XMM2, false ); 5113 mapDwarfRegToLLVMReg(24, X86::XMM3, false ); 5114 mapDwarfRegToLLVMReg(25, X86::XMM4, false ); 5115 mapDwarfRegToLLVMReg(26, X86::XMM5, false ); 5116 mapDwarfRegToLLVMReg(27, X86::XMM6, false ); 5117 mapDwarfRegToLLVMReg(28, X86::XMM7, false ); 5118 break; 5119 case 2: 5120 mapDwarfRegToLLVMReg(0, X86::EAX, false ); 5121 mapDwarfRegToLLVMReg(5, X86::EBP, false ); 5122 mapDwarfRegToLLVMReg(3, X86::EBX, false ); 5123 mapDwarfRegToLLVMReg(1, X86::ECX, false ); 5124 mapDwarfRegToLLVMReg(7, X86::EDI, false ); 5125 mapDwarfRegToLLVMReg(2, X86::EDX, false ); 5126 mapDwarfRegToLLVMReg(8, X86::EIP, false ); 5127 mapDwarfRegToLLVMReg(6, X86::ESI, false ); 5128 mapDwarfRegToLLVMReg(4, X86::ESP, false ); 5129 mapDwarfRegToLLVMReg(29, X86::MM0, false ); 5130 mapDwarfRegToLLVMReg(30, X86::MM1, false ); 5131 mapDwarfRegToLLVMReg(31, X86::MM2, false ); 5132 mapDwarfRegToLLVMReg(32, X86::MM3, false ); 5133 mapDwarfRegToLLVMReg(33, X86::MM4, false ); 5134 mapDwarfRegToLLVMReg(34, X86::MM5, false ); 5135 mapDwarfRegToLLVMReg(35, X86::MM6, false ); 5136 mapDwarfRegToLLVMReg(36, X86::MM7, false ); 5137 mapDwarfRegToLLVMReg(11, X86::ST0, false ); 5138 mapDwarfRegToLLVMReg(12, X86::ST1, false ); 5139 mapDwarfRegToLLVMReg(13, X86::ST2, false ); 5140 mapDwarfRegToLLVMReg(14, X86::ST3, false ); 5141 mapDwarfRegToLLVMReg(15, X86::ST4, false ); 5142 mapDwarfRegToLLVMReg(16, X86::ST5, false ); 5143 mapDwarfRegToLLVMReg(17, X86::ST6, false ); 5144 mapDwarfRegToLLVMReg(18, X86::ST7, false ); 5145 mapDwarfRegToLLVMReg(21, X86::XMM0, false ); 5146 mapDwarfRegToLLVMReg(22, X86::XMM1, false ); 5147 mapDwarfRegToLLVMReg(23, X86::XMM2, false ); 5148 mapDwarfRegToLLVMReg(24, X86::XMM3, false ); 5149 mapDwarfRegToLLVMReg(25, X86::XMM4, false ); 5150 mapDwarfRegToLLVMReg(26, X86::XMM5, false ); 5151 mapDwarfRegToLLVMReg(27, X86::XMM6, false ); 5152 mapDwarfRegToLLVMReg(28, X86::XMM7, false ); 5153 break; 5154 } 5155 switch (EHFlavour) { 5156 default: 5157 assert(0 && "Unknown DWARF flavour"); 5158 break; 5159 case 0: 5160 mapDwarfRegToLLVMReg(41, X86::MM0, true ); 5161 mapDwarfRegToLLVMReg(42, X86::MM1, true ); 5162 mapDwarfRegToLLVMReg(43, X86::MM2, true ); 5163 mapDwarfRegToLLVMReg(44, X86::MM3, true ); 5164 mapDwarfRegToLLVMReg(45, X86::MM4, true ); 5165 mapDwarfRegToLLVMReg(46, X86::MM5, true ); 5166 mapDwarfRegToLLVMReg(47, X86::MM6, true ); 5167 mapDwarfRegToLLVMReg(48, X86::MM7, true ); 5168 mapDwarfRegToLLVMReg(8, X86::R8, true ); 5169 mapDwarfRegToLLVMReg(9, X86::R9, true ); 5170 mapDwarfRegToLLVMReg(10, X86::R10, true ); 5171 mapDwarfRegToLLVMReg(11, X86::R11, true ); 5172 mapDwarfRegToLLVMReg(12, X86::R12, true ); 5173 mapDwarfRegToLLVMReg(13, X86::R13, true ); 5174 mapDwarfRegToLLVMReg(14, X86::R14, true ); 5175 mapDwarfRegToLLVMReg(15, X86::R15, true ); 5176 mapDwarfRegToLLVMReg(0, X86::RAX, true ); 5177 mapDwarfRegToLLVMReg(6, X86::RBP, true ); 5178 mapDwarfRegToLLVMReg(3, X86::RBX, true ); 5179 mapDwarfRegToLLVMReg(2, X86::RCX, true ); 5180 mapDwarfRegToLLVMReg(5, X86::RDI, true ); 5181 mapDwarfRegToLLVMReg(1, X86::RDX, true ); 5182 mapDwarfRegToLLVMReg(16, X86::RIP, true ); 5183 mapDwarfRegToLLVMReg(4, X86::RSI, true ); 5184 mapDwarfRegToLLVMReg(7, X86::RSP, true ); 5185 mapDwarfRegToLLVMReg(33, X86::ST0, true ); 5186 mapDwarfRegToLLVMReg(34, X86::ST1, true ); 5187 mapDwarfRegToLLVMReg(35, X86::ST2, true ); 5188 mapDwarfRegToLLVMReg(36, X86::ST3, true ); 5189 mapDwarfRegToLLVMReg(37, X86::ST4, true ); 5190 mapDwarfRegToLLVMReg(38, X86::ST5, true ); 5191 mapDwarfRegToLLVMReg(39, X86::ST6, true ); 5192 mapDwarfRegToLLVMReg(40, X86::ST7, true ); 5193 mapDwarfRegToLLVMReg(17, X86::XMM0, true ); 5194 mapDwarfRegToLLVMReg(18, X86::XMM1, true ); 5195 mapDwarfRegToLLVMReg(19, X86::XMM2, true ); 5196 mapDwarfRegToLLVMReg(20, X86::XMM3, true ); 5197 mapDwarfRegToLLVMReg(21, X86::XMM4, true ); 5198 mapDwarfRegToLLVMReg(22, X86::XMM5, true ); 5199 mapDwarfRegToLLVMReg(23, X86::XMM6, true ); 5200 mapDwarfRegToLLVMReg(24, X86::XMM7, true ); 5201 mapDwarfRegToLLVMReg(25, X86::XMM8, true ); 5202 mapDwarfRegToLLVMReg(26, X86::XMM9, true ); 5203 mapDwarfRegToLLVMReg(27, X86::XMM10, true ); 5204 mapDwarfRegToLLVMReg(28, X86::XMM11, true ); 5205 mapDwarfRegToLLVMReg(29, X86::XMM12, true ); 5206 mapDwarfRegToLLVMReg(30, X86::XMM13, true ); 5207 mapDwarfRegToLLVMReg(31, X86::XMM14, true ); 5208 mapDwarfRegToLLVMReg(32, X86::XMM15, true ); 5209 break; 5210 case 1: 5211 mapDwarfRegToLLVMReg(0, X86::EAX, true ); 5212 mapDwarfRegToLLVMReg(4, X86::EBP, true ); 5213 mapDwarfRegToLLVMReg(3, X86::EBX, true ); 5214 mapDwarfRegToLLVMReg(1, X86::ECX, true ); 5215 mapDwarfRegToLLVMReg(7, X86::EDI, true ); 5216 mapDwarfRegToLLVMReg(2, X86::EDX, true ); 5217 mapDwarfRegToLLVMReg(8, X86::EIP, true ); 5218 mapDwarfRegToLLVMReg(6, X86::ESI, true ); 5219 mapDwarfRegToLLVMReg(5, X86::ESP, true ); 5220 mapDwarfRegToLLVMReg(29, X86::MM0, true ); 5221 mapDwarfRegToLLVMReg(30, X86::MM1, true ); 5222 mapDwarfRegToLLVMReg(31, X86::MM2, true ); 5223 mapDwarfRegToLLVMReg(32, X86::MM3, true ); 5224 mapDwarfRegToLLVMReg(33, X86::MM4, true ); 5225 mapDwarfRegToLLVMReg(34, X86::MM5, true ); 5226 mapDwarfRegToLLVMReg(35, X86::MM6, true ); 5227 mapDwarfRegToLLVMReg(36, X86::MM7, true ); 5228 mapDwarfRegToLLVMReg(12, X86::ST0, true ); 5229 mapDwarfRegToLLVMReg(13, X86::ST1, true ); 5230 mapDwarfRegToLLVMReg(14, X86::ST2, true ); 5231 mapDwarfRegToLLVMReg(15, X86::ST3, true ); 5232 mapDwarfRegToLLVMReg(16, X86::ST4, true ); 5233 mapDwarfRegToLLVMReg(17, X86::ST5, true ); 5234 mapDwarfRegToLLVMReg(18, X86::ST6, true ); 5235 mapDwarfRegToLLVMReg(19, X86::ST7, true ); 5236 mapDwarfRegToLLVMReg(21, X86::XMM0, true ); 5237 mapDwarfRegToLLVMReg(22, X86::XMM1, true ); 5238 mapDwarfRegToLLVMReg(23, X86::XMM2, true ); 5239 mapDwarfRegToLLVMReg(24, X86::XMM3, true ); 5240 mapDwarfRegToLLVMReg(25, X86::XMM4, true ); 5241 mapDwarfRegToLLVMReg(26, X86::XMM5, true ); 5242 mapDwarfRegToLLVMReg(27, X86::XMM6, true ); 5243 mapDwarfRegToLLVMReg(28, X86::XMM7, true ); 5244 break; 5245 case 2: 5246 mapDwarfRegToLLVMReg(0, X86::EAX, true ); 5247 mapDwarfRegToLLVMReg(5, X86::EBP, true ); 5248 mapDwarfRegToLLVMReg(3, X86::EBX, true ); 5249 mapDwarfRegToLLVMReg(1, X86::ECX, true ); 5250 mapDwarfRegToLLVMReg(7, X86::EDI, true ); 5251 mapDwarfRegToLLVMReg(2, X86::EDX, true ); 5252 mapDwarfRegToLLVMReg(8, X86::EIP, true ); 5253 mapDwarfRegToLLVMReg(6, X86::ESI, true ); 5254 mapDwarfRegToLLVMReg(4, X86::ESP, true ); 5255 mapDwarfRegToLLVMReg(29, X86::MM0, true ); 5256 mapDwarfRegToLLVMReg(30, X86::MM1, true ); 5257 mapDwarfRegToLLVMReg(31, X86::MM2, true ); 5258 mapDwarfRegToLLVMReg(32, X86::MM3, true ); 5259 mapDwarfRegToLLVMReg(33, X86::MM4, true ); 5260 mapDwarfRegToLLVMReg(34, X86::MM5, true ); 5261 mapDwarfRegToLLVMReg(35, X86::MM6, true ); 5262 mapDwarfRegToLLVMReg(36, X86::MM7, true ); 5263 mapDwarfRegToLLVMReg(11, X86::ST0, true ); 5264 mapDwarfRegToLLVMReg(12, X86::ST1, true ); 5265 mapDwarfRegToLLVMReg(13, X86::ST2, true ); 5266 mapDwarfRegToLLVMReg(14, X86::ST3, true ); 5267 mapDwarfRegToLLVMReg(15, X86::ST4, true ); 5268 mapDwarfRegToLLVMReg(16, X86::ST5, true ); 5269 mapDwarfRegToLLVMReg(17, X86::ST6, true ); 5270 mapDwarfRegToLLVMReg(18, X86::ST7, true ); 5271 mapDwarfRegToLLVMReg(21, X86::XMM0, true ); 5272 mapDwarfRegToLLVMReg(22, X86::XMM1, true ); 5273 mapDwarfRegToLLVMReg(23, X86::XMM2, true ); 5274 mapDwarfRegToLLVMReg(24, X86::XMM3, true ); 5275 mapDwarfRegToLLVMReg(25, X86::XMM4, true ); 5276 mapDwarfRegToLLVMReg(26, X86::XMM5, true ); 5277 mapDwarfRegToLLVMReg(27, X86::XMM6, true ); 5278 mapDwarfRegToLLVMReg(28, X86::XMM7, true ); 5279 break; 5280 } 5281 switch (DwarfFlavour) { 5282 default: 5283 assert(0 && "Unknown DWARF flavour"); 5284 break; 5285 case 0: 5286 mapLLVMRegToDwarfReg(X86::AH, -1, false ); 5287 mapLLVMRegToDwarfReg(X86::AL, -1, false ); 5288 mapLLVMRegToDwarfReg(X86::AX, -1, false ); 5289 mapLLVMRegToDwarfReg(X86::BH, -1, false ); 5290 mapLLVMRegToDwarfReg(X86::BL, -1, false ); 5291 mapLLVMRegToDwarfReg(X86::BP, -1, false ); 5292 mapLLVMRegToDwarfReg(X86::BPL, -1, false ); 5293 mapLLVMRegToDwarfReg(X86::BX, -1, false ); 5294 mapLLVMRegToDwarfReg(X86::CH, -1, false ); 5295 mapLLVMRegToDwarfReg(X86::CL, -1, false ); 5296 mapLLVMRegToDwarfReg(X86::CR0, -1, false ); 5297 mapLLVMRegToDwarfReg(X86::CR1, -1, false ); 5298 mapLLVMRegToDwarfReg(X86::CR2, -1, false ); 5299 mapLLVMRegToDwarfReg(X86::CR3, -1, false ); 5300 mapLLVMRegToDwarfReg(X86::CR4, -1, false ); 5301 mapLLVMRegToDwarfReg(X86::CR5, -1, false ); 5302 mapLLVMRegToDwarfReg(X86::CR6, -1, false ); 5303 mapLLVMRegToDwarfReg(X86::CR7, -1, false ); 5304 mapLLVMRegToDwarfReg(X86::CR8, -1, false ); 5305 mapLLVMRegToDwarfReg(X86::CR9, -1, false ); 5306 mapLLVMRegToDwarfReg(X86::CR10, -1, false ); 5307 mapLLVMRegToDwarfReg(X86::CR11, -1, false ); 5308 mapLLVMRegToDwarfReg(X86::CR12, -1, false ); 5309 mapLLVMRegToDwarfReg(X86::CR13, -1, false ); 5310 mapLLVMRegToDwarfReg(X86::CR14, -1, false ); 5311 mapLLVMRegToDwarfReg(X86::CR15, -1, false ); 5312 mapLLVMRegToDwarfReg(X86::CS, -1, false ); 5313 mapLLVMRegToDwarfReg(X86::CX, -1, false ); 5314 mapLLVMRegToDwarfReg(X86::DH, -1, false ); 5315 mapLLVMRegToDwarfReg(X86::DI, -1, false ); 5316 mapLLVMRegToDwarfReg(X86::DIL, -1, false ); 5317 mapLLVMRegToDwarfReg(X86::DL, -1, false ); 5318 mapLLVMRegToDwarfReg(X86::DR0, -1, false ); 5319 mapLLVMRegToDwarfReg(X86::DR1, -1, false ); 5320 mapLLVMRegToDwarfReg(X86::DR2, -1, false ); 5321 mapLLVMRegToDwarfReg(X86::DR3, -1, false ); 5322 mapLLVMRegToDwarfReg(X86::DR4, -1, false ); 5323 mapLLVMRegToDwarfReg(X86::DR5, -1, false ); 5324 mapLLVMRegToDwarfReg(X86::DR6, -1, false ); 5325 mapLLVMRegToDwarfReg(X86::DR7, -1, false ); 5326 mapLLVMRegToDwarfReg(X86::DS, -1, false ); 5327 mapLLVMRegToDwarfReg(X86::DX, -1, false ); 5328 mapLLVMRegToDwarfReg(X86::EAX, -2, false ); 5329 mapLLVMRegToDwarfReg(X86::EBP, -2, false ); 5330 mapLLVMRegToDwarfReg(X86::EBX, -2, false ); 5331 mapLLVMRegToDwarfReg(X86::ECX, -2, false ); 5332 mapLLVMRegToDwarfReg(X86::EDI, -2, false ); 5333 mapLLVMRegToDwarfReg(X86::EDX, -2, false ); 5334 mapLLVMRegToDwarfReg(X86::EFLAGS, -1, false ); 5335 mapLLVMRegToDwarfReg(X86::EIP, -2, false ); 5336 mapLLVMRegToDwarfReg(X86::EIZ, -1, false ); 5337 mapLLVMRegToDwarfReg(X86::ES, -1, false ); 5338 mapLLVMRegToDwarfReg(X86::ESI, -2, false ); 5339 mapLLVMRegToDwarfReg(X86::ESP, -2, false ); 5340 mapLLVMRegToDwarfReg(X86::FP0, -1, false ); 5341 mapLLVMRegToDwarfReg(X86::FP1, -1, false ); 5342 mapLLVMRegToDwarfReg(X86::FP2, -1, false ); 5343 mapLLVMRegToDwarfReg(X86::FP3, -1, false ); 5344 mapLLVMRegToDwarfReg(X86::FP4, -1, false ); 5345 mapLLVMRegToDwarfReg(X86::FP5, -1, false ); 5346 mapLLVMRegToDwarfReg(X86::FP6, -1, false ); 5347 mapLLVMRegToDwarfReg(X86::FS, -1, false ); 5348 mapLLVMRegToDwarfReg(X86::GS, -1, false ); 5349 mapLLVMRegToDwarfReg(X86::IP, -1, false ); 5350 mapLLVMRegToDwarfReg(X86::MM0, 41, false ); 5351 mapLLVMRegToDwarfReg(X86::MM1, 42, false ); 5352 mapLLVMRegToDwarfReg(X86::MM2, 43, false ); 5353 mapLLVMRegToDwarfReg(X86::MM3, 44, false ); 5354 mapLLVMRegToDwarfReg(X86::MM4, 45, false ); 5355 mapLLVMRegToDwarfReg(X86::MM5, 46, false ); 5356 mapLLVMRegToDwarfReg(X86::MM6, 47, false ); 5357 mapLLVMRegToDwarfReg(X86::MM7, 48, false ); 5358 mapLLVMRegToDwarfReg(X86::R8, 8, false ); 5359 mapLLVMRegToDwarfReg(X86::R8B, -1, false ); 5360 mapLLVMRegToDwarfReg(X86::R8D, -1, false ); 5361 mapLLVMRegToDwarfReg(X86::R8W, -1, false ); 5362 mapLLVMRegToDwarfReg(X86::R9, 9, false ); 5363 mapLLVMRegToDwarfReg(X86::R9B, -1, false ); 5364 mapLLVMRegToDwarfReg(X86::R9D, -1, false ); 5365 mapLLVMRegToDwarfReg(X86::R9W, -1, false ); 5366 mapLLVMRegToDwarfReg(X86::R10, 10, false ); 5367 mapLLVMRegToDwarfReg(X86::R10B, -1, false ); 5368 mapLLVMRegToDwarfReg(X86::R10D, -1, false ); 5369 mapLLVMRegToDwarfReg(X86::R10W, -1, false ); 5370 mapLLVMRegToDwarfReg(X86::R11, 11, false ); 5371 mapLLVMRegToDwarfReg(X86::R11B, -1, false ); 5372 mapLLVMRegToDwarfReg(X86::R11D, -1, false ); 5373 mapLLVMRegToDwarfReg(X86::R11W, -1, false ); 5374 mapLLVMRegToDwarfReg(X86::R12, 12, false ); 5375 mapLLVMRegToDwarfReg(X86::R12B, -1, false ); 5376 mapLLVMRegToDwarfReg(X86::R12D, -1, false ); 5377 mapLLVMRegToDwarfReg(X86::R12W, -1, false ); 5378 mapLLVMRegToDwarfReg(X86::R13, 13, false ); 5379 mapLLVMRegToDwarfReg(X86::R13B, -1, false ); 5380 mapLLVMRegToDwarfReg(X86::R13D, -1, false ); 5381 mapLLVMRegToDwarfReg(X86::R13W, -1, false ); 5382 mapLLVMRegToDwarfReg(X86::R14, 14, false ); 5383 mapLLVMRegToDwarfReg(X86::R14B, -1, false ); 5384 mapLLVMRegToDwarfReg(X86::R14D, -1, false ); 5385 mapLLVMRegToDwarfReg(X86::R14W, -1, false ); 5386 mapLLVMRegToDwarfReg(X86::R15, 15, false ); 5387 mapLLVMRegToDwarfReg(X86::R15B, -1, false ); 5388 mapLLVMRegToDwarfReg(X86::R15D, -1, false ); 5389 mapLLVMRegToDwarfReg(X86::R15W, -1, false ); 5390 mapLLVMRegToDwarfReg(X86::RAX, 0, false ); 5391 mapLLVMRegToDwarfReg(X86::RBP, 6, false ); 5392 mapLLVMRegToDwarfReg(X86::RBX, 3, false ); 5393 mapLLVMRegToDwarfReg(X86::RCX, 2, false ); 5394 mapLLVMRegToDwarfReg(X86::RDI, 5, false ); 5395 mapLLVMRegToDwarfReg(X86::RDX, 1, false ); 5396 mapLLVMRegToDwarfReg(X86::RIP, 16, false ); 5397 mapLLVMRegToDwarfReg(X86::RIZ, -1, false ); 5398 mapLLVMRegToDwarfReg(X86::RSI, 4, false ); 5399 mapLLVMRegToDwarfReg(X86::RSP, 7, false ); 5400 mapLLVMRegToDwarfReg(X86::SI, -1, false ); 5401 mapLLVMRegToDwarfReg(X86::SIL, -1, false ); 5402 mapLLVMRegToDwarfReg(X86::SP, -1, false ); 5403 mapLLVMRegToDwarfReg(X86::SPL, -1, false ); 5404 mapLLVMRegToDwarfReg(X86::SS, -1, false ); 5405 mapLLVMRegToDwarfReg(X86::ST0, 33, false ); 5406 mapLLVMRegToDwarfReg(X86::ST1, 34, false ); 5407 mapLLVMRegToDwarfReg(X86::ST2, 35, false ); 5408 mapLLVMRegToDwarfReg(X86::ST3, 36, false ); 5409 mapLLVMRegToDwarfReg(X86::ST4, 37, false ); 5410 mapLLVMRegToDwarfReg(X86::ST5, 38, false ); 5411 mapLLVMRegToDwarfReg(X86::ST6, 39, false ); 5412 mapLLVMRegToDwarfReg(X86::ST7, 40, false ); 5413 mapLLVMRegToDwarfReg(X86::XMM0, 17, false ); 5414 mapLLVMRegToDwarfReg(X86::XMM1, 18, false ); 5415 mapLLVMRegToDwarfReg(X86::XMM2, 19, false ); 5416 mapLLVMRegToDwarfReg(X86::XMM3, 20, false ); 5417 mapLLVMRegToDwarfReg(X86::XMM4, 21, false ); 5418 mapLLVMRegToDwarfReg(X86::XMM5, 22, false ); 5419 mapLLVMRegToDwarfReg(X86::XMM6, 23, false ); 5420 mapLLVMRegToDwarfReg(X86::XMM7, 24, false ); 5421 mapLLVMRegToDwarfReg(X86::XMM8, 25, false ); 5422 mapLLVMRegToDwarfReg(X86::XMM9, 26, false ); 5423 mapLLVMRegToDwarfReg(X86::XMM10, 27, false ); 5424 mapLLVMRegToDwarfReg(X86::XMM11, 28, false ); 5425 mapLLVMRegToDwarfReg(X86::XMM12, 29, false ); 5426 mapLLVMRegToDwarfReg(X86::XMM13, 30, false ); 5427 mapLLVMRegToDwarfReg(X86::XMM14, 31, false ); 5428 mapLLVMRegToDwarfReg(X86::XMM15, 32, false ); 5429 mapLLVMRegToDwarfReg(X86::YMM0, 17, false ); 5430 mapLLVMRegToDwarfReg(X86::YMM1, 18, false ); 5431 mapLLVMRegToDwarfReg(X86::YMM2, 19, false ); 5432 mapLLVMRegToDwarfReg(X86::YMM3, 20, false ); 5433 mapLLVMRegToDwarfReg(X86::YMM4, 21, false ); 5434 mapLLVMRegToDwarfReg(X86::YMM5, 22, false ); 5435 mapLLVMRegToDwarfReg(X86::YMM6, 23, false ); 5436 mapLLVMRegToDwarfReg(X86::YMM7, 24, false ); 5437 mapLLVMRegToDwarfReg(X86::YMM8, 25, false ); 5438 mapLLVMRegToDwarfReg(X86::YMM9, 26, false ); 5439 mapLLVMRegToDwarfReg(X86::YMM10, 27, false ); 5440 mapLLVMRegToDwarfReg(X86::YMM11, 28, false ); 5441 mapLLVMRegToDwarfReg(X86::YMM12, 29, false ); 5442 mapLLVMRegToDwarfReg(X86::YMM13, 30, false ); 5443 mapLLVMRegToDwarfReg(X86::YMM14, 31, false ); 5444 mapLLVMRegToDwarfReg(X86::YMM15, 32, false ); 5445 break; 5446 case 1: 5447 mapLLVMRegToDwarfReg(X86::AH, -1, false ); 5448 mapLLVMRegToDwarfReg(X86::AL, -1, false ); 5449 mapLLVMRegToDwarfReg(X86::AX, -1, false ); 5450 mapLLVMRegToDwarfReg(X86::BH, -1, false ); 5451 mapLLVMRegToDwarfReg(X86::BL, -1, false ); 5452 mapLLVMRegToDwarfReg(X86::BP, -1, false ); 5453 mapLLVMRegToDwarfReg(X86::BPL, -1, false ); 5454 mapLLVMRegToDwarfReg(X86::BX, -1, false ); 5455 mapLLVMRegToDwarfReg(X86::CH, -1, false ); 5456 mapLLVMRegToDwarfReg(X86::CL, -1, false ); 5457 mapLLVMRegToDwarfReg(X86::CR0, -1, false ); 5458 mapLLVMRegToDwarfReg(X86::CR1, -1, false ); 5459 mapLLVMRegToDwarfReg(X86::CR2, -1, false ); 5460 mapLLVMRegToDwarfReg(X86::CR3, -1, false ); 5461 mapLLVMRegToDwarfReg(X86::CR4, -1, false ); 5462 mapLLVMRegToDwarfReg(X86::CR5, -1, false ); 5463 mapLLVMRegToDwarfReg(X86::CR6, -1, false ); 5464 mapLLVMRegToDwarfReg(X86::CR7, -1, false ); 5465 mapLLVMRegToDwarfReg(X86::CR8, -1, false ); 5466 mapLLVMRegToDwarfReg(X86::CR9, -1, false ); 5467 mapLLVMRegToDwarfReg(X86::CR10, -1, false ); 5468 mapLLVMRegToDwarfReg(X86::CR11, -1, false ); 5469 mapLLVMRegToDwarfReg(X86::CR12, -1, false ); 5470 mapLLVMRegToDwarfReg(X86::CR13, -1, false ); 5471 mapLLVMRegToDwarfReg(X86::CR14, -1, false ); 5472 mapLLVMRegToDwarfReg(X86::CR15, -1, false ); 5473 mapLLVMRegToDwarfReg(X86::CS, -1, false ); 5474 mapLLVMRegToDwarfReg(X86::CX, -1, false ); 5475 mapLLVMRegToDwarfReg(X86::DH, -1, false ); 5476 mapLLVMRegToDwarfReg(X86::DI, -1, false ); 5477 mapLLVMRegToDwarfReg(X86::DIL, -1, false ); 5478 mapLLVMRegToDwarfReg(X86::DL, -1, false ); 5479 mapLLVMRegToDwarfReg(X86::DR0, -1, false ); 5480 mapLLVMRegToDwarfReg(X86::DR1, -1, false ); 5481 mapLLVMRegToDwarfReg(X86::DR2, -1, false ); 5482 mapLLVMRegToDwarfReg(X86::DR3, -1, false ); 5483 mapLLVMRegToDwarfReg(X86::DR4, -1, false ); 5484 mapLLVMRegToDwarfReg(X86::DR5, -1, false ); 5485 mapLLVMRegToDwarfReg(X86::DR6, -1, false ); 5486 mapLLVMRegToDwarfReg(X86::DR7, -1, false ); 5487 mapLLVMRegToDwarfReg(X86::DS, -1, false ); 5488 mapLLVMRegToDwarfReg(X86::DX, -1, false ); 5489 mapLLVMRegToDwarfReg(X86::EAX, 0, false ); 5490 mapLLVMRegToDwarfReg(X86::EBP, 4, false ); 5491 mapLLVMRegToDwarfReg(X86::EBX, 3, false ); 5492 mapLLVMRegToDwarfReg(X86::ECX, 1, false ); 5493 mapLLVMRegToDwarfReg(X86::EDI, 7, false ); 5494 mapLLVMRegToDwarfReg(X86::EDX, 2, false ); 5495 mapLLVMRegToDwarfReg(X86::EFLAGS, -1, false ); 5496 mapLLVMRegToDwarfReg(X86::EIP, 8, false ); 5497 mapLLVMRegToDwarfReg(X86::EIZ, -1, false ); 5498 mapLLVMRegToDwarfReg(X86::ES, -1, false ); 5499 mapLLVMRegToDwarfReg(X86::ESI, 6, false ); 5500 mapLLVMRegToDwarfReg(X86::ESP, 5, false ); 5501 mapLLVMRegToDwarfReg(X86::FP0, -1, false ); 5502 mapLLVMRegToDwarfReg(X86::FP1, -1, false ); 5503 mapLLVMRegToDwarfReg(X86::FP2, -1, false ); 5504 mapLLVMRegToDwarfReg(X86::FP3, -1, false ); 5505 mapLLVMRegToDwarfReg(X86::FP4, -1, false ); 5506 mapLLVMRegToDwarfReg(X86::FP5, -1, false ); 5507 mapLLVMRegToDwarfReg(X86::FP6, -1, false ); 5508 mapLLVMRegToDwarfReg(X86::FS, -1, false ); 5509 mapLLVMRegToDwarfReg(X86::GS, -1, false ); 5510 mapLLVMRegToDwarfReg(X86::IP, -1, false ); 5511 mapLLVMRegToDwarfReg(X86::MM0, 29, false ); 5512 mapLLVMRegToDwarfReg(X86::MM1, 30, false ); 5513 mapLLVMRegToDwarfReg(X86::MM2, 31, false ); 5514 mapLLVMRegToDwarfReg(X86::MM3, 32, false ); 5515 mapLLVMRegToDwarfReg(X86::MM4, 33, false ); 5516 mapLLVMRegToDwarfReg(X86::MM5, 34, false ); 5517 mapLLVMRegToDwarfReg(X86::MM6, 35, false ); 5518 mapLLVMRegToDwarfReg(X86::MM7, 36, false ); 5519 mapLLVMRegToDwarfReg(X86::R8, -2, false ); 5520 mapLLVMRegToDwarfReg(X86::R8B, -1, false ); 5521 mapLLVMRegToDwarfReg(X86::R8D, -1, false ); 5522 mapLLVMRegToDwarfReg(X86::R8W, -1, false ); 5523 mapLLVMRegToDwarfReg(X86::R9, -2, false ); 5524 mapLLVMRegToDwarfReg(X86::R9B, -1, false ); 5525 mapLLVMRegToDwarfReg(X86::R9D, -1, false ); 5526 mapLLVMRegToDwarfReg(X86::R9W, -1, false ); 5527 mapLLVMRegToDwarfReg(X86::R10, -2, false ); 5528 mapLLVMRegToDwarfReg(X86::R10B, -1, false ); 5529 mapLLVMRegToDwarfReg(X86::R10D, -1, false ); 5530 mapLLVMRegToDwarfReg(X86::R10W, -1, false ); 5531 mapLLVMRegToDwarfReg(X86::R11, -2, false ); 5532 mapLLVMRegToDwarfReg(X86::R11B, -1, false ); 5533 mapLLVMRegToDwarfReg(X86::R11D, -1, false ); 5534 mapLLVMRegToDwarfReg(X86::R11W, -1, false ); 5535 mapLLVMRegToDwarfReg(X86::R12, -2, false ); 5536 mapLLVMRegToDwarfReg(X86::R12B, -1, false ); 5537 mapLLVMRegToDwarfReg(X86::R12D, -1, false ); 5538 mapLLVMRegToDwarfReg(X86::R12W, -1, false ); 5539 mapLLVMRegToDwarfReg(X86::R13, -2, false ); 5540 mapLLVMRegToDwarfReg(X86::R13B, -1, false ); 5541 mapLLVMRegToDwarfReg(X86::R13D, -1, false ); 5542 mapLLVMRegToDwarfReg(X86::R13W, -1, false ); 5543 mapLLVMRegToDwarfReg(X86::R14, -2, false ); 5544 mapLLVMRegToDwarfReg(X86::R14B, -1, false ); 5545 mapLLVMRegToDwarfReg(X86::R14D, -1, false ); 5546 mapLLVMRegToDwarfReg(X86::R14W, -1, false ); 5547 mapLLVMRegToDwarfReg(X86::R15, -2, false ); 5548 mapLLVMRegToDwarfReg(X86::R15B, -1, false ); 5549 mapLLVMRegToDwarfReg(X86::R15D, -1, false ); 5550 mapLLVMRegToDwarfReg(X86::R15W, -1, false ); 5551 mapLLVMRegToDwarfReg(X86::RAX, -2, false ); 5552 mapLLVMRegToDwarfReg(X86::RBP, -2, false ); 5553 mapLLVMRegToDwarfReg(X86::RBX, -2, false ); 5554 mapLLVMRegToDwarfReg(X86::RCX, -2, false ); 5555 mapLLVMRegToDwarfReg(X86::RDI, -2, false ); 5556 mapLLVMRegToDwarfReg(X86::RDX, -2, false ); 5557 mapLLVMRegToDwarfReg(X86::RIP, -2, false ); 5558 mapLLVMRegToDwarfReg(X86::RIZ, -1, false ); 5559 mapLLVMRegToDwarfReg(X86::RSI, -2, false ); 5560 mapLLVMRegToDwarfReg(X86::RSP, -2, false ); 5561 mapLLVMRegToDwarfReg(X86::SI, -1, false ); 5562 mapLLVMRegToDwarfReg(X86::SIL, -1, false ); 5563 mapLLVMRegToDwarfReg(X86::SP, -1, false ); 5564 mapLLVMRegToDwarfReg(X86::SPL, -1, false ); 5565 mapLLVMRegToDwarfReg(X86::SS, -1, false ); 5566 mapLLVMRegToDwarfReg(X86::ST0, 12, false ); 5567 mapLLVMRegToDwarfReg(X86::ST1, 13, false ); 5568 mapLLVMRegToDwarfReg(X86::ST2, 14, false ); 5569 mapLLVMRegToDwarfReg(X86::ST3, 15, false ); 5570 mapLLVMRegToDwarfReg(X86::ST4, 16, false ); 5571 mapLLVMRegToDwarfReg(X86::ST5, 17, false ); 5572 mapLLVMRegToDwarfReg(X86::ST6, 18, false ); 5573 mapLLVMRegToDwarfReg(X86::ST7, 19, false ); 5574 mapLLVMRegToDwarfReg(X86::XMM0, 21, false ); 5575 mapLLVMRegToDwarfReg(X86::XMM1, 22, false ); 5576 mapLLVMRegToDwarfReg(X86::XMM2, 23, false ); 5577 mapLLVMRegToDwarfReg(X86::XMM3, 24, false ); 5578 mapLLVMRegToDwarfReg(X86::XMM4, 25, false ); 5579 mapLLVMRegToDwarfReg(X86::XMM5, 26, false ); 5580 mapLLVMRegToDwarfReg(X86::XMM6, 27, false ); 5581 mapLLVMRegToDwarfReg(X86::XMM7, 28, false ); 5582 mapLLVMRegToDwarfReg(X86::XMM8, -2, false ); 5583 mapLLVMRegToDwarfReg(X86::XMM9, -2, false ); 5584 mapLLVMRegToDwarfReg(X86::XMM10, -2, false ); 5585 mapLLVMRegToDwarfReg(X86::XMM11, -2, false ); 5586 mapLLVMRegToDwarfReg(X86::XMM12, -2, false ); 5587 mapLLVMRegToDwarfReg(X86::XMM13, -2, false ); 5588 mapLLVMRegToDwarfReg(X86::XMM14, -2, false ); 5589 mapLLVMRegToDwarfReg(X86::XMM15, -2, false ); 5590 mapLLVMRegToDwarfReg(X86::YMM0, 21, false ); 5591 mapLLVMRegToDwarfReg(X86::YMM1, 22, false ); 5592 mapLLVMRegToDwarfReg(X86::YMM2, 23, false ); 5593 mapLLVMRegToDwarfReg(X86::YMM3, 24, false ); 5594 mapLLVMRegToDwarfReg(X86::YMM4, 25, false ); 5595 mapLLVMRegToDwarfReg(X86::YMM5, 26, false ); 5596 mapLLVMRegToDwarfReg(X86::YMM6, 27, false ); 5597 mapLLVMRegToDwarfReg(X86::YMM7, 28, false ); 5598 mapLLVMRegToDwarfReg(X86::YMM8, -2, false ); 5599 mapLLVMRegToDwarfReg(X86::YMM9, -2, false ); 5600 mapLLVMRegToDwarfReg(X86::YMM10, -2, false ); 5601 mapLLVMRegToDwarfReg(X86::YMM11, -2, false ); 5602 mapLLVMRegToDwarfReg(X86::YMM12, -2, false ); 5603 mapLLVMRegToDwarfReg(X86::YMM13, -2, false ); 5604 mapLLVMRegToDwarfReg(X86::YMM14, -2, false ); 5605 mapLLVMRegToDwarfReg(X86::YMM15, -2, false ); 5606 break; 5607 case 2: 5608 mapLLVMRegToDwarfReg(X86::AH, -1, false ); 5609 mapLLVMRegToDwarfReg(X86::AL, -1, false ); 5610 mapLLVMRegToDwarfReg(X86::AX, -1, false ); 5611 mapLLVMRegToDwarfReg(X86::BH, -1, false ); 5612 mapLLVMRegToDwarfReg(X86::BL, -1, false ); 5613 mapLLVMRegToDwarfReg(X86::BP, -1, false ); 5614 mapLLVMRegToDwarfReg(X86::BPL, -1, false ); 5615 mapLLVMRegToDwarfReg(X86::BX, -1, false ); 5616 mapLLVMRegToDwarfReg(X86::CH, -1, false ); 5617 mapLLVMRegToDwarfReg(X86::CL, -1, false ); 5618 mapLLVMRegToDwarfReg(X86::CR0, -1, false ); 5619 mapLLVMRegToDwarfReg(X86::CR1, -1, false ); 5620 mapLLVMRegToDwarfReg(X86::CR2, -1, false ); 5621 mapLLVMRegToDwarfReg(X86::CR3, -1, false ); 5622 mapLLVMRegToDwarfReg(X86::CR4, -1, false ); 5623 mapLLVMRegToDwarfReg(X86::CR5, -1, false ); 5624 mapLLVMRegToDwarfReg(X86::CR6, -1, false ); 5625 mapLLVMRegToDwarfReg(X86::CR7, -1, false ); 5626 mapLLVMRegToDwarfReg(X86::CR8, -1, false ); 5627 mapLLVMRegToDwarfReg(X86::CR9, -1, false ); 5628 mapLLVMRegToDwarfReg(X86::CR10, -1, false ); 5629 mapLLVMRegToDwarfReg(X86::CR11, -1, false ); 5630 mapLLVMRegToDwarfReg(X86::CR12, -1, false ); 5631 mapLLVMRegToDwarfReg(X86::CR13, -1, false ); 5632 mapLLVMRegToDwarfReg(X86::CR14, -1, false ); 5633 mapLLVMRegToDwarfReg(X86::CR15, -1, false ); 5634 mapLLVMRegToDwarfReg(X86::CS, -1, false ); 5635 mapLLVMRegToDwarfReg(X86::CX, -1, false ); 5636 mapLLVMRegToDwarfReg(X86::DH, -1, false ); 5637 mapLLVMRegToDwarfReg(X86::DI, -1, false ); 5638 mapLLVMRegToDwarfReg(X86::DIL, -1, false ); 5639 mapLLVMRegToDwarfReg(X86::DL, -1, false ); 5640 mapLLVMRegToDwarfReg(X86::DR0, -1, false ); 5641 mapLLVMRegToDwarfReg(X86::DR1, -1, false ); 5642 mapLLVMRegToDwarfReg(X86::DR2, -1, false ); 5643 mapLLVMRegToDwarfReg(X86::DR3, -1, false ); 5644 mapLLVMRegToDwarfReg(X86::DR4, -1, false ); 5645 mapLLVMRegToDwarfReg(X86::DR5, -1, false ); 5646 mapLLVMRegToDwarfReg(X86::DR6, -1, false ); 5647 mapLLVMRegToDwarfReg(X86::DR7, -1, false ); 5648 mapLLVMRegToDwarfReg(X86::DS, -1, false ); 5649 mapLLVMRegToDwarfReg(X86::DX, -1, false ); 5650 mapLLVMRegToDwarfReg(X86::EAX, 0, false ); 5651 mapLLVMRegToDwarfReg(X86::EBP, 5, false ); 5652 mapLLVMRegToDwarfReg(X86::EBX, 3, false ); 5653 mapLLVMRegToDwarfReg(X86::ECX, 1, false ); 5654 mapLLVMRegToDwarfReg(X86::EDI, 7, false ); 5655 mapLLVMRegToDwarfReg(X86::EDX, 2, false ); 5656 mapLLVMRegToDwarfReg(X86::EFLAGS, -1, false ); 5657 mapLLVMRegToDwarfReg(X86::EIP, 8, false ); 5658 mapLLVMRegToDwarfReg(X86::EIZ, -1, false ); 5659 mapLLVMRegToDwarfReg(X86::ES, -1, false ); 5660 mapLLVMRegToDwarfReg(X86::ESI, 6, false ); 5661 mapLLVMRegToDwarfReg(X86::ESP, 4, false ); 5662 mapLLVMRegToDwarfReg(X86::FP0, -1, false ); 5663 mapLLVMRegToDwarfReg(X86::FP1, -1, false ); 5664 mapLLVMRegToDwarfReg(X86::FP2, -1, false ); 5665 mapLLVMRegToDwarfReg(X86::FP3, -1, false ); 5666 mapLLVMRegToDwarfReg(X86::FP4, -1, false ); 5667 mapLLVMRegToDwarfReg(X86::FP5, -1, false ); 5668 mapLLVMRegToDwarfReg(X86::FP6, -1, false ); 5669 mapLLVMRegToDwarfReg(X86::FS, -1, false ); 5670 mapLLVMRegToDwarfReg(X86::GS, -1, false ); 5671 mapLLVMRegToDwarfReg(X86::IP, -1, false ); 5672 mapLLVMRegToDwarfReg(X86::MM0, 29, false ); 5673 mapLLVMRegToDwarfReg(X86::MM1, 30, false ); 5674 mapLLVMRegToDwarfReg(X86::MM2, 31, false ); 5675 mapLLVMRegToDwarfReg(X86::MM3, 32, false ); 5676 mapLLVMRegToDwarfReg(X86::MM4, 33, false ); 5677 mapLLVMRegToDwarfReg(X86::MM5, 34, false ); 5678 mapLLVMRegToDwarfReg(X86::MM6, 35, false ); 5679 mapLLVMRegToDwarfReg(X86::MM7, 36, false ); 5680 mapLLVMRegToDwarfReg(X86::R8, -2, false ); 5681 mapLLVMRegToDwarfReg(X86::R8B, -1, false ); 5682 mapLLVMRegToDwarfReg(X86::R8D, -1, false ); 5683 mapLLVMRegToDwarfReg(X86::R8W, -1, false ); 5684 mapLLVMRegToDwarfReg(X86::R9, -2, false ); 5685 mapLLVMRegToDwarfReg(X86::R9B, -1, false ); 5686 mapLLVMRegToDwarfReg(X86::R9D, -1, false ); 5687 mapLLVMRegToDwarfReg(X86::R9W, -1, false ); 5688 mapLLVMRegToDwarfReg(X86::R10, -2, false ); 5689 mapLLVMRegToDwarfReg(X86::R10B, -1, false ); 5690 mapLLVMRegToDwarfReg(X86::R10D, -1, false ); 5691 mapLLVMRegToDwarfReg(X86::R10W, -1, false ); 5692 mapLLVMRegToDwarfReg(X86::R11, -2, false ); 5693 mapLLVMRegToDwarfReg(X86::R11B, -1, false ); 5694 mapLLVMRegToDwarfReg(X86::R11D, -1, false ); 5695 mapLLVMRegToDwarfReg(X86::R11W, -1, false ); 5696 mapLLVMRegToDwarfReg(X86::R12, -2, false ); 5697 mapLLVMRegToDwarfReg(X86::R12B, -1, false ); 5698 mapLLVMRegToDwarfReg(X86::R12D, -1, false ); 5699 mapLLVMRegToDwarfReg(X86::R12W, -1, false ); 5700 mapLLVMRegToDwarfReg(X86::R13, -2, false ); 5701 mapLLVMRegToDwarfReg(X86::R13B, -1, false ); 5702 mapLLVMRegToDwarfReg(X86::R13D, -1, false ); 5703 mapLLVMRegToDwarfReg(X86::R13W, -1, false ); 5704 mapLLVMRegToDwarfReg(X86::R14, -2, false ); 5705 mapLLVMRegToDwarfReg(X86::R14B, -1, false ); 5706 mapLLVMRegToDwarfReg(X86::R14D, -1, false ); 5707 mapLLVMRegToDwarfReg(X86::R14W, -1, false ); 5708 mapLLVMRegToDwarfReg(X86::R15, -2, false ); 5709 mapLLVMRegToDwarfReg(X86::R15B, -1, false ); 5710 mapLLVMRegToDwarfReg(X86::R15D, -1, false ); 5711 mapLLVMRegToDwarfReg(X86::R15W, -1, false ); 5712 mapLLVMRegToDwarfReg(X86::RAX, -2, false ); 5713 mapLLVMRegToDwarfReg(X86::RBP, -2, false ); 5714 mapLLVMRegToDwarfReg(X86::RBX, -2, false ); 5715 mapLLVMRegToDwarfReg(X86::RCX, -2, false ); 5716 mapLLVMRegToDwarfReg(X86::RDI, -2, false ); 5717 mapLLVMRegToDwarfReg(X86::RDX, -2, false ); 5718 mapLLVMRegToDwarfReg(X86::RIP, -2, false ); 5719 mapLLVMRegToDwarfReg(X86::RIZ, -1, false ); 5720 mapLLVMRegToDwarfReg(X86::RSI, -2, false ); 5721 mapLLVMRegToDwarfReg(X86::RSP, -2, false ); 5722 mapLLVMRegToDwarfReg(X86::SI, -1, false ); 5723 mapLLVMRegToDwarfReg(X86::SIL, -1, false ); 5724 mapLLVMRegToDwarfReg(X86::SP, -1, false ); 5725 mapLLVMRegToDwarfReg(X86::SPL, -1, false ); 5726 mapLLVMRegToDwarfReg(X86::SS, -1, false ); 5727 mapLLVMRegToDwarfReg(X86::ST0, 11, false ); 5728 mapLLVMRegToDwarfReg(X86::ST1, 12, false ); 5729 mapLLVMRegToDwarfReg(X86::ST2, 13, false ); 5730 mapLLVMRegToDwarfReg(X86::ST3, 14, false ); 5731 mapLLVMRegToDwarfReg(X86::ST4, 15, false ); 5732 mapLLVMRegToDwarfReg(X86::ST5, 16, false ); 5733 mapLLVMRegToDwarfReg(X86::ST6, 17, false ); 5734 mapLLVMRegToDwarfReg(X86::ST7, 18, false ); 5735 mapLLVMRegToDwarfReg(X86::XMM0, 21, false ); 5736 mapLLVMRegToDwarfReg(X86::XMM1, 22, false ); 5737 mapLLVMRegToDwarfReg(X86::XMM2, 23, false ); 5738 mapLLVMRegToDwarfReg(X86::XMM3, 24, false ); 5739 mapLLVMRegToDwarfReg(X86::XMM4, 25, false ); 5740 mapLLVMRegToDwarfReg(X86::XMM5, 26, false ); 5741 mapLLVMRegToDwarfReg(X86::XMM6, 27, false ); 5742 mapLLVMRegToDwarfReg(X86::XMM7, 28, false ); 5743 mapLLVMRegToDwarfReg(X86::XMM8, -2, false ); 5744 mapLLVMRegToDwarfReg(X86::XMM9, -2, false ); 5745 mapLLVMRegToDwarfReg(X86::XMM10, -2, false ); 5746 mapLLVMRegToDwarfReg(X86::XMM11, -2, false ); 5747 mapLLVMRegToDwarfReg(X86::XMM12, -2, false ); 5748 mapLLVMRegToDwarfReg(X86::XMM13, -2, false ); 5749 mapLLVMRegToDwarfReg(X86::XMM14, -2, false ); 5750 mapLLVMRegToDwarfReg(X86::XMM15, -2, false ); 5751 mapLLVMRegToDwarfReg(X86::YMM0, 21, false ); 5752 mapLLVMRegToDwarfReg(X86::YMM1, 22, false ); 5753 mapLLVMRegToDwarfReg(X86::YMM2, 23, false ); 5754 mapLLVMRegToDwarfReg(X86::YMM3, 24, false ); 5755 mapLLVMRegToDwarfReg(X86::YMM4, 25, false ); 5756 mapLLVMRegToDwarfReg(X86::YMM5, 26, false ); 5757 mapLLVMRegToDwarfReg(X86::YMM6, 27, false ); 5758 mapLLVMRegToDwarfReg(X86::YMM7, 28, false ); 5759 mapLLVMRegToDwarfReg(X86::YMM8, -2, false ); 5760 mapLLVMRegToDwarfReg(X86::YMM9, -2, false ); 5761 mapLLVMRegToDwarfReg(X86::YMM10, -2, false ); 5762 mapLLVMRegToDwarfReg(X86::YMM11, -2, false ); 5763 mapLLVMRegToDwarfReg(X86::YMM12, -2, false ); 5764 mapLLVMRegToDwarfReg(X86::YMM13, -2, false ); 5765 mapLLVMRegToDwarfReg(X86::YMM14, -2, false ); 5766 mapLLVMRegToDwarfReg(X86::YMM15, -2, false ); 5767 break; 5768 } 5769 switch (EHFlavour) { 5770 default: 5771 assert(0 && "Unknown DWARF flavour"); 5772 break; 5773 case 0: 5774 mapLLVMRegToDwarfReg(X86::AH, -1, true ); 5775 mapLLVMRegToDwarfReg(X86::AL, -1, true ); 5776 mapLLVMRegToDwarfReg(X86::AX, -1, true ); 5777 mapLLVMRegToDwarfReg(X86::BH, -1, true ); 5778 mapLLVMRegToDwarfReg(X86::BL, -1, true ); 5779 mapLLVMRegToDwarfReg(X86::BP, -1, true ); 5780 mapLLVMRegToDwarfReg(X86::BPL, -1, true ); 5781 mapLLVMRegToDwarfReg(X86::BX, -1, true ); 5782 mapLLVMRegToDwarfReg(X86::CH, -1, true ); 5783 mapLLVMRegToDwarfReg(X86::CL, -1, true ); 5784 mapLLVMRegToDwarfReg(X86::CR0, -1, true ); 5785 mapLLVMRegToDwarfReg(X86::CR1, -1, true ); 5786 mapLLVMRegToDwarfReg(X86::CR2, -1, true ); 5787 mapLLVMRegToDwarfReg(X86::CR3, -1, true ); 5788 mapLLVMRegToDwarfReg(X86::CR4, -1, true ); 5789 mapLLVMRegToDwarfReg(X86::CR5, -1, true ); 5790 mapLLVMRegToDwarfReg(X86::CR6, -1, true ); 5791 mapLLVMRegToDwarfReg(X86::CR7, -1, true ); 5792 mapLLVMRegToDwarfReg(X86::CR8, -1, true ); 5793 mapLLVMRegToDwarfReg(X86::CR9, -1, true ); 5794 mapLLVMRegToDwarfReg(X86::CR10, -1, true ); 5795 mapLLVMRegToDwarfReg(X86::CR11, -1, true ); 5796 mapLLVMRegToDwarfReg(X86::CR12, -1, true ); 5797 mapLLVMRegToDwarfReg(X86::CR13, -1, true ); 5798 mapLLVMRegToDwarfReg(X86::CR14, -1, true ); 5799 mapLLVMRegToDwarfReg(X86::CR15, -1, true ); 5800 mapLLVMRegToDwarfReg(X86::CS, -1, true ); 5801 mapLLVMRegToDwarfReg(X86::CX, -1, true ); 5802 mapLLVMRegToDwarfReg(X86::DH, -1, true ); 5803 mapLLVMRegToDwarfReg(X86::DI, -1, true ); 5804 mapLLVMRegToDwarfReg(X86::DIL, -1, true ); 5805 mapLLVMRegToDwarfReg(X86::DL, -1, true ); 5806 mapLLVMRegToDwarfReg(X86::DR0, -1, true ); 5807 mapLLVMRegToDwarfReg(X86::DR1, -1, true ); 5808 mapLLVMRegToDwarfReg(X86::DR2, -1, true ); 5809 mapLLVMRegToDwarfReg(X86::DR3, -1, true ); 5810 mapLLVMRegToDwarfReg(X86::DR4, -1, true ); 5811 mapLLVMRegToDwarfReg(X86::DR5, -1, true ); 5812 mapLLVMRegToDwarfReg(X86::DR6, -1, true ); 5813 mapLLVMRegToDwarfReg(X86::DR7, -1, true ); 5814 mapLLVMRegToDwarfReg(X86::DS, -1, true ); 5815 mapLLVMRegToDwarfReg(X86::DX, -1, true ); 5816 mapLLVMRegToDwarfReg(X86::EAX, -2, true ); 5817 mapLLVMRegToDwarfReg(X86::EBP, -2, true ); 5818 mapLLVMRegToDwarfReg(X86::EBX, -2, true ); 5819 mapLLVMRegToDwarfReg(X86::ECX, -2, true ); 5820 mapLLVMRegToDwarfReg(X86::EDI, -2, true ); 5821 mapLLVMRegToDwarfReg(X86::EDX, -2, true ); 5822 mapLLVMRegToDwarfReg(X86::EFLAGS, -1, true ); 5823 mapLLVMRegToDwarfReg(X86::EIP, -2, true ); 5824 mapLLVMRegToDwarfReg(X86::EIZ, -1, true ); 5825 mapLLVMRegToDwarfReg(X86::ES, -1, true ); 5826 mapLLVMRegToDwarfReg(X86::ESI, -2, true ); 5827 mapLLVMRegToDwarfReg(X86::ESP, -2, true ); 5828 mapLLVMRegToDwarfReg(X86::FP0, -1, true ); 5829 mapLLVMRegToDwarfReg(X86::FP1, -1, true ); 5830 mapLLVMRegToDwarfReg(X86::FP2, -1, true ); 5831 mapLLVMRegToDwarfReg(X86::FP3, -1, true ); 5832 mapLLVMRegToDwarfReg(X86::FP4, -1, true ); 5833 mapLLVMRegToDwarfReg(X86::FP5, -1, true ); 5834 mapLLVMRegToDwarfReg(X86::FP6, -1, true ); 5835 mapLLVMRegToDwarfReg(X86::FS, -1, true ); 5836 mapLLVMRegToDwarfReg(X86::GS, -1, true ); 5837 mapLLVMRegToDwarfReg(X86::IP, -1, true ); 5838 mapLLVMRegToDwarfReg(X86::MM0, 41, true ); 5839 mapLLVMRegToDwarfReg(X86::MM1, 42, true ); 5840 mapLLVMRegToDwarfReg(X86::MM2, 43, true ); 5841 mapLLVMRegToDwarfReg(X86::MM3, 44, true ); 5842 mapLLVMRegToDwarfReg(X86::MM4, 45, true ); 5843 mapLLVMRegToDwarfReg(X86::MM5, 46, true ); 5844 mapLLVMRegToDwarfReg(X86::MM6, 47, true ); 5845 mapLLVMRegToDwarfReg(X86::MM7, 48, true ); 5846 mapLLVMRegToDwarfReg(X86::R8, 8, true ); 5847 mapLLVMRegToDwarfReg(X86::R8B, -1, true ); 5848 mapLLVMRegToDwarfReg(X86::R8D, -1, true ); 5849 mapLLVMRegToDwarfReg(X86::R8W, -1, true ); 5850 mapLLVMRegToDwarfReg(X86::R9, 9, true ); 5851 mapLLVMRegToDwarfReg(X86::R9B, -1, true ); 5852 mapLLVMRegToDwarfReg(X86::R9D, -1, true ); 5853 mapLLVMRegToDwarfReg(X86::R9W, -1, true ); 5854 mapLLVMRegToDwarfReg(X86::R10, 10, true ); 5855 mapLLVMRegToDwarfReg(X86::R10B, -1, true ); 5856 mapLLVMRegToDwarfReg(X86::R10D, -1, true ); 5857 mapLLVMRegToDwarfReg(X86::R10W, -1, true ); 5858 mapLLVMRegToDwarfReg(X86::R11, 11, true ); 5859 mapLLVMRegToDwarfReg(X86::R11B, -1, true ); 5860 mapLLVMRegToDwarfReg(X86::R11D, -1, true ); 5861 mapLLVMRegToDwarfReg(X86::R11W, -1, true ); 5862 mapLLVMRegToDwarfReg(X86::R12, 12, true ); 5863 mapLLVMRegToDwarfReg(X86::R12B, -1, true ); 5864 mapLLVMRegToDwarfReg(X86::R12D, -1, true ); 5865 mapLLVMRegToDwarfReg(X86::R12W, -1, true ); 5866 mapLLVMRegToDwarfReg(X86::R13, 13, true ); 5867 mapLLVMRegToDwarfReg(X86::R13B, -1, true ); 5868 mapLLVMRegToDwarfReg(X86::R13D, -1, true ); 5869 mapLLVMRegToDwarfReg(X86::R13W, -1, true ); 5870 mapLLVMRegToDwarfReg(X86::R14, 14, true ); 5871 mapLLVMRegToDwarfReg(X86::R14B, -1, true ); 5872 mapLLVMRegToDwarfReg(X86::R14D, -1, true ); 5873 mapLLVMRegToDwarfReg(X86::R14W, -1, true ); 5874 mapLLVMRegToDwarfReg(X86::R15, 15, true ); 5875 mapLLVMRegToDwarfReg(X86::R15B, -1, true ); 5876 mapLLVMRegToDwarfReg(X86::R15D, -1, true ); 5877 mapLLVMRegToDwarfReg(X86::R15W, -1, true ); 5878 mapLLVMRegToDwarfReg(X86::RAX, 0, true ); 5879 mapLLVMRegToDwarfReg(X86::RBP, 6, true ); 5880 mapLLVMRegToDwarfReg(X86::RBX, 3, true ); 5881 mapLLVMRegToDwarfReg(X86::RCX, 2, true ); 5882 mapLLVMRegToDwarfReg(X86::RDI, 5, true ); 5883 mapLLVMRegToDwarfReg(X86::RDX, 1, true ); 5884 mapLLVMRegToDwarfReg(X86::RIP, 16, true ); 5885 mapLLVMRegToDwarfReg(X86::RIZ, -1, true ); 5886 mapLLVMRegToDwarfReg(X86::RSI, 4, true ); 5887 mapLLVMRegToDwarfReg(X86::RSP, 7, true ); 5888 mapLLVMRegToDwarfReg(X86::SI, -1, true ); 5889 mapLLVMRegToDwarfReg(X86::SIL, -1, true ); 5890 mapLLVMRegToDwarfReg(X86::SP, -1, true ); 5891 mapLLVMRegToDwarfReg(X86::SPL, -1, true ); 5892 mapLLVMRegToDwarfReg(X86::SS, -1, true ); 5893 mapLLVMRegToDwarfReg(X86::ST0, 33, true ); 5894 mapLLVMRegToDwarfReg(X86::ST1, 34, true ); 5895 mapLLVMRegToDwarfReg(X86::ST2, 35, true ); 5896 mapLLVMRegToDwarfReg(X86::ST3, 36, true ); 5897 mapLLVMRegToDwarfReg(X86::ST4, 37, true ); 5898 mapLLVMRegToDwarfReg(X86::ST5, 38, true ); 5899 mapLLVMRegToDwarfReg(X86::ST6, 39, true ); 5900 mapLLVMRegToDwarfReg(X86::ST7, 40, true ); 5901 mapLLVMRegToDwarfReg(X86::XMM0, 17, true ); 5902 mapLLVMRegToDwarfReg(X86::XMM1, 18, true ); 5903 mapLLVMRegToDwarfReg(X86::XMM2, 19, true ); 5904 mapLLVMRegToDwarfReg(X86::XMM3, 20, true ); 5905 mapLLVMRegToDwarfReg(X86::XMM4, 21, true ); 5906 mapLLVMRegToDwarfReg(X86::XMM5, 22, true ); 5907 mapLLVMRegToDwarfReg(X86::XMM6, 23, true ); 5908 mapLLVMRegToDwarfReg(X86::XMM7, 24, true ); 5909 mapLLVMRegToDwarfReg(X86::XMM8, 25, true ); 5910 mapLLVMRegToDwarfReg(X86::XMM9, 26, true ); 5911 mapLLVMRegToDwarfReg(X86::XMM10, 27, true ); 5912 mapLLVMRegToDwarfReg(X86::XMM11, 28, true ); 5913 mapLLVMRegToDwarfReg(X86::XMM12, 29, true ); 5914 mapLLVMRegToDwarfReg(X86::XMM13, 30, true ); 5915 mapLLVMRegToDwarfReg(X86::XMM14, 31, true ); 5916 mapLLVMRegToDwarfReg(X86::XMM15, 32, true ); 5917 mapLLVMRegToDwarfReg(X86::YMM0, 17, true ); 5918 mapLLVMRegToDwarfReg(X86::YMM1, 18, true ); 5919 mapLLVMRegToDwarfReg(X86::YMM2, 19, true ); 5920 mapLLVMRegToDwarfReg(X86::YMM3, 20, true ); 5921 mapLLVMRegToDwarfReg(X86::YMM4, 21, true ); 5922 mapLLVMRegToDwarfReg(X86::YMM5, 22, true ); 5923 mapLLVMRegToDwarfReg(X86::YMM6, 23, true ); 5924 mapLLVMRegToDwarfReg(X86::YMM7, 24, true ); 5925 mapLLVMRegToDwarfReg(X86::YMM8, 25, true ); 5926 mapLLVMRegToDwarfReg(X86::YMM9, 26, true ); 5927 mapLLVMRegToDwarfReg(X86::YMM10, 27, true ); 5928 mapLLVMRegToDwarfReg(X86::YMM11, 28, true ); 5929 mapLLVMRegToDwarfReg(X86::YMM12, 29, true ); 5930 mapLLVMRegToDwarfReg(X86::YMM13, 30, true ); 5931 mapLLVMRegToDwarfReg(X86::YMM14, 31, true ); 5932 mapLLVMRegToDwarfReg(X86::YMM15, 32, true ); 5933 break; 5934 case 1: 5935 mapLLVMRegToDwarfReg(X86::AH, -1, true ); 5936 mapLLVMRegToDwarfReg(X86::AL, -1, true ); 5937 mapLLVMRegToDwarfReg(X86::AX, -1, true ); 5938 mapLLVMRegToDwarfReg(X86::BH, -1, true ); 5939 mapLLVMRegToDwarfReg(X86::BL, -1, true ); 5940 mapLLVMRegToDwarfReg(X86::BP, -1, true ); 5941 mapLLVMRegToDwarfReg(X86::BPL, -1, true ); 5942 mapLLVMRegToDwarfReg(X86::BX, -1, true ); 5943 mapLLVMRegToDwarfReg(X86::CH, -1, true ); 5944 mapLLVMRegToDwarfReg(X86::CL, -1, true ); 5945 mapLLVMRegToDwarfReg(X86::CR0, -1, true ); 5946 mapLLVMRegToDwarfReg(X86::CR1, -1, true ); 5947 mapLLVMRegToDwarfReg(X86::CR2, -1, true ); 5948 mapLLVMRegToDwarfReg(X86::CR3, -1, true ); 5949 mapLLVMRegToDwarfReg(X86::CR4, -1, true ); 5950 mapLLVMRegToDwarfReg(X86::CR5, -1, true ); 5951 mapLLVMRegToDwarfReg(X86::CR6, -1, true ); 5952 mapLLVMRegToDwarfReg(X86::CR7, -1, true ); 5953 mapLLVMRegToDwarfReg(X86::CR8, -1, true ); 5954 mapLLVMRegToDwarfReg(X86::CR9, -1, true ); 5955 mapLLVMRegToDwarfReg(X86::CR10, -1, true ); 5956 mapLLVMRegToDwarfReg(X86::CR11, -1, true ); 5957 mapLLVMRegToDwarfReg(X86::CR12, -1, true ); 5958 mapLLVMRegToDwarfReg(X86::CR13, -1, true ); 5959 mapLLVMRegToDwarfReg(X86::CR14, -1, true ); 5960 mapLLVMRegToDwarfReg(X86::CR15, -1, true ); 5961 mapLLVMRegToDwarfReg(X86::CS, -1, true ); 5962 mapLLVMRegToDwarfReg(X86::CX, -1, true ); 5963 mapLLVMRegToDwarfReg(X86::DH, -1, true ); 5964 mapLLVMRegToDwarfReg(X86::DI, -1, true ); 5965 mapLLVMRegToDwarfReg(X86::DIL, -1, true ); 5966 mapLLVMRegToDwarfReg(X86::DL, -1, true ); 5967 mapLLVMRegToDwarfReg(X86::DR0, -1, true ); 5968 mapLLVMRegToDwarfReg(X86::DR1, -1, true ); 5969 mapLLVMRegToDwarfReg(X86::DR2, -1, true ); 5970 mapLLVMRegToDwarfReg(X86::DR3, -1, true ); 5971 mapLLVMRegToDwarfReg(X86::DR4, -1, true ); 5972 mapLLVMRegToDwarfReg(X86::DR5, -1, true ); 5973 mapLLVMRegToDwarfReg(X86::DR6, -1, true ); 5974 mapLLVMRegToDwarfReg(X86::DR7, -1, true ); 5975 mapLLVMRegToDwarfReg(X86::DS, -1, true ); 5976 mapLLVMRegToDwarfReg(X86::DX, -1, true ); 5977 mapLLVMRegToDwarfReg(X86::EAX, 0, true ); 5978 mapLLVMRegToDwarfReg(X86::EBP, 4, true ); 5979 mapLLVMRegToDwarfReg(X86::EBX, 3, true ); 5980 mapLLVMRegToDwarfReg(X86::ECX, 1, true ); 5981 mapLLVMRegToDwarfReg(X86::EDI, 7, true ); 5982 mapLLVMRegToDwarfReg(X86::EDX, 2, true ); 5983 mapLLVMRegToDwarfReg(X86::EFLAGS, -1, true ); 5984 mapLLVMRegToDwarfReg(X86::EIP, 8, true ); 5985 mapLLVMRegToDwarfReg(X86::EIZ, -1, true ); 5986 mapLLVMRegToDwarfReg(X86::ES, -1, true ); 5987 mapLLVMRegToDwarfReg(X86::ESI, 6, true ); 5988 mapLLVMRegToDwarfReg(X86::ESP, 5, true ); 5989 mapLLVMRegToDwarfReg(X86::FP0, -1, true ); 5990 mapLLVMRegToDwarfReg(X86::FP1, -1, true ); 5991 mapLLVMRegToDwarfReg(X86::FP2, -1, true ); 5992 mapLLVMRegToDwarfReg(X86::FP3, -1, true ); 5993 mapLLVMRegToDwarfReg(X86::FP4, -1, true ); 5994 mapLLVMRegToDwarfReg(X86::FP5, -1, true ); 5995 mapLLVMRegToDwarfReg(X86::FP6, -1, true ); 5996 mapLLVMRegToDwarfReg(X86::FS, -1, true ); 5997 mapLLVMRegToDwarfReg(X86::GS, -1, true ); 5998 mapLLVMRegToDwarfReg(X86::IP, -1, true ); 5999 mapLLVMRegToDwarfReg(X86::MM0, 29, true ); 6000 mapLLVMRegToDwarfReg(X86::MM1, 30, true ); 6001 mapLLVMRegToDwarfReg(X86::MM2, 31, true ); 6002 mapLLVMRegToDwarfReg(X86::MM3, 32, true ); 6003 mapLLVMRegToDwarfReg(X86::MM4, 33, true ); 6004 mapLLVMRegToDwarfReg(X86::MM5, 34, true ); 6005 mapLLVMRegToDwarfReg(X86::MM6, 35, true ); 6006 mapLLVMRegToDwarfReg(X86::MM7, 36, true ); 6007 mapLLVMRegToDwarfReg(X86::R8, -2, true ); 6008 mapLLVMRegToDwarfReg(X86::R8B, -1, true ); 6009 mapLLVMRegToDwarfReg(X86::R8D, -1, true ); 6010 mapLLVMRegToDwarfReg(X86::R8W, -1, true ); 6011 mapLLVMRegToDwarfReg(X86::R9, -2, true ); 6012 mapLLVMRegToDwarfReg(X86::R9B, -1, true ); 6013 mapLLVMRegToDwarfReg(X86::R9D, -1, true ); 6014 mapLLVMRegToDwarfReg(X86::R9W, -1, true ); 6015 mapLLVMRegToDwarfReg(X86::R10, -2, true ); 6016 mapLLVMRegToDwarfReg(X86::R10B, -1, true ); 6017 mapLLVMRegToDwarfReg(X86::R10D, -1, true ); 6018 mapLLVMRegToDwarfReg(X86::R10W, -1, true ); 6019 mapLLVMRegToDwarfReg(X86::R11, -2, true ); 6020 mapLLVMRegToDwarfReg(X86::R11B, -1, true ); 6021 mapLLVMRegToDwarfReg(X86::R11D, -1, true ); 6022 mapLLVMRegToDwarfReg(X86::R11W, -1, true ); 6023 mapLLVMRegToDwarfReg(X86::R12, -2, true ); 6024 mapLLVMRegToDwarfReg(X86::R12B, -1, true ); 6025 mapLLVMRegToDwarfReg(X86::R12D, -1, true ); 6026 mapLLVMRegToDwarfReg(X86::R12W, -1, true ); 6027 mapLLVMRegToDwarfReg(X86::R13, -2, true ); 6028 mapLLVMRegToDwarfReg(X86::R13B, -1, true ); 6029 mapLLVMRegToDwarfReg(X86::R13D, -1, true ); 6030 mapLLVMRegToDwarfReg(X86::R13W, -1, true ); 6031 mapLLVMRegToDwarfReg(X86::R14, -2, true ); 6032 mapLLVMRegToDwarfReg(X86::R14B, -1, true ); 6033 mapLLVMRegToDwarfReg(X86::R14D, -1, true ); 6034 mapLLVMRegToDwarfReg(X86::R14W, -1, true ); 6035 mapLLVMRegToDwarfReg(X86::R15, -2, true ); 6036 mapLLVMRegToDwarfReg(X86::R15B, -1, true ); 6037 mapLLVMRegToDwarfReg(X86::R15D, -1, true ); 6038 mapLLVMRegToDwarfReg(X86::R15W, -1, true ); 6039 mapLLVMRegToDwarfReg(X86::RAX, -2, true ); 6040 mapLLVMRegToDwarfReg(X86::RBP, -2, true ); 6041 mapLLVMRegToDwarfReg(X86::RBX, -2, true ); 6042 mapLLVMRegToDwarfReg(X86::RCX, -2, true ); 6043 mapLLVMRegToDwarfReg(X86::RDI, -2, true ); 6044 mapLLVMRegToDwarfReg(X86::RDX, -2, true ); 6045 mapLLVMRegToDwarfReg(X86::RIP, -2, true ); 6046 mapLLVMRegToDwarfReg(X86::RIZ, -1, true ); 6047 mapLLVMRegToDwarfReg(X86::RSI, -2, true ); 6048 mapLLVMRegToDwarfReg(X86::RSP, -2, true ); 6049 mapLLVMRegToDwarfReg(X86::SI, -1, true ); 6050 mapLLVMRegToDwarfReg(X86::SIL, -1, true ); 6051 mapLLVMRegToDwarfReg(X86::SP, -1, true ); 6052 mapLLVMRegToDwarfReg(X86::SPL, -1, true ); 6053 mapLLVMRegToDwarfReg(X86::SS, -1, true ); 6054 mapLLVMRegToDwarfReg(X86::ST0, 12, true ); 6055 mapLLVMRegToDwarfReg(X86::ST1, 13, true ); 6056 mapLLVMRegToDwarfReg(X86::ST2, 14, true ); 6057 mapLLVMRegToDwarfReg(X86::ST3, 15, true ); 6058 mapLLVMRegToDwarfReg(X86::ST4, 16, true ); 6059 mapLLVMRegToDwarfReg(X86::ST5, 17, true ); 6060 mapLLVMRegToDwarfReg(X86::ST6, 18, true ); 6061 mapLLVMRegToDwarfReg(X86::ST7, 19, true ); 6062 mapLLVMRegToDwarfReg(X86::XMM0, 21, true ); 6063 mapLLVMRegToDwarfReg(X86::XMM1, 22, true ); 6064 mapLLVMRegToDwarfReg(X86::XMM2, 23, true ); 6065 mapLLVMRegToDwarfReg(X86::XMM3, 24, true ); 6066 mapLLVMRegToDwarfReg(X86::XMM4, 25, true ); 6067 mapLLVMRegToDwarfReg(X86::XMM5, 26, true ); 6068 mapLLVMRegToDwarfReg(X86::XMM6, 27, true ); 6069 mapLLVMRegToDwarfReg(X86::XMM7, 28, true ); 6070 mapLLVMRegToDwarfReg(X86::XMM8, -2, true ); 6071 mapLLVMRegToDwarfReg(X86::XMM9, -2, true ); 6072 mapLLVMRegToDwarfReg(X86::XMM10, -2, true ); 6073 mapLLVMRegToDwarfReg(X86::XMM11, -2, true ); 6074 mapLLVMRegToDwarfReg(X86::XMM12, -2, true ); 6075 mapLLVMRegToDwarfReg(X86::XMM13, -2, true ); 6076 mapLLVMRegToDwarfReg(X86::XMM14, -2, true ); 6077 mapLLVMRegToDwarfReg(X86::XMM15, -2, true ); 6078 mapLLVMRegToDwarfReg(X86::YMM0, 21, true ); 6079 mapLLVMRegToDwarfReg(X86::YMM1, 22, true ); 6080 mapLLVMRegToDwarfReg(X86::YMM2, 23, true ); 6081 mapLLVMRegToDwarfReg(X86::YMM3, 24, true ); 6082 mapLLVMRegToDwarfReg(X86::YMM4, 25, true ); 6083 mapLLVMRegToDwarfReg(X86::YMM5, 26, true ); 6084 mapLLVMRegToDwarfReg(X86::YMM6, 27, true ); 6085 mapLLVMRegToDwarfReg(X86::YMM7, 28, true ); 6086 mapLLVMRegToDwarfReg(X86::YMM8, -2, true ); 6087 mapLLVMRegToDwarfReg(X86::YMM9, -2, true ); 6088 mapLLVMRegToDwarfReg(X86::YMM10, -2, true ); 6089 mapLLVMRegToDwarfReg(X86::YMM11, -2, true ); 6090 mapLLVMRegToDwarfReg(X86::YMM12, -2, true ); 6091 mapLLVMRegToDwarfReg(X86::YMM13, -2, true ); 6092 mapLLVMRegToDwarfReg(X86::YMM14, -2, true ); 6093 mapLLVMRegToDwarfReg(X86::YMM15, -2, true ); 6094 break; 6095 case 2: 6096 mapLLVMRegToDwarfReg(X86::AH, -1, true ); 6097 mapLLVMRegToDwarfReg(X86::AL, -1, true ); 6098 mapLLVMRegToDwarfReg(X86::AX, -1, true ); 6099 mapLLVMRegToDwarfReg(X86::BH, -1, true ); 6100 mapLLVMRegToDwarfReg(X86::BL, -1, true ); 6101 mapLLVMRegToDwarfReg(X86::BP, -1, true ); 6102 mapLLVMRegToDwarfReg(X86::BPL, -1, true ); 6103 mapLLVMRegToDwarfReg(X86::BX, -1, true ); 6104 mapLLVMRegToDwarfReg(X86::CH, -1, true ); 6105 mapLLVMRegToDwarfReg(X86::CL, -1, true ); 6106 mapLLVMRegToDwarfReg(X86::CR0, -1, true ); 6107 mapLLVMRegToDwarfReg(X86::CR1, -1, true ); 6108 mapLLVMRegToDwarfReg(X86::CR2, -1, true ); 6109 mapLLVMRegToDwarfReg(X86::CR3, -1, true ); 6110 mapLLVMRegToDwarfReg(X86::CR4, -1, true ); 6111 mapLLVMRegToDwarfReg(X86::CR5, -1, true ); 6112 mapLLVMRegToDwarfReg(X86::CR6, -1, true ); 6113 mapLLVMRegToDwarfReg(X86::CR7, -1, true ); 6114 mapLLVMRegToDwarfReg(X86::CR8, -1, true ); 6115 mapLLVMRegToDwarfReg(X86::CR9, -1, true ); 6116 mapLLVMRegToDwarfReg(X86::CR10, -1, true ); 6117 mapLLVMRegToDwarfReg(X86::CR11, -1, true ); 6118 mapLLVMRegToDwarfReg(X86::CR12, -1, true ); 6119 mapLLVMRegToDwarfReg(X86::CR13, -1, true ); 6120 mapLLVMRegToDwarfReg(X86::CR14, -1, true ); 6121 mapLLVMRegToDwarfReg(X86::CR15, -1, true ); 6122 mapLLVMRegToDwarfReg(X86::CS, -1, true ); 6123 mapLLVMRegToDwarfReg(X86::CX, -1, true ); 6124 mapLLVMRegToDwarfReg(X86::DH, -1, true ); 6125 mapLLVMRegToDwarfReg(X86::DI, -1, true ); 6126 mapLLVMRegToDwarfReg(X86::DIL, -1, true ); 6127 mapLLVMRegToDwarfReg(X86::DL, -1, true ); 6128 mapLLVMRegToDwarfReg(X86::DR0, -1, true ); 6129 mapLLVMRegToDwarfReg(X86::DR1, -1, true ); 6130 mapLLVMRegToDwarfReg(X86::DR2, -1, true ); 6131 mapLLVMRegToDwarfReg(X86::DR3, -1, true ); 6132 mapLLVMRegToDwarfReg(X86::DR4, -1, true ); 6133 mapLLVMRegToDwarfReg(X86::DR5, -1, true ); 6134 mapLLVMRegToDwarfReg(X86::DR6, -1, true ); 6135 mapLLVMRegToDwarfReg(X86::DR7, -1, true ); 6136 mapLLVMRegToDwarfReg(X86::DS, -1, true ); 6137 mapLLVMRegToDwarfReg(X86::DX, -1, true ); 6138 mapLLVMRegToDwarfReg(X86::EAX, 0, true ); 6139 mapLLVMRegToDwarfReg(X86::EBP, 5, true ); 6140 mapLLVMRegToDwarfReg(X86::EBX, 3, true ); 6141 mapLLVMRegToDwarfReg(X86::ECX, 1, true ); 6142 mapLLVMRegToDwarfReg(X86::EDI, 7, true ); 6143 mapLLVMRegToDwarfReg(X86::EDX, 2, true ); 6144 mapLLVMRegToDwarfReg(X86::EFLAGS, -1, true ); 6145 mapLLVMRegToDwarfReg(X86::EIP, 8, true ); 6146 mapLLVMRegToDwarfReg(X86::EIZ, -1, true ); 6147 mapLLVMRegToDwarfReg(X86::ES, -1, true ); 6148 mapLLVMRegToDwarfReg(X86::ESI, 6, true ); 6149 mapLLVMRegToDwarfReg(X86::ESP, 4, true ); 6150 mapLLVMRegToDwarfReg(X86::FP0, -1, true ); 6151 mapLLVMRegToDwarfReg(X86::FP1, -1, true ); 6152 mapLLVMRegToDwarfReg(X86::FP2, -1, true ); 6153 mapLLVMRegToDwarfReg(X86::FP3, -1, true ); 6154 mapLLVMRegToDwarfReg(X86::FP4, -1, true ); 6155 mapLLVMRegToDwarfReg(X86::FP5, -1, true ); 6156 mapLLVMRegToDwarfReg(X86::FP6, -1, true ); 6157 mapLLVMRegToDwarfReg(X86::FS, -1, true ); 6158 mapLLVMRegToDwarfReg(X86::GS, -1, true ); 6159 mapLLVMRegToDwarfReg(X86::IP, -1, true ); 6160 mapLLVMRegToDwarfReg(X86::MM0, 29, true ); 6161 mapLLVMRegToDwarfReg(X86::MM1, 30, true ); 6162 mapLLVMRegToDwarfReg(X86::MM2, 31, true ); 6163 mapLLVMRegToDwarfReg(X86::MM3, 32, true ); 6164 mapLLVMRegToDwarfReg(X86::MM4, 33, true ); 6165 mapLLVMRegToDwarfReg(X86::MM5, 34, true ); 6166 mapLLVMRegToDwarfReg(X86::MM6, 35, true ); 6167 mapLLVMRegToDwarfReg(X86::MM7, 36, true ); 6168 mapLLVMRegToDwarfReg(X86::R8, -2, true ); 6169 mapLLVMRegToDwarfReg(X86::R8B, -1, true ); 6170 mapLLVMRegToDwarfReg(X86::R8D, -1, true ); 6171 mapLLVMRegToDwarfReg(X86::R8W, -1, true ); 6172 mapLLVMRegToDwarfReg(X86::R9, -2, true ); 6173 mapLLVMRegToDwarfReg(X86::R9B, -1, true ); 6174 mapLLVMRegToDwarfReg(X86::R9D, -1, true ); 6175 mapLLVMRegToDwarfReg(X86::R9W, -1, true ); 6176 mapLLVMRegToDwarfReg(X86::R10, -2, true ); 6177 mapLLVMRegToDwarfReg(X86::R10B, -1, true ); 6178 mapLLVMRegToDwarfReg(X86::R10D, -1, true ); 6179 mapLLVMRegToDwarfReg(X86::R10W, -1, true ); 6180 mapLLVMRegToDwarfReg(X86::R11, -2, true ); 6181 mapLLVMRegToDwarfReg(X86::R11B, -1, true ); 6182 mapLLVMRegToDwarfReg(X86::R11D, -1, true ); 6183 mapLLVMRegToDwarfReg(X86::R11W, -1, true ); 6184 mapLLVMRegToDwarfReg(X86::R12, -2, true ); 6185 mapLLVMRegToDwarfReg(X86::R12B, -1, true ); 6186 mapLLVMRegToDwarfReg(X86::R12D, -1, true ); 6187 mapLLVMRegToDwarfReg(X86::R12W, -1, true ); 6188 mapLLVMRegToDwarfReg(X86::R13, -2, true ); 6189 mapLLVMRegToDwarfReg(X86::R13B, -1, true ); 6190 mapLLVMRegToDwarfReg(X86::R13D, -1, true ); 6191 mapLLVMRegToDwarfReg(X86::R13W, -1, true ); 6192 mapLLVMRegToDwarfReg(X86::R14, -2, true ); 6193 mapLLVMRegToDwarfReg(X86::R14B, -1, true ); 6194 mapLLVMRegToDwarfReg(X86::R14D, -1, true ); 6195 mapLLVMRegToDwarfReg(X86::R14W, -1, true ); 6196 mapLLVMRegToDwarfReg(X86::R15, -2, true ); 6197 mapLLVMRegToDwarfReg(X86::R15B, -1, true ); 6198 mapLLVMRegToDwarfReg(X86::R15D, -1, true ); 6199 mapLLVMRegToDwarfReg(X86::R15W, -1, true ); 6200 mapLLVMRegToDwarfReg(X86::RAX, -2, true ); 6201 mapLLVMRegToDwarfReg(X86::RBP, -2, true ); 6202 mapLLVMRegToDwarfReg(X86::RBX, -2, true ); 6203 mapLLVMRegToDwarfReg(X86::RCX, -2, true ); 6204 mapLLVMRegToDwarfReg(X86::RDI, -2, true ); 6205 mapLLVMRegToDwarfReg(X86::RDX, -2, true ); 6206 mapLLVMRegToDwarfReg(X86::RIP, -2, true ); 6207 mapLLVMRegToDwarfReg(X86::RIZ, -1, true ); 6208 mapLLVMRegToDwarfReg(X86::RSI, -2, true ); 6209 mapLLVMRegToDwarfReg(X86::RSP, -2, true ); 6210 mapLLVMRegToDwarfReg(X86::SI, -1, true ); 6211 mapLLVMRegToDwarfReg(X86::SIL, -1, true ); 6212 mapLLVMRegToDwarfReg(X86::SP, -1, true ); 6213 mapLLVMRegToDwarfReg(X86::SPL, -1, true ); 6214 mapLLVMRegToDwarfReg(X86::SS, -1, true ); 6215 mapLLVMRegToDwarfReg(X86::ST0, 11, true ); 6216 mapLLVMRegToDwarfReg(X86::ST1, 12, true ); 6217 mapLLVMRegToDwarfReg(X86::ST2, 13, true ); 6218 mapLLVMRegToDwarfReg(X86::ST3, 14, true ); 6219 mapLLVMRegToDwarfReg(X86::ST4, 15, true ); 6220 mapLLVMRegToDwarfReg(X86::ST5, 16, true ); 6221 mapLLVMRegToDwarfReg(X86::ST6, 17, true ); 6222 mapLLVMRegToDwarfReg(X86::ST7, 18, true ); 6223 mapLLVMRegToDwarfReg(X86::XMM0, 21, true ); 6224 mapLLVMRegToDwarfReg(X86::XMM1, 22, true ); 6225 mapLLVMRegToDwarfReg(X86::XMM2, 23, true ); 6226 mapLLVMRegToDwarfReg(X86::XMM3, 24, true ); 6227 mapLLVMRegToDwarfReg(X86::XMM4, 25, true ); 6228 mapLLVMRegToDwarfReg(X86::XMM5, 26, true ); 6229 mapLLVMRegToDwarfReg(X86::XMM6, 27, true ); 6230 mapLLVMRegToDwarfReg(X86::XMM7, 28, true ); 6231 mapLLVMRegToDwarfReg(X86::XMM8, -2, true ); 6232 mapLLVMRegToDwarfReg(X86::XMM9, -2, true ); 6233 mapLLVMRegToDwarfReg(X86::XMM10, -2, true ); 6234 mapLLVMRegToDwarfReg(X86::XMM11, -2, true ); 6235 mapLLVMRegToDwarfReg(X86::XMM12, -2, true ); 6236 mapLLVMRegToDwarfReg(X86::XMM13, -2, true ); 6237 mapLLVMRegToDwarfReg(X86::XMM14, -2, true ); 6238 mapLLVMRegToDwarfReg(X86::XMM15, -2, true ); 6239 mapLLVMRegToDwarfReg(X86::YMM0, 21, true ); 6240 mapLLVMRegToDwarfReg(X86::YMM1, 22, true ); 6241 mapLLVMRegToDwarfReg(X86::YMM2, 23, true ); 6242 mapLLVMRegToDwarfReg(X86::YMM3, 24, true ); 6243 mapLLVMRegToDwarfReg(X86::YMM4, 25, true ); 6244 mapLLVMRegToDwarfReg(X86::YMM5, 26, true ); 6245 mapLLVMRegToDwarfReg(X86::YMM6, 27, true ); 6246 mapLLVMRegToDwarfReg(X86::YMM7, 28, true ); 6247 mapLLVMRegToDwarfReg(X86::YMM8, -2, true ); 6248 mapLLVMRegToDwarfReg(X86::YMM9, -2, true ); 6249 mapLLVMRegToDwarfReg(X86::YMM10, -2, true ); 6250 mapLLVMRegToDwarfReg(X86::YMM11, -2, true ); 6251 mapLLVMRegToDwarfReg(X86::YMM12, -2, true ); 6252 mapLLVMRegToDwarfReg(X86::YMM13, -2, true ); 6253 mapLLVMRegToDwarfReg(X86::YMM14, -2, true ); 6254 mapLLVMRegToDwarfReg(X86::YMM15, -2, true ); 6255 break; 6256 } 6257} 6258 6259} // End llvm namespace 6260#endif // GET_REGINFO_TARGET_DESC 6261 6262