1 /*
2
3 Copyright (c) 2009, 2010, 2011 STMicroelectronics
4 Written by Christophe Lyon
5
6 Permission is hereby granted, free of charge, to any person obtaining a copy
7 of this software and associated documentation files (the "Software"), to deal
8 in the Software without restriction, including without limitation the rights
9 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 copies of the Software, and to permit persons to whom the Software is
11 furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 THE SOFTWARE.
23
24 */
25
26 #if defined(__arm__) || defined(__aarch64__)
27 #include <arm_neon.h>
28 #else
29 #include "stm-arm-neon.h"
30 #endif
31
32 #include "stm-arm-neon-ref.h"
33
34 #ifndef INSN_NAME
35 #define INSN_NAME vmla
36 #define TEST_MSG "VMLA"
37 #endif
38
39
40 #define FNNAME1(NAME) void exec_ ## NAME (void)
41 #define FNNAME(NAME) FNNAME1(NAME)
42
FNNAME(INSN_NAME)43 FNNAME (INSN_NAME)
44 {
45 #define DECL_VMLX(T, W, N) \
46 DECL_VARIABLE(vector1, T, W, N); \
47 DECL_VARIABLE(vector2, T, W, N); \
48 DECL_VARIABLE(vector3, T, W, N); \
49 DECL_VARIABLE(vector_res, T, W, N)
50
51 /* vector_res = OP(vector, vector3, vector4),
52 then store the result. */
53 #define TEST_VMLX1(INSN, Q, T1, T2, W, N) \
54 VECT_VAR(vector_res, T1, W, N) = \
55 INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
56 VECT_VAR(vector2, T1, W, N), \
57 VECT_VAR(vector3, T1, W, N)); \
58 vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
59 VECT_VAR(vector_res, T1, W, N))
60
61 #define TEST_VMLX(INSN, Q, T1, T2, W, N) \
62 TEST_VMLX1(INSN, Q, T1, T2, W, N)
63
64 /* With ARM RVCT, we need to declare variables before any executable
65 statement */
66 DECL_VMLX(int, 8, 8);
67 DECL_VMLX(int, 16, 4);
68 DECL_VMLX(int, 32, 2);
69 DECL_VMLX(uint, 8, 8);
70 DECL_VMLX(uint, 16, 4);
71 DECL_VMLX(uint, 32, 2);
72 DECL_VMLX(float, 32, 2);
73 DECL_VMLX(int, 8, 16);
74 DECL_VMLX(int, 16, 8);
75 DECL_VMLX(int, 32, 4);
76 DECL_VMLX(uint, 8, 16);
77 DECL_VMLX(uint, 16, 8);
78 DECL_VMLX(uint, 32, 4);
79 DECL_VMLX(float, 32, 4);
80
81 clean_results ();
82
83 VLOAD(vector1, buffer, , int, s, 8, 8);
84 VLOAD(vector1, buffer, , int, s, 16, 4);
85 VLOAD(vector1, buffer, , int, s, 32, 2);
86 VLOAD(vector1, buffer, , uint, u, 8, 8);
87 VLOAD(vector1, buffer, , uint, u, 16, 4);
88 VLOAD(vector1, buffer, , uint, u, 32, 2);
89 VLOAD(vector1, buffer, , float, f, 32, 2);
90 VLOAD(vector1, buffer, q, int, s, 8, 16);
91 VLOAD(vector1, buffer, q, int, s, 16, 8);
92 VLOAD(vector1, buffer, q, int, s, 32, 4);
93 VLOAD(vector1, buffer, q, uint, u, 8, 16);
94 VLOAD(vector1, buffer, q, uint, u, 16, 8);
95 VLOAD(vector1, buffer, q, uint, u, 32, 4);
96 VLOAD(vector1, buffer, q, float, f, 32, 4);
97
98 VDUP(vector2, , int, s, 8, 8, 0x11);
99 VDUP(vector2, , int, s, 16, 4, 0x22);
100 VDUP(vector2, , int, s, 32, 2, 0x33);
101 VDUP(vector2, , uint, u, 8, 8, 0x44);
102 VDUP(vector2, , uint, u, 16, 4, 0x55);
103 VDUP(vector2, , uint, u, 32, 2, 0x66);
104 VDUP(vector2, , float, f, 32, 2, 33.1f);
105 VDUP(vector2, q, int, s, 8, 16, 0x77);
106 VDUP(vector2, q, int, s, 16, 8, 0x88);
107 VDUP(vector2, q, int, s, 32, 4, 0x99);
108 VDUP(vector2, q, uint, u, 8, 16, 0xAA);
109 VDUP(vector2, q, uint, u, 16, 8, 0xBB);
110 VDUP(vector2, q, uint, u, 32, 4, 0xCC);
111 VDUP(vector2, q, float, f, 32, 4, 99.2f);
112
113 VDUP(vector3, , int, s, 8, 8, 0xFF);
114 VDUP(vector3, , int, s, 16, 4, 0xEE);
115 VDUP(vector3, , int, s, 32, 2, 0xDD);
116 VDUP(vector3, , uint, u, 8, 8, 0xCC);
117 VDUP(vector3, , uint, u, 16, 4, 0xBB);
118 VDUP(vector3, , uint, u, 32, 2, 0xAA);
119 VDUP(vector3, , float, f, 32, 2, 10.23f);
120 VDUP(vector3, q, int, s, 8, 16, 0x99);
121 VDUP(vector3, q, int, s, 16, 8, 0x88);
122 VDUP(vector3, q, int, s, 32, 4, 0x77);
123 VDUP(vector3, q, uint, u, 8, 16, 0x66);
124 VDUP(vector3, q, uint, u, 16, 8, 0x55);
125 VDUP(vector3, q, uint, u, 32, 4, 0x44);
126 VDUP(vector3, q, float, f, 32, 4, 77.8f);
127
128 TEST_VMLX(INSN_NAME, , int, s, 8, 8);
129 TEST_VMLX(INSN_NAME, , int, s, 16, 4);
130 TEST_VMLX(INSN_NAME, , int, s, 32, 2);
131 TEST_VMLX(INSN_NAME, , uint, u, 8, 8);
132 TEST_VMLX(INSN_NAME, , uint, u, 16, 4);
133 TEST_VMLX(INSN_NAME, , uint, u, 32, 2);
134 TEST_VMLX(INSN_NAME, , float, f, 32, 2);
135 TEST_VMLX(INSN_NAME, q, int, s, 8, 16);
136 TEST_VMLX(INSN_NAME, q, int, s, 16, 8);
137 TEST_VMLX(INSN_NAME, q, int, s, 32, 4);
138 TEST_VMLX(INSN_NAME, q, uint, u, 8, 16);
139 TEST_VMLX(INSN_NAME, q, uint, u, 16, 8);
140 TEST_VMLX(INSN_NAME, q, uint, u, 32, 4);
141 TEST_VMLX(INSN_NAME, q, float, f, 32, 4);
142
143 dump_results_hex (TEST_MSG);
144 }
145