1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27// Test description for instructions of the following form: 28// MNEMONIC{<c>}.W <Rn>, #<const> 29 30{ 31 "mnemonics" : [ 32 "Cmn", // CMN{<c>}{<q>} <Rn>, #<const> ; T1 33 "Cmp", // CMP{<c>}{<q>} <Rn>, #<const> ; T2 34 "Mov", // MOV{<c>}{<q>} <Rd>, #<const> ; T2 35 "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; T2 36 "Mvn", // MVN{<c>}{<q>} <Rd>, #<const> ; T1 37 "Mvns", // MVNS{<c>}{<q>} <Rd>, #<const> ; T1 38 "Teq", // TEQ{<c>}{<q>} <Rn>, #<const> ; T1 39 "Tst" // TST{<c>}{<q>} <Rn>, #<const> ; T1 40 ], 41 "description" : { 42 "operands": [ 43 { 44 "name": "cond", 45 "type": "Condition" 46 }, 47 { 48 "name": "rd", 49 "type": "AllRegistersButPC" 50 }, 51 { 52 "name": "op", 53 "wrapper": "Operand", 54 "operands": [ 55 { 56 "name": "immediate", 57 "type": "T32ModifiedImmediate" 58 } 59 ] 60 } 61 ], 62 "inputs": [ 63 { 64 "name": "apsr", 65 "type": "NZCV" 66 }, 67 { 68 "name": "rd", 69 "type": "Register" 70 } 71 ] 72 }, 73 "test-files": [ 74 { 75 "type": "assembler", 76 "test-cases": [ 77 { 78 "name": "Operands", 79 "operands": [ 80 "cond", "rd", "immediate" 81 ], 82 "operand-filter": "cond == 'al'" 83 } 84 ] 85 }, 86 { 87 "type": "simulator", 88 "test-cases": [ 89 { 90 "name": "Condition", 91 "operands": [ 92 "cond" 93 ], 94 "inputs": [ 95 "apsr" 96 ] 97 }, 98 { 99 "name": "ModifiedImmediate", 100 "operands": [ 101 "immediate" 102 ], 103 "inputs": [ 104 "rd" 105 ] 106 } 107 ] 108 } 109 ] 110} 111