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1// Copyright 2016, VIXL authors
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are met:
6//
7//   * Redistributions of source code must retain the above copyright notice,
8//     this list of conditions and the following disclaimer.
9//   * Redistributions in binary form must reproduce the above copyright notice,
10//     this list of conditions and the following disclaimer in the documentation
11//     and/or other materials provided with the distribution.
12//   * Neither the name of ARM Limited nor the names of its contributors may be
13//     used to endorse or promote products derived from this software without
14//     specific prior written permission.
15//
16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27// Test description for instructions of the following form:
28//   MNEMONIC{<c>}.W <Rn>, <Rm>, LSL|ROR #<amount>
29//   MNEMONIC{<c>}.N <Rn>, <Rm>, LSL|ROR #<amount> ; Special case for MOV and MOVS
30
31{
32  "mnemonics" : [
33    "Cmn",  // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T2
34    "Cmp",  // CMP{<c>}{<q>} <Rn>, <Rm>, <shift> #<amount> ; T3
35    "Mov",  // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
36            // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
37    "Movs", // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
38            // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
39    "Mvn",  // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
40    "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
41    "Teq",  // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T1
42    "Tst"   // TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T2
43  ],
44  "description" : {
45    "operands": [
46      {
47        "name": "cond",
48        "type": "Condition"
49      },
50      {
51        "name": "rd",
52        "type": "AllRegistersButPC"
53      },
54      {
55        "name": "op",
56        "wrapper": "Operand",
57        "operands": [
58          {
59            "name": "rn",
60            "type": "AllRegistersButPC"
61          },
62          {
63            "name": "shift",
64            "type": "Shift1To32"
65          },
66          {
67            "name": "amount",
68            "type": "ShiftAmount1To32"
69          }
70        ]
71      }
72    ],
73    "inputs": [
74      {
75        "name": "apsr",
76        "type": "NZCV"
77      },
78      {
79        "name": "rd",
80        "type": "Register"
81      },
82      {
83        "name": "rn",
84        "type": "Register"
85      }
86    ]
87  },
88  "test-files": [
89    {
90      "type": "assembler",
91      "test-cases": [
92        {
93          "name": "Unconditional",
94          "operands": [
95            "cond", "rd", "rn", "shift", "amount"
96          ],
97          "operand-filter": "cond == 'al'",
98          "operand-limit": 500
99        }
100      ]
101    },
102    // Test instructions in an IT block with no restrictions on registers.
103    {
104      "name": "in-it-block",
105      "type": "assembler",
106      "mnemonics" : [
107        "Mov" // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
108      ],
109      "test-cases": [
110        {
111          "name": "InITBlock",
112          "operands": [
113            "cond", "rd", "rn", "shift", "amount"
114          ],
115          // Generate an extra IT instruction.
116          "in-it-block": "{cond}",
117          "operand-filter": "cond != 'al' and register_is_low(rd) and register_is_low(rn)",
118          "operand-limit": 500
119        }
120      ]
121    },
122    {
123      "type": "simulator",
124      "test-cases": [
125        {
126          "name": "Condition",
127          "operands": [
128            "cond"
129          ],
130          "inputs": [
131            "apsr"
132          ]
133        },
134        // Test combinations of registers values with rd == rn.
135        {
136          "name": "RdIsRn",
137          "operands": [
138            "rd", "rn"
139          ],
140          "inputs": [
141            "rd", "rn"
142          ],
143          "operand-filter": "rd == rn",
144          "input-filter": "rd == rn"
145        },
146        // Test combinations of registers values.
147        {
148          "name": "RdIsNotRn",
149          "operands": [
150            "rd", "rn"
151          ],
152          "inputs": [
153            "rd", "rn"
154          ],
155          "operand-filter": "rd != rn",
156          "operand-limit": 10,
157          "input-limit": 200
158        },
159        // Test combinations of shift types and register values.
160        {
161          "name": "ShiftTypes",
162          "operands": [
163            "rd", "rn", "shift", "amount"
164          ],
165          "inputs": [
166            "rn"
167          ],
168          // Specify exactly what registers to use in this test to make sure
169          // that they are different. It makes the execution trace more
170          // understandable.
171          "operand-filter": "rd == 'r0' and rn == 'r1'"
172        }
173      ]
174    }
175  ]
176}
177