1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27// Test description for instructions of the following forms: 28// MNEMONIC{<c>}{<q>} <Rd>, <Rm> 29// MNEMONIC{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } 30// MNEMONIC{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } 31// 32// Note that this test only covers the cases where the optional shift 33// operand is not provided. The shift operands are tested in 34// "cond-rd-operand-rn-shift-amount-*-t32.json". 35 36{ 37 "mnemonics" : [ 38 "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm> ; T1 39 // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T2 40 "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm> ; T1 41 // CMP{<c>}{<q>} <Rn>, <Rm> ; T2 42 "Mov", // MOV{<c>}{<q>} <Rd>, <Rm> ; T1 43 // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2 44 // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3 45 "Movs", // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2 46 // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3 47 "Mvn", // MVN<c>{<q>} <Rd>, <Rm> ; T1 48 // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2 49 "Mvns", // MVNS{<q>} <Rd>, <Rm> ; T1 50 // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2 51 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T1 52 "Tst", // TST{<c>}{<q>} <Rn>, <Rm> ; T1 53 54 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1 55 // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 56 "Sxtb16", // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1 57 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1 58 // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 59 "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1 60 // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 61 "Uxtb16", // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1 62 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1 63 // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 64 ], 65 "description" : { 66 "operands": [ 67 { 68 "name": "cond", 69 "type": "Condition" 70 }, 71 { 72 "name": "rd", 73 "type": "AllRegistersButPC" 74 }, 75 { 76 "name": "op", 77 "wrapper": "Operand", 78 "operands": [ 79 { 80 "name": "rn", 81 "type": "AllRegistersButPC" 82 } 83 ] 84 } 85 ], 86 "inputs": [ 87 { 88 "name": "apsr", 89 "type": "NZCV" 90 }, 91 { 92 "name": "rd", 93 "type": "Register" 94 }, 95 { 96 "name": "rn", 97 "type": "Register" 98 } 99 ] 100 }, 101 "test-files": [ 102 { 103 "type": "assembler", 104 "test-cases": [ 105 { 106 "name": "Unconditional", 107 "operands": [ 108 "cond", "rd", "rn" 109 ], 110 "operand-filter": "cond == 'al'" 111 } 112 ] 113 }, 114 // Test instructions in an IT block with no restrictions on registers. 115 { 116 "name": "in-it-block", 117 "type": "assembler", 118 "mnemonics" : [ 119 "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm> ; T1 120 "Mov" // MOV{<c>}{<q>} <Rd>, <Rm> ; T1 121 ], 122 "test-cases": [ 123 { 124 "name": "InITBlock", 125 "operands": [ 126 "cond", "rd", "rn" 127 ], 128 // Generate an extra IT instruction. 129 "in-it-block": "{cond}", 130 "operand-filter": "cond != 'al'" 131 } 132 ] 133 }, 134 // Test instructions in an IT block where registers have to be from r0 to r7. 135 { 136 "name": "low-registers-in-it-block", 137 "type": "assembler", 138 "mnemonics" : [ 139 "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm> ; T1 140 "Tst" // TST{<c>}{<q>} <Rn>, <Rm> ; T1 141 ], 142 "test-cases": [ 143 { 144 "name": "InITBlock", 145 "operands": [ 146 "cond", "rd", "rn" 147 ], 148 // Generate an extra IT instruction. 149 "in-it-block": "{cond}", 150 "operand-filter": "cond != 'al' and register_is_low(rd) and register_is_low(rn)" 151 } 152 ] 153 }, 154 // Special case for MVN in an IT block, both register operands 155 // need to be identical as well as from r0 to r7. 156 { 157 "name": "identical-low-registers-in-it-block", 158 "type": "assembler", 159 "mnemonics" : [ 160 "Mvn" // MVN<c>{<q>} <Rd>, <Rm> ; T1 161 ], 162 "test-cases": [ 163 { 164 "name": "InITBlock", 165 "operands": [ 166 "cond", "rd", "rn" 167 ], 168 // Generate an extra IT instruction. 169 "in-it-block": "{cond}", 170 "operand-filter": "cond != 'al' and rd == rn and register_is_low(rd)" 171 } 172 ] 173 }, 174 { 175 "type": "simulator", 176 "test-cases": [ 177 { 178 "name": "Condition", 179 "operands": [ 180 "cond" 181 ], 182 "inputs": [ 183 "apsr" 184 ] 185 }, 186 // Test combinations of registers values with rd == rn. 187 { 188 "name": "RdIsRn", 189 "operands": [ 190 "rd", "rn" 191 ], 192 "inputs": [ 193 "rd", "rn" 194 ], 195 "operand-filter": "rd == rn", 196 "input-filter": "rd == rn" 197 }, 198 // Test combinations of registers values. 199 { 200 "name": "RdIsNotRn", 201 "operands": [ 202 "rd", "rn" 203 ], 204 "inputs": [ 205 "rd", "rn" 206 ], 207 "operand-filter": "rd != rn", 208 "operand-limit": 10, 209 "input-limit": 200 210 } 211 ] 212 } 213 ] 214} 215