1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27{ 28 "mnemonics": [ 29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 32 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 33 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 34 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 35 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 36 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 37 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 38 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 39 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 40 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 41 "Rsb", // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 42 "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 43 "Rsc", // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 44 "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 45 "Sbc", // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 46 "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 47 "Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 48 "Subs" // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1 49 ], 50 "description": { 51 "operands": [ 52 { 53 "name": "cond", 54 "type": "Condition" 55 }, 56 { 57 "name": "rd", 58 "type": "AllRegistersButPC" 59 }, 60 { 61 "name": "rn", 62 "type": "AllRegistersButPC" 63 }, 64 { 65 "name": "op", 66 "wrapper": "Operand", 67 "operands": [ 68 { 69 "name": "rm", 70 "type": "AllRegistersButPC" 71 }, 72 { 73 "name": "shift", 74 "type": "Shift" 75 }, 76 { 77 "name": "rs", 78 "type": "AllRegistersButPC" 79 } 80 ] 81 } 82 ], 83 "inputs": [ 84 { 85 "name": "apsr", 86 "type": "NZCV" 87 }, 88 { 89 "name": "rd", 90 "type": "Register" 91 }, 92 { 93 "name": "rn", 94 "type": "Register" 95 }, 96 { 97 "name": "rm", 98 "type": "Register" 99 }, 100 { 101 "name": "rs", 102 "type": "RegisterShift" 103 } 104 ] 105 }, 106 "test-files": [ 107 { 108 "type": "assembler", 109 "test-cases": [ 110 { 111 "name": "Operands", 112 "operands": [ 113 "cond", "rd", "rn", "rm", "shift", "rs" 114 ], 115 "operand-limit": 1000 116 } 117 ] 118 }, 119 { 120 "type": "simulator", 121 "test-cases": [ 122 { 123 "name": "Condition", 124 "operands": [ 125 "cond" 126 ], 127 "inputs": [ 128 "apsr" 129 ] 130 }, 131 // Test combinations of registers values with rd == rn. 132 { 133 "name": "RdIsRn", 134 "operands": [ 135 "rd", "rn", "rm" 136 ], 137 "inputs": [ 138 "rd", "rn", "rm" 139 ], 140 "operand-filter": "rd == rn and rn != rm", 141 "operand-limit": 10, 142 "input-filter": "rd == rn", 143 "input-limit": 200 144 }, 145 // Test combinations of registers values with rd == rm. 146 { 147 "name": "RdIsRm", 148 "operands": [ 149 "rd", "rn", "rm" 150 ], 151 "inputs": [ 152 "rd", "rn", "rm" 153 ], 154 "operand-filter": "rd == rm and rn != rm", 155 "operand-limit": 10, 156 "input-filter": "rd == rm", 157 "input-limit": 200 158 }, 159 // Test combinations of registers values. 160 { 161 "name": "RdIsNotRnIsNotRm", 162 "operands": [ 163 "rd", "rn", "rm" 164 ], 165 "inputs": [ 166 "rd", "rn", "rm" 167 ], 168 "operand-filter": "rd != rn != rm", 169 "operand-limit": 10, 170 "input-limit": 200 171 }, 172 // Test combinations of shift types and register values. 173 { 174 "name": "ShiftTypes", 175 "operands": [ 176 "rm", "shift", "rs" 177 ], 178 "inputs": [ 179 "rm", "rs" 180 ], 181 "operand-filter": "rm == 'r1' and rs == 'r2'" 182 } 183 ] 184 } 185 ] 186} 187