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1// Copyright 2016, VIXL authors
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are met:
6//
7//   * Redistributions of source code must retain the above copyright notice,
8//     this list of conditions and the following disclaimer.
9//   * Redistributions in binary form must reproduce the above copyright notice,
10//     this list of conditions and the following disclaimer in the documentation
11//     and/or other materials provided with the distribution.
12//   * Neither the name of ARM Limited nor the names of its contributors may be
13//     used to endorse or promote products derived from this software without
14//     specific prior written permission.
15//
16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27// Test description for instructions of the following form:
28//   MNEMONIC{<c>}.N <Rdn>, #<imm8>
29
30{
31  "mnemonics" : [
32    "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1
33    "Mov", // MOV<c>{<q>} <Rd>, #<imm8> ; T1
34    "Movs" // MOVS{<q>} <Rd>, #<imm8> ; T1
35  ],
36  "description" : {
37    "operands": [
38      {
39        "name": "cond",
40        "type": "Condition"
41      },
42      {
43        "name": "rd",
44        "type": "LowRegisters"
45      },
46      {
47        "name": "op",
48        "wrapper": "Operand",
49        "operands": [
50          {
51            "name": "immediate",
52            "type": "OffsetLowerThan256"
53          }
54        ]
55      }
56    ],
57    "inputs": [
58      {
59        "name": "apsr",
60        "type": "NZCV"
61      },
62      {
63        "name": "rd",
64        "type": "Register"
65      }
66    ]
67  },
68  "test-files": [
69    {
70      "type": "assembler",
71      "test-cases": [
72        {
73          "name": "Unconditional",
74          "operands": [
75            "cond", "rd", "immediate"
76          ],
77          "operand-filter": "cond == 'al'"
78        }
79      ]
80    },
81    {
82      "name": "in-it-block",
83      "type": "assembler",
84      "mnemonics" : [
85        "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1
86        "Mov"  // MOV<c>{<q>} <Rd>, #<imm8> ; T1
87      ],
88      "test-cases": [
89        {
90          "name": "InITBlock",
91          "operands": [
92            "cond", "rd", "immediate"
93          ],
94          // Generate an extra IT instruction.
95          "in-it-block": "{cond}",
96          "operand-filter": "cond != 'al'",
97          "operand-limit": 1000
98        }
99      ]
100    },
101    {
102      "type": "simulator",
103      "test-cases": [
104        {
105          "name": "Condition",
106          "operands": [
107            "cond"
108          ],
109          "inputs": [
110            "apsr"
111          ]
112        },
113        {
114          "name": "ModifiedImmediate",
115          "operands": [
116            "immediate"
117          ],
118          "inputs": [
119            "rd"
120          ]
121        }
122      ]
123    }
124  ]
125}
126