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1// Copyright 2016, VIXL authors
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are met:
6//
7//   * Redistributions of source code must retain the above copyright notice,
8//     this list of conditions and the following disclaimer.
9//   * Redistributions in binary form must reproduce the above copyright notice,
10//     this list of conditions and the following disclaimer in the documentation
11//     and/or other materials provided with the distribution.
12//   * Neither the name of ARM Limited nor the names of its contributors may be
13//     used to endorse or promote products derived from this software without
14//     specific prior written permission.
15//
16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27{
28  "mnemonics" : [
29    "Crc32b",  // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; A1
30    "Crc32cb", // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; A1
31    "Crc32ch", // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; A1
32    "Crc32cw", // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; A1
33    "Crc32h",  // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; A1
34    "Crc32w"   // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; A1
35  ],
36  "description" : {
37    "operands": [
38      {
39        "name": "rd",
40        "type": "AllRegistersButPC"
41      },
42      {
43        "name": "rn",
44        "type": "AllRegistersButPC"
45      },
46      {
47        "name": "rm",
48        "type": "AllRegistersButPC"
49      }
50    ],
51    "inputs": [
52      {
53        "name": "rd",
54        "type": "Register"
55      },
56      {
57        "name": "rn",
58        "type": "Register"
59      },
60      {
61        "name": "rm",
62        "type": "Register"
63      }
64    ]
65  },
66  "test-files": [
67    {
68      "type": "assembler",
69      "test-cases": [
70        {
71          "name": "Registers",
72          "operands": [
73            "rd", "rn", "rm"
74          ],
75          "operand-limit": 500
76        }
77      ]
78    },
79    {
80      "type": "simulator",
81      "test-cases": [
82        {
83          "name": "RnIsRm",
84          "operands": [
85            "rd", "rn", "rm"
86          ],
87          "inputs": [
88            "rd", "rn", "rm"
89          ],
90          "operand-filter": "rn == rm",
91          "operand-limit": 10,
92          "input-filter": "rn == rm",
93          "input-limit": 200
94        },
95        {
96          "name": "RnIsNotRm",
97          "operands": [
98            "rd", "rn", "rm"
99          ],
100          "inputs": [
101            "rd", "rn", "rm"
102          ],
103          "operand-filter": "rn != rm",
104          "operand-limit": 10,
105          "input-filter": "rn != rm",
106          "input-limit": 200
107        }
108      ]
109    }
110  ]
111}
112