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Searched refs:instr (Results 1 – 25 of 135) sorted by relevance

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/art/compiler/optimizing/
Dscheduler_arm64.cc24 void SchedulingLatencyVisitorARM64::VisitBinaryOperation(HBinaryOperation* instr) { in VisitBinaryOperation() argument
25 last_visited_latency_ = Primitive::IsFloatingPointType(instr->GetResultType()) in VisitBinaryOperation()
48 HIntermediateAddressIndex* instr ATTRIBUTE_UNUSED) { in VisitIntermediateAddressIndex()
80 void SchedulingLatencyVisitorARM64::VisitDiv(HDiv* instr) { in VisitDiv() argument
81 Primitive::Type type = instr->GetResultType(); in VisitDiv()
91 if (instr->GetRight()->IsConstant()) { in VisitDiv()
92 int64_t imm = Int64FromConstant(instr->GetRight()->AsConstant()); in VisitDiv()
133 void SchedulingLatencyVisitorARM64::VisitMul(HMul* instr) { in VisitMul() argument
134 last_visited_latency_ = Primitive::IsFloatingPointType(instr->GetResultType()) in VisitMul()
194 void SchedulingLatencyVisitorARM64::VisitTypeConversion(HTypeConversion* instr) { in VisitTypeConversion() argument
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Dreference_type_propagation.cc86 void VisitLoadString(HLoadString* instr) OVERRIDE;
87 void VisitLoadException(HLoadException* instr) OVERRIDE;
88 void VisitNewArray(HNewArray* instr) OVERRIDE;
89 void VisitParameterValue(HParameterValue* instr) OVERRIDE;
90 void UpdateFieldAccessTypeInfo(HInstruction* instr, const FieldInfo& info);
91 void SetClassAsTypeInfo(HInstruction* instr, ObjPtr<mirror::Class> klass, bool is_exact)
93 void VisitInstanceFieldGet(HInstanceFieldGet* instr) OVERRIDE;
94 void VisitStaticFieldGet(HStaticFieldGet* instr) OVERRIDE;
95 void VisitUnresolvedInstanceFieldGet(HUnresolvedInstanceFieldGet* instr) OVERRIDE;
96 void VisitUnresolvedStaticFieldGet(HUnresolvedStaticFieldGet* instr) OVERRIDE;
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Dcommon_arm.h96 inline vixl::aarch32::SRegister OutputSRegister(HInstruction* instr) { in OutputSRegister() argument
97 Primitive::Type type = instr->GetType(); in OutputSRegister()
99 return SRegisterFrom(instr->GetLocations()->Out()); in OutputSRegister()
102 inline vixl::aarch32::DRegister OutputDRegister(HInstruction* instr) { in OutputDRegister() argument
103 Primitive::Type type = instr->GetType(); in OutputDRegister()
105 return DRegisterFrom(instr->GetLocations()->Out()); in OutputDRegister()
108 inline vixl::aarch32::VRegister OutputVRegister(HInstruction* instr) { in OutputVRegister() argument
109 Primitive::Type type = instr->GetType(); in OutputVRegister()
111 return OutputSRegister(instr); in OutputVRegister()
113 return OutputDRegister(instr); in OutputVRegister()
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Dcommon_arm64.h81 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { in OutputRegister() argument
82 return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputRegister()
85 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt() argument
86 return RegisterFrom(instr->GetLocations()->InAt(input_index), in InputRegisterAt()
87 instr->InputAt(input_index)->GetType()); in InputRegisterAt()
115 inline vixl::aarch64::FPRegister OutputFPRegister(HInstruction* instr) { in OutputFPRegister() argument
116 return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputFPRegister()
119 inline vixl::aarch64::FPRegister InputFPRegisterAt(HInstruction* instr, int input_index) { in InputFPRegisterAt() argument
120 return FPRegisterFrom(instr->GetLocations()->InAt(input_index), in InputFPRegisterAt()
121 instr->InputAt(input_index)->GetType()); in InputFPRegisterAt()
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Dinstruction_simplifier_shared.h41 inline bool HasShifterOperand(HInstruction* instr, InstructionSet isa) { in HasShifterOperand() argument
44 bool res = instr->IsAdd() || instr->IsAnd() || (isa == kArm64 && instr->IsNeg()) || in HasShifterOperand()
45 instr->IsOr() || instr->IsSub() || instr->IsXor(); in HasShifterOperand()
Dscheduler_arm.cc29 void SchedulingLatencyVisitorARM::HandleBinaryOperationLantencies(HBinaryOperation* instr) { in HandleBinaryOperationLantencies() argument
30 switch (instr->GetResultType()) { in HandleBinaryOperationLantencies()
48 void SchedulingLatencyVisitorARM::VisitAdd(HAdd* instr) { in VisitAdd() argument
49 HandleBinaryOperationLantencies(instr); in VisitAdd()
52 void SchedulingLatencyVisitorARM::VisitSub(HSub* instr) { in VisitSub() argument
53 HandleBinaryOperationLantencies(instr); in VisitSub()
56 void SchedulingLatencyVisitorARM::VisitMul(HMul* instr) { in VisitMul() argument
57 switch (instr->GetResultType()) { in VisitMul()
72 void SchedulingLatencyVisitorARM::HandleBitwiseOperationLantencies(HBinaryOperation* instr) { in HandleBitwiseOperationLantencies() argument
73 switch (instr->GetResultType()) { in HandleBitwiseOperationLantencies()
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Dreference_type_propagation.h95 void AddToWorklist(HInstruction* instr);
96 void AddDependentInstructionsToWorklist(HInstruction* instr);
98 bool UpdateNullability(HInstruction* instr);
99 bool UpdateReferenceTypeInfo(HInstruction* instr);
101 static void UpdateArrayGet(HArrayGet* instr, HandleCache* handle_cache)
Dscheduler.h157 SchedulingNode(HInstruction* instr, ArenaAllocator* arena, bool is_scheduling_barrier) in SchedulingNode() argument
161 instruction_(instr), in SchedulingNode()
253 SchedulingNode* AddNode(HInstruction* instr, bool is_scheduling_barrier = false) {
254 SchedulingNode* node = new (arena_) SchedulingNode(instr, arena_, is_scheduling_barrier);
255 nodes_map_.Insert(std::make_pair(instr, node));
257 AddDependencies(instr, is_scheduling_barrier);
270 SchedulingNode* GetNode(const HInstruction* instr) const { in GetNode() argument
271 auto it = nodes_map_.Find(instr); in GetNode()
Dnodes_shared.h215 HDataProcWithShifterOp(HInstruction* instr,
223 : HExpression(instr->GetType(), SideEffects::None(), dex_pc),
224 instr_kind_(instr->GetKind()), op_kind_(op),
225 shift_amount_(shift & (instr->GetType() == Primitive::kPrimInt
228 DCHECK(!instr->HasSideEffects());
Dscheduler_test.cc131 for (HInstruction* instr : block_instructions) { in TestBuildDependencyGraphAndSchedule()
132 block1->AddInstruction(instr); in TestBuildDependencyGraphAndSchedule()
148 for (HInstruction* instr : ReverseRange(block_instructions)) { in TestBuildDependencyGraphAndSchedule()
149 scheduling_graph.AddNode(instr); in TestBuildDependencyGraphAndSchedule()
262 for (HInstruction* instr : block_instructions) { in TestDependencyGraphOnAliasingArrayAccesses()
263 entry->AddInstruction(instr); in TestDependencyGraphOnAliasingArrayAccesses()
272 for (HInstruction* instr : ReverseRange(block_instructions)) { in TestDependencyGraphOnAliasingArrayAccesses()
275 scheduling_graph.AddNode(instr); in TestDependencyGraphOnAliasingArrayAccesses()
Dgraph_visualizer.h66 void AddInstructionInterval(HInstruction* instr, size_t start, size_t end) { in AddInstructionInterval() argument
67 instruction_intervals_.Put(instr, {start, end}); in AddInstructionInterval()
/art/disassembler/
Ddisassembler_x86.cc164 RegFile dst_reg_file, const uint8_t** instr, in DumpAddress() argument
169 *address_bits = *reinterpret_cast<const uint32_t*>(*instr); in DumpAddress()
172 address << StringPrintf("[RIP + 0x%x]", *reinterpret_cast<const uint32_t*>(*instr)); in DumpAddress()
174 (*instr) += 4; in DumpAddress()
176 uint8_t sib = **instr; in DumpAddress()
177 (*instr)++; in DumpAddress()
209 address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(*instr)); in DumpAddress()
212 *address_bits = *reinterpret_cast<const uint32_t*>(*instr); in DumpAddress()
215 (*instr) += 4; in DumpAddress()
218 address << StringPrintf(" + %d", *reinterpret_cast<const int8_t*>(*instr)); in DumpAddress()
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Ddisassembler_arm64.cc44 void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr, in AppendRegisterNameToOutput() argument
46 USE(instr); in AppendRegisterNameToOutput()
58 Disassembler::AppendRegisterNameToOutput(instr, reg); in AppendRegisterNameToOutput()
61 void CustomDisassembler::VisitLoadLiteral(const Instruction* instr) { in VisitLoadLiteral() argument
62 Disassembler::VisitLoadLiteral(instr); in VisitLoadLiteral()
71 void* data_address = instr->GetLiteralAddress<void*>(); in VisitLoadLiteral()
78 Instr op = instr->Mask(LoadLiteralMask); in VisitLoadLiteral()
100 void CustomDisassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) { in VisitLoadStoreUnsignedOffset() argument
101 Disassembler::VisitLoadStoreUnsignedOffset(instr); in VisitLoadStoreUnsignedOffset()
103 if (instr->GetRn() == TR) { in VisitLoadStoreUnsignedOffset()
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Ddisassembler_x86.h36 size_t DumpNops(std::ostream& os, const uint8_t* instr);
37 size_t DumpInstruction(std::ostream& os, const uint8_t* instr);
41 RegFile src_reg_file, RegFile dst_reg_file, const uint8_t** instr,
Ddisassembler_arm64.h47 void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr,
51 void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) OVERRIDE;
54 void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) OVERRIDE;
/art/runtime/
Dinstrumentation_test.cc187 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in CheckConfigureStubs() local
193 instr->ConfigureStubs(key, level); in CheckConfigureStubs()
214 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in TestEvent() local
219 instr->AddListener(&listener, instrumentation_event); in TestEvent()
226 EXPECT_TRUE(HasEventListener(instr, instrumentation_event)); in TestEvent()
228 ReportEvent(instr, in TestEvent()
241 instr->RemoveListener(&listener, instrumentation_event); in TestEvent()
245 EXPECT_FALSE(HasEventListener(instr, instrumentation_event)); in TestEvent()
247 ReportEvent(instr, in TestEvent()
343 static bool HasEventListener(const instrumentation::Instrumentation* instr, uint32_t event_type) in HasEventListener() argument
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Dcommon_throws.cc442 static bool IsValidImplicitCheck(uintptr_t addr, ArtMethod* method, const Instruction& instr) in IsValidImplicitCheck() argument
448 switch (instr.Opcode()) { in IsValidImplicitCheck()
485 Runtime::Current()->GetClassLinker()->ResolveField(instr.VRegC_22c(), method, false); in IsValidImplicitCheck()
507 return (addr == 0u) || (addr == instr.VRegC_22c()); in IsValidImplicitCheck()
550 const Instruction* instr = Instruction::At(&code->insns_[throw_dex_pc]); in ThrowNullPointerExceptionFromDexPC() local
551 if (check_address && !IsValidImplicitCheck(addr, method, *instr)) { in ThrowNullPointerExceptionFromDexPC()
556 << instr->DumpString(dex_file) in ThrowNullPointerExceptionFromDexPC()
561 switch (instr->Opcode()) { in ThrowNullPointerExceptionFromDexPC()
563 ThrowNullPointerExceptionForMethodAccess(instr->VRegB_35c(), kDirect); in ThrowNullPointerExceptionFromDexPC()
566 ThrowNullPointerExceptionForMethodAccess(instr->VRegB_3rc(), kDirect); in ThrowNullPointerExceptionFromDexPC()
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/art/runtime/interpreter/mterp/x86_64/
Dbinop1.S12 $instr # ex: addl %ecx,%eax
16 $instr # ex: addl %ecx,%eax
Dshop2addr.S12 $instr # ex: sarl %cl, %eax
16 $instr # ex: sarl %cl, %eax
/art/runtime/interpreter/
Dinterpreter.cc470 static bool IsStringInit(const Instruction* instr, ArtMethod* caller) in IsStringInit() argument
472 if (instr->Opcode() == Instruction::INVOKE_DIRECT || in IsStringInit()
473 instr->Opcode() == Instruction::INVOKE_DIRECT_RANGE) { in IsStringInit()
476 uint16_t callee_method_idx = (instr->Opcode() == Instruction::INVOKE_DIRECT_RANGE) ? in IsStringInit()
477 instr->VRegB_3rc() : instr->VRegB_35c(); in IsStringInit()
493 static int16_t GetReceiverRegisterForStringInit(const Instruction* instr) { in GetReceiverRegisterForStringInit() argument
494 DCHECK(instr->Opcode() == Instruction::INVOKE_DIRECT_RANGE || in GetReceiverRegisterForStringInit()
495 instr->Opcode() == Instruction::INVOKE_DIRECT); in GetReceiverRegisterForStringInit()
496 return (instr->Opcode() == Instruction::INVOKE_DIRECT_RANGE) ? in GetReceiverRegisterForStringInit()
497 instr->VRegC_3rc() : instr->VRegC_35c(); in GetReceiverRegisterForStringInit()
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/art/runtime/interpreter/mterp/arm/
Dop_nop.S1 FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST
/art/runtime/interpreter/mterp/arm64/
Dunop.S14 $instr // w0<- op, w0-w3 changed
DunopWide.S13 $instr
DfunopNarrower.S13 $instr // d0<- op
DfunopNarrow.S14 $instr // d0<- op

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