| /art/runtime/arch/x86/ |
| D | quick_entrypoints_x86.S | 27 MACRO2(SETUP_SAVE_ALL_CALLEE_SAVES_FRAME, got_reg, temp_reg)
35 movl SYMBOL(_ZN3art7Runtime9instance_E)@GOT(REG_VAR(got_reg)), REG_VAR(temp_reg)
36 movl (REG_VAR(temp_reg)), REG_VAR(temp_reg)
38 pushl RUNTIME_SAVE_ALL_CALLEE_SAVES_METHOD_OFFSET(REG_VAR(temp_reg))
53 MACRO2(SETUP_SAVE_REFS_ONLY_FRAME, got_reg, temp_reg)
61 movl SYMBOL(_ZN3art7Runtime9instance_E)@GOT(REG_VAR(got_reg)), REG_VAR(temp_reg)
62 movl (REG_VAR(temp_reg)), REG_VAR(temp_reg)
64 pushl RUNTIME_SAVE_REFS_ONLY_METHOD_OFFSET(REG_VAR(temp_reg))
81 MACRO2(SETUP_SAVE_REFS_ONLY_FRAME_PRESERVE_GOT_REG, got_reg, temp_reg)
91 movl SYMBOL(_ZN3art7Runtime9instance_E)@GOT(REG_VAR(got_reg)), REG_VAR(temp_reg)
[all …]
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| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 72 const vixl::aarch32::Register temp_reg = temps.Acquire(); in CreateTrampoline() local
76 ___ Ldr(temp_reg, MemOperand(r0, JNIEnvExt::SelfOffset(4).Int32Value())); in CreateTrampoline()
77 ___ Ldr(pc, MemOperand(temp_reg, offset.Int32Value())); in CreateTrampoline()
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| /art/compiler/optimizing/ |
| D | intrinsics_arm_vixl.cc | 1022 const vixl32::Register temp_reg = temps.Acquire(); in GenUnsafeGet() local
1023 __ Add(temp_reg, base, offset); in GenUnsafeGet()
1024 __ Ldrexd(trg_lo, trg_hi, MemOperand(temp_reg)); in GenUnsafeGet()
1184 const vixl32::Register temp_reg = temps.Acquire(); in GenUnsafePut() local
1186 __ Add(temp_reg, base, offset); in GenUnsafePut()
1189 __ Ldrexd(temp_lo, temp_hi, MemOperand(temp_reg)); in GenUnsafePut()
1190 __ Strexd(temp_lo, value_lo, value_hi, MemOperand(temp_reg)); in GenUnsafePut()
1572 vixl32::Register temp_reg = temps.Acquire(); in VisitStringCompareTo() local
1573 __ Ldr(temp_reg, MemOperand(str, temp1)); in VisitStringCompareTo()
1575 __ Cmp(temp_reg, temp2); in VisitStringCompareTo()
[all …]
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| D | code_generator_x86.cc | 4134 Register temp_reg = locations->GetTemp(0).AsRegister<Register>(); in VisitRor() local
4138 __ movl(temp_reg, first_reg_hi); in VisitRor()
4140 __ shrd(first_reg_lo, temp_reg, second_reg); in VisitRor()
4141 __ movl(temp_reg, first_reg_hi); in VisitRor()
4144 __ cmovl(kNotEqual, first_reg_lo, temp_reg); in VisitRor()
4153 __ movl(temp_reg, first_reg_lo); in VisitRor()
4155 __ movl(first_reg_hi, temp_reg); in VisitRor()
4161 __ movl(temp_reg, first_reg_lo); in VisitRor()
4167 __ shrd(first_reg_hi, temp_reg, imm); in VisitRor()
4171 __ movl(temp_reg, first_reg_lo); in VisitRor()
[all …]
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| D | code_generator_mips64.cc | 4529 GpuRegister temp_reg = temp.AsRegister<GpuRegister>(); in GenerateReferenceLoadWithBakerReadBarrier() local
4533 __ LoadFromOffset(kLoadWord, temp_reg, obj, monitor_offset); in GenerateReferenceLoadWithBakerReadBarrier()
4584 temp_reg); in GenerateReferenceLoadWithBakerReadBarrier()
4598 __ Sll(temp_reg, temp_reg, 31 - LockWord::kReadBarrierStateShift); in GenerateReferenceLoadWithBakerReadBarrier()
4599 __ Bltzc(temp_reg, slow_path->GetEntryLabel()); in GenerateReferenceLoadWithBakerReadBarrier()
6228 GpuRegister temp_reg = TMP; in GenPackedSwitchWithCompares() local
6229 __ Addiu32(temp_reg, value_reg, -lower_bound); in GenPackedSwitchWithCompares()
6233 __ Bltzc(temp_reg, codegen_->GetLabelOf(default_block)); in GenPackedSwitchWithCompares()
6237 __ Beqzc(temp_reg, codegen_->GetLabelOf(successors[0])); in GenPackedSwitchWithCompares()
6240 __ Addiu(temp_reg, temp_reg, -2); in GenPackedSwitchWithCompares()
[all …]
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| D | code_generator_mips.cc | 6605 Register temp_reg = temp.AsRegister<Register>(); in GenerateReferenceLoadWithBakerReadBarrier() local
6609 __ LoadFromOffset(kLoadWord, temp_reg, obj, monitor_offset); in GenerateReferenceLoadWithBakerReadBarrier()
6663 temp_reg); in GenerateReferenceLoadWithBakerReadBarrier()
6677 __ Sll(temp_reg, temp_reg, 31 - LockWord::kReadBarrierStateShift); in GenerateReferenceLoadWithBakerReadBarrier()
6678 __ Bltz(temp_reg, slow_path->GetEntryLabel()); in GenerateReferenceLoadWithBakerReadBarrier()
7223 Register temp_reg = temp.AsRegister<Register>(); in GenerateStaticOrDirectCall() local
7225 __ Addiu(temp_reg, TMP, /* placeholder */ 0x5678); in GenerateStaticOrDirectCall()
7237 Register temp_reg = temp.AsRegister<Register>(); in GenerateStaticOrDirectCall() local
7240 __ Lw(temp_reg, TMP, /* placeholder */ 0x5678); in GenerateStaticOrDirectCall()
8648 Register temp_reg = TMP; in GenPackedSwitchWithCompares() local
[all …]
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| D | code_generator_arm_vixl.cc | 8834 vixl32::Register temp_reg = RegisterFrom(temp); in GenerateReferenceLoadWithBakerReadBarrier() local
8840 instruction, ref, obj, offset, index, scale_factor, needs_null_check, temp_reg); in GenerateReferenceLoadWithBakerReadBarrier()
8880 vixl32::Register temp_reg = RegisterFrom(temp); in UpdateReferenceFieldWithBakerReadBarrier() local
8893 temp_reg, in UpdateReferenceFieldWithBakerReadBarrier()
9074 vixl32::Register temp_reg = RegisterFrom(temp); in GenerateStaticOrDirectCall() local
9075 EmitMovwMovtPlaceholder(labels, temp_reg); in GenerateStaticOrDirectCall()
9084 vixl32::Register temp_reg = RegisterFrom(temp); in GenerateStaticOrDirectCall() local
9085 EmitMovwMovtPlaceholder(labels, temp_reg); in GenerateStaticOrDirectCall()
9086 GetAssembler()->LoadFromOffset(kLoadWord, temp_reg, temp_reg, /* offset*/ 0); in GenerateStaticOrDirectCall()
9373 vixl32::Register temp_reg = temps.Acquire(); in VisitPackedSwitch() local
[all …]
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| D | code_generator_x86_64.cc | 6772 CpuRegister temp_reg = locations->GetTemp(0).AsRegister<CpuRegister>(); in VisitPackedSwitch() local
6825 __ leal(temp_reg, Address(value_reg_in, -lower_bound)); in VisitPackedSwitch()
6826 value_reg_out = temp_reg.AsRegister(); in VisitPackedSwitch()
6839 __ movsxd(temp_reg, Address(base_reg, value_reg, TIMES_4, 0)); in VisitPackedSwitch()
6842 __ addq(temp_reg, base_reg); in VisitPackedSwitch()
6845 __ jmp(temp_reg); in VisitPackedSwitch()
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| D | code_generator_arm64.cc | 5866 Register temp_reg = RegisterFrom(maybe_temp, type); in GenerateReferenceLoadOneRegister() local
5867 __ Mov(temp_reg, out_reg); in GenerateReferenceLoadOneRegister()
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