| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 195 case ISD::ADDE: { in trySelect()
199 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in trySelect()
204 if (Opcode == ISD::ADDE) { in trySelect()
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| D | MipsSEISelDAGToDAG.cpp | 245 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectAddESubE()
739 case ISD::ADDE: { in trySelect()
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| /external/swiftshader/third_party/LLVM/test/CodeGen/Alpha/ |
| D | add128.ll | 1 ;test for ADDC and ADDE expansion
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 210 case ISD::ADDE: { in Select()
213 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in Select()
218 if (Opcode == ISD::ADDE) { in Select()
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| D | MipsISelLowering.cpp | 217 setTargetDAGCombine(ISD::ADDE); in MipsTargetLowering()
644 case ISD::ADDE: in PerformDAGCombine()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 123 case ISD::ADDE: in isdToLanaiAluCode()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 98 setOperationAction(ISD::ADDE, MVT::i32, Custom); in BlackfinTargetLowering()
429 unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB; in LowerADDE()
471 case ISD::ADDE: in LowerOperation()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_32.c | 124 FAIL_IF(push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2))); in emit_single_op()
127 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)); in emit_single_op()
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| D | sljitNativePPC_64.c | 245 FAIL_IF(push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2))); in emit_single_op()
249 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)); in emit_single_op()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 217 ADDE, SUBE, enumerator
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| D | SelectionDAG.h | 907 case ISD::ADDE: return true;
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 223 ADDE, SUBE, enumerator
|
| D | SelectionDAG.h | 1185 case ISD::ADDE:
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 75 ADDE, // Add using carry enumerator
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| D | ARMISelLowering.cpp | 567 setOperationAction(ISD::ADDE, MVT::i32, Custom); in ARMTargetLowering()
845 case ARMISD::ADDE: return "ARMISD::ADDE"; in getTargetNodeName()
4879 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
4983 case ISD::ADDE: in LowerOperation()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 72 ADDE, // Add using carry enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 227 case ISD::ADDE: return "adde"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 1390 case ISD::ADDE: in ExpandIntegerResult()
1751 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
1832 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 99 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 91 setOperationAction(ISD::ADDE, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 1145 case ISD::ADDE: in ExpandIntegerResult()
1284 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3); in ExpandShiftByConstant()
1527 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUB()
1576 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUBC()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1834 setOperationAction(ISD::ADDE, MVT::i8, Expand); in HexagonTargetLowering()
1835 setOperationAction(ISD::ADDE, MVT::i16, Expand); in HexagonTargetLowering()
1836 setOperationAction(ISD::ADDE, MVT::i32, Expand); in HexagonTargetLowering()
1837 setOperationAction(ISD::ADDE, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1614 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
2929 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2930 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3078 case ISD::ADDE: in LowerOperation()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 103 setOperationAction(ISD::ADDE , MVT::i64, Expand); in AlphaTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 90 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
|