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Searched refs:ADDR_TILEINFO (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/amd/addrlib/r800/
Degbaddrlib.h108 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo,
123 BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const;
160 ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
182 ADDR_TILEINFO* pTileInfo) const = 0;
191 UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const = 0;
198 ADDR_TILEINFO* pTileInfo) const = 0;
201 const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const;
207 const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
237 ADDR_TILEINFO* pTileInfo) const;
246 ADDR_TILEINFO* pTileInfo) const;
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Dsiaddrlib.h49 ADDR_TILEINFO info;
102 ADDR_TILEINFO* pTileInfo, UINT_32* pBitPosition) const;
107 ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
124 ADDR_TILEINFO* pInfo, AddrTileMode* pMode = 0, AddrTileType* pType = 0) const;
128 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
137 ADDR_TILEINFO* pTileInfo) const;
139 virtual UINT_32 HwlGetPipes(const ADDR_TILEINFO* pTileInfo) const;
156 ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
171 const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const;
182 ADDR_TILEINFO* pTileInfo) const in HwlSanityCheckMacroTiled()
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Dciaddrlib.h108 INT_32 index, INT_32 macroModeIndex, ADDR_TILEINFO* pInfo,
113 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
117 ADDR_TILEINFO* pTileInfo, AddrTileMode* pTileMode = NULL, AddrTileType* pTileType = NULL
124 ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
128 const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
162 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
171 UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
194 ADDR_TILEINFO m_macroTileTable[MacroTileTableSize];
Degbaddrlib.cpp95 ADDR_TILEINFO tileInfoDef = {0}; in DispatchComputeSurfaceInfo()
96 ADDR_TILEINFO* pTileInfo = &tileInfoDef; in DispatchComputeSurfaceInfo()
134 memset(pTileInfo, 0, sizeof(ADDR_TILEINFO)); in DispatchComputeSurfaceInfo()
704 ADDR_TILEINFO* pTileInfo ///< [in/out] bank structure. in HwlReduceBankWidthHeight()
807 ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure. in ComputeSurfaceAlignmentsMacroTiled()
920 ADDR_TILEINFO* pTileInfo ///< [in] macro-tiled parameters in SanityCheckMacroTiled()
1034 ADDR_TILEINFO* pTileInfo ///< [in] ptr to bank structure in ComputeSurfaceMipLevelTileMode()
1128 ADDR_TILEINFO tileInfo = *pIn->pTileInfo; in HwlDegradeBaseLevel()
1273 ADDR_TILEINFO* pTileInfo = pIn->pTileInfo; in DispatchComputeSurfaceAddrFromCoord()
1434 ADDR_TILEINFO* pTileInfo, ///< [in] bank structure in ComputeSurfaceAddrFromCoordMacroTiled()
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Dciaddrlib.cpp450 const ADDR_TILEINFO* pInfo, ///< [in] Tile Info in HwlPostCheckTileIndex()
541 ADDR_TILEINFO* pInfo, ///< [out] Tile Info in HwlSetupTileCfg()
650 ADDR_TILEINFO tileInfo = {0}; in HwlComputeFmaskInfo()
962 ADDR_TILEINFO* pTileInfoIn, ///< [in] Tile info input: NULL for default in HwlSetupTileInfo()
963 ADDR_TILEINFO* pTileInfoOut, ///< [out] Tile info output in HwlSetupTileInfo()
969 ADDR_TILEINFO* pTileInfo = pTileInfoOut; in HwlSetupTileInfo()
1377 ADDR_TILEINFO* pCfg ///< [out] output structure in ReadGbMacroTileCfg()
1451 ADDR_TILEINFO* pTileInfo, ///< [out] Pointer to ADDR_TILEINFO in HwlComputeMacroModeIndex()
1569 ADDR_TILEINFO* pTileInfo ///< [in] tile info in HwlComputeTileDataWidthAndHeightLinear()
1764 ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure. in HwlPadDimensions()
Dsiaddrlib.cpp105 const ADDR_TILEINFO* pTileInfo ///< [in] Tile info in HwlGetPipes()
186 ADDR_TILEINFO* pTileInfo ///< [in] Tile info in ComputePipeFromCoord()
731 ADDR_TILEINFO* pTileInfo ///< [in] tile info in HwlComputeTileDataWidthAndHeightLinear()
804 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info in HwlComputeXmaskAddrFromCoord()
962 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info in HwlComputeXmaskCoordFromAddr()
1457 ADDR_TILEINFO* pTileInfoIn, ///< [in] Tile info input: NULL for default in HwlSetupTileInfo()
1458 ADDR_TILEINFO* pTileInfoOut, ///< [out] Tile info output in HwlSetupTileInfo()
1464 ADDR_TILEINFO* pTileInfo = pTileInfoOut; in HwlSetupTileInfo()
1984 ADDR_TILEINFO* pTileInfo ///< [in] bank structure. **All fields to be valid on entry** in HwlComputeSurfaceCoord2DFromBankPipe()
2141 ADDR_TILEINFO* pTileInfo ///< [in] tile info in HwlPreAdjustBank()
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/external/mesa3d/src/amd/addrlib/
Daddrinterface.h402 } ADDR_TILEINFO; typedef
406 typedef ADDR_TILEINFO ADDR_R800_TILEINFO;
502 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate
549 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input
619 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
713 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
800 ADDR_TILEINFO* pTileInfo; ///< Tile info
868 ADDR_TILEINFO* pTileInfo; ///< Tile info
929 ADDR_TILEINFO* pTileInfo; ///< Tile info
1010 ADDR_TILEINFO* pTileInfo; ///< Tile info
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/external/mesa3d/src/amd/addrlib/core/
Daddrlib.h346 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo,
356 BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const = 0;
429 ADDR_TILEINFO* pTileInfo,
438 ADDR_TILEINFO* pTileInfo, UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pCmaskBytes,
444 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
450 BOOL_32 isHeight8, ADDR_TILEINFO* pTileInfo,
456 ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
479 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
485 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel, in HwlPadDimensions()
526 const ADDR_TILEINFO* pTileInfo) const;
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Daddrlib.cpp419 ADDR_TILEINFO tileInfoNull = {0}; in ComputeSurfaceInfo()
678 ADDR_TILEINFO tileInfoNull; in ComputeSurfaceAddrFromCoord()
758 ADDR_TILEINFO tileInfoNull; in ComputeSurfaceCoordFromAddr()
833 ADDR_TILEINFO tileInfoNull; in ComputeSliceTileSwizzle()
886 ADDR_TILEINFO tileInfoNull; in ExtractBankPipeSwizzle()
938 ADDR_TILEINFO tileInfoNull; in CombineBankPipeSwizzle()
992 ADDR_TILEINFO tileInfoNull; in ComputeBaseSwizzle()
1057 ADDR_TILEINFO tileInfoNull; in ComputeFmaskInfo()
1233 ADDR_TILEINFO tileInfoNull; in ConvertTileInfoToHW()
1444 ADDR_TILEINFO tileInfoNull; in ComputeHtileInfo()
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/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c301 ADDR_TILEINFO AddrTileInfoIn = {0}; in radv_amdgpu_winsys_surface_init()
302 ADDR_TILEINFO AddrTileInfoOut = {0}; in radv_amdgpu_winsys_surface_init()
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c315 ADDR_TILEINFO AddrTileInfoIn = {0}; in amdgpu_surface_init()
316 ADDR_TILEINFO AddrTileInfoOut = {0}; in amdgpu_surface_init()