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Searched refs:ADDR_TM_1D_TILED_THIN1 (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/amd/addrlib/r800/
Dciaddrlib.cpp851 tileMode = ADDR_TM_1D_TILED_THIN1; in HwlOverrideTileMode()
1063 case ADDR_TM_1D_TILED_THIN1: in HwlSetupTileInfo()
1079 case ADDR_TM_1D_TILED_THIN1: in HwlSetupTileInfo()
1098 case ADDR_TM_1D_TILED_THIN1: in HwlSetupTileInfo()
1150 case ADDR_TM_1D_TILED_THIN1: in HwlSetupTileInfo()
Degbaddrlib.cpp170 case ADDR_TM_1D_TILED_THIN1://fall through in DispatchComputeSurfaceInfo()
1083 expTileMode = ADDR_TM_1D_TILED_THIN1; in ComputeSurfaceMipLevelTileMode()
1195 expTileMode = ADDR_TM_1D_TILED_THIN1; in HwlDegradeThickTileMode()
1324 case ADDR_TM_1D_TILED_THIN1://fall through in DispatchComputeSurfaceAddrFromCoord()
2072 case ADDR_TM_1D_TILED_THIN1://fall through in DispatchComputeSurfaceCoordFromAddr()
3282 case ADDR_TM_1D_TILED_THIN1: in DispatchComputeFmaskAddrFromCoord()
3787 case ADDR_TM_1D_TILED_THIN1: in DispatchComputeFmaskCoordFromAddr()
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c220 case ADDR_TM_1D_TILED_THIN1: in radv_compute_level()
335 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1; in radv_amdgpu_winsys_surface_init()
/external/mesa3d/src/amd/addrlib/
Daddrtypes.h175 ADDR_TM_1D_TILED_THIN1 = 2, ///< Linear array of 8x8 tiles enumerator
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c201 case ADDR_TM_1D_TILED_THIN1: in compute_level()
354 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1; in amdgpu_surface_init()
/external/mesa3d/src/amd/addrlib/core/
Daddrlib.cpp3519 *pTileMode = thickness == 1 ? ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK; in DegradeBaseLevel()