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Searched refs:ADDR_TM_2D_TILED_THIN1 (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c223 case ADDR_TM_2D_TILED_THIN1: in radv_compute_level()
338 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1; in radv_amdgpu_winsys_surface_init()
406 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && in radv_amdgpu_winsys_surface_init()
428 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); in radv_amdgpu_winsys_surface_init()
472 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) { in radv_amdgpu_winsys_surface_init()
505 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) { in radv_amdgpu_winsys_surface_init()
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c204 case ADDR_TM_2D_TILED_THIN1: in compute_level()
357 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1; in amdgpu_surface_init()
438 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && in amdgpu_surface_init()
462 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); in amdgpu_surface_init()
513 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) { in amdgpu_surface_init()
548 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) { in amdgpu_surface_init()
/external/mesa3d/src/amd/addrlib/r800/
Dciaddrlib.cpp662 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
668 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
672 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
856 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1082 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1101 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1153 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
Degbaddrlib.cpp175 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1073 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1199 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1209 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1339 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2090 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2349 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
2860 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
2886 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
2996 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
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Dsiaddrlib.cpp928 UINT_32 pipe = ComputePipeFromCoord(x, y, 0, ADDR_TM_2D_TILED_THIN1, 0, FALSE, pTileInfo); in HwlComputeXmaskAddrFromCoord()
2790 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
/external/mesa3d/src/amd/addrlib/
Daddrtypes.h177 ADDR_TM_2D_TILED_THIN1 = 4, ///< A set of macro tiles consist of 8x8 tiles enumerator
/external/mesa3d/src/amd/addrlib/core/
Daddrlib.cpp2598 ADDR_TM_2D_TILED_THIN1, in HwlComputeXmaskAddrFromCoord()
3580 tileMode = ADDR_TM_2D_TILED_THIN1; in DegradeLargeThickTile()