Searched refs:ADDR_TM_3D_TILED_THIN1 (Results 1 – 5 of 5) sorted by relevance
177 case ADDR_TM_3D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()1074 case ADDR_TM_3D_TILED_THIN1: in ComputeSurfaceMipLevelTileMode()1203 expTileMode = ADDR_TM_3D_TILED_THIN1; in HwlDegradeThickTileMode()1221 expTileMode = ADDR_TM_3D_TILED_THIN1; in HwlDegradeThickTileMode()1341 case ADDR_TM_3D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()2092 case ADDR_TM_3D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()2352 case ADDR_TM_3D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()2865 case ADDR_TM_3D_TILED_THIN1: // fall through in ComputeBankFromCoord()2887 case ADDR_TM_3D_TILED_THIN1: //fall through in ComputeBankFromCoord()2960 case ADDR_TM_3D_TILED_THIN1: //fall through in ComputePipeRotation()[all …]
663 tileMode == ADDR_TM_3D_TILED_THIN1 || in HwlComputeFmaskInfo()669 ADDR_ASSERT(m_tileTable[15].mode == ADDR_TM_3D_TILED_THIN1); in HwlComputeFmaskInfo()861 tileMode = ADDR_TM_3D_TILED_THIN1; in HwlOverrideTileMode()997 else if (tileMode == ADDR_TM_3D_TILED_THIN1 || tileMode == ADDR_TM_PRT_3D_TILED_THIN1) in HwlSetupTileInfo()1104 case ADDR_TM_3D_TILED_THIN1: in HwlSetupTileInfo()
302 case ADDR_TM_3D_TILED_THIN1: //fall through thin in ComputePipeFromCoord()
185 ADDR_TM_3D_TILED_THIN1 = 12, ///< Macro tiling w/ pipe rotation between slices enumerator
3591 tileMode = ADDR_TM_3D_TILED_THIN1; in DegradeLargeThickTile()