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Searched refs:ADDR_TM_LINEAR_ALIGNED (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c217 case ADDR_TM_LINEAR_ALIGNED: in radv_compute_level()
332 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED; in radv_amdgpu_winsys_surface_init()
/external/mesa3d/src/amd/addrlib/
Daddrtypes.h174 ADDR_TM_LINEAR_ALIGNED = 1, ///< Requests pitch or slice to be multiple of 64 pixels enumerator
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c198 case ADDR_TM_LINEAR_ALIGNED: in compute_level()
351 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED; in amdgpu_surface_init()
/external/mesa3d/src/amd/addrlib/r800/
Dciaddrlib.cpp497 else if (mode == ADDR_TM_LINEAR_ALIGNED) in HwlPostCheckTileIndex()
1213 else if (tileMode == ADDR_TM_LINEAR_ALIGNED) in HwlSetupTileInfo()
1341 ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED); in InitTileSettingTable()
Dsiaddrlib.cpp1707 if (tileMode == ADDR_TM_LINEAR_ALIGNED) in HwlSetupTileInfo()
2403 else if (mode == ADDR_TM_LINEAR_ALIGNED) in HwlPostCheckTileIndex()
2599 ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED); in InitTileSettingTable()
Degbaddrlib.cpp166 case ADDR_TM_LINEAR_ALIGNED: in DispatchComputeSurfaceInfo()
612 case ADDR_TM_LINEAR_ALIGNED: in ComputeSurfaceAlignmentsLinear()
1313 case ADDR_TM_LINEAR_ALIGNED: in DispatchComputeSurfaceAddrFromCoord()
2060 case ADDR_TM_LINEAR_ALIGNED: in DispatchComputeSurfaceCoordFromAddr()
/external/mesa3d/src/amd/addrlib/core/
Daddrlib.cpp479 ADDR_ASSERT(localIn.tileMode == ADDR_TM_LINEAR_ALIGNED || localIn.height == 1); in ComputeSurfaceInfo()
3287 pIn->tileMode == ADDR_TM_LINEAR_ALIGNED) in HwlPreHandleBaseLvl3xPitch()
3318 pIn->tileMode == ADDR_TM_LINEAR_ALIGNED) in HwlPostHandleBaseLvl3xPitch()