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Searched refs:ADDiu (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsAnalyzeImmediate.cpp32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm)); in GetInstSeqLs()
89 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || in ReplaceADDiuSLLWithLUi()
131 ADDiu = Mips::ADDiu; in Analyze()
136 ADDiu = Mips::DADDiu; in Analyze()
DMipsAnalyzeImmediate.h58 unsigned ADDiu, ORi, SLL, LUi; variable
DMipsLongBranch.cpp298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
337 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
351 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
456 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp()
DMipsInstrInfo.td118 // target constant nodes that would otherwise remain unchanged with ADDiu
1673 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
2197 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
2200 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
2302 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
2304 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
2458 (ADDiu ZERO, imm:$in)>;
2477 (ADDiu GPR32:$src, imm:$imm)>, ASE_NOT_DSP;
2508 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
2509 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
[all …]
DMipsSEISelDAGToDAG.cpp92 if ((MI.getOpcode() == Mips::ADDiu) && in replaceUsesWithZeroReg()
173 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
189 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) in initGlobalBaseReg()
DMipsMCInstLower.cpp253 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu, MipsMCExpr::MEK_LO); in lowerLongBranch()
DMipsFastISel.cpp322 unsigned Opc = Mips::ADDiu; in materialize32BitInt()
381 emitInst(Mips::ADDiu, TempReg) in materializeGV()
704 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
705 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
DMipsSEInstrInfo.cpp443 unsigned ADDiu = ABI.GetPtrAddiuOp(); in adjustStackPtr() local
450 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); in adjustStackPtr()
DMipsSEFrameLowering.cpp392 unsigned ADDiu = ABI.GetPtrAddiuOp(); in emitPrologue() local
521 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign); in emitPrologue()
DMipsSEISelLowering.cpp2955 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) in emitBPOSGE32()
2961 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
3024 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) in emitMSACBranchPseudo()
3030 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
DMipsDSPInstrInfo.td1374 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1382 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
DMipsISelLowering.cpp1568 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) in emitAtomicCmpSwapPartword()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrInfo.td103 // target constant nodes that would otherwise remain unchanged with ADDiu
650 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
840 (ADDiu ZERO, imm:$in)>;
854 (ADDiu CPURegs:$src, imm:$imm)>;
867 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
868 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
870 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
872 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
875 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
877 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
[all …]
DMipsFrameLowering.cpp183 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) in emitPrologue()
300 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) in emitEpilogue()
DMipsISelLowering.cpp1015 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) in EmitAtomicBinaryPartword()
1243 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) in EmitAtomicCmpSwapPartword()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsABIInfo.cpp95 return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu; in GetPtrAddiuOp()
DMipsTargetStreamer.cpp1029 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad()
1107 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr), in emitDirectiveCpsetup()
1124 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr), in emitDirectiveCpsetup()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp1676 TOut.emitRRX(Mips::ADDiu, Mips::T9, Mips::T9, in processInstruction()
2042 case Mips::ADDiu: in tryExpandInstruction()
2199 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2431 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
2528 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3106 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDiv()
3110 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); in expandDiv()
3350 case (Mips::ADDiu): in expandAliasImmediate()