Searched refs:ADDlow (Results 1 – 4 of 4) sorted by relevance
/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.h | 38 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand. enumerator
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D | AArch64ISelDAGToDAG.cpp | 684 if (N.getOpcode() == AArch64ISD::ADDlow && isWorthFoldingADDlow(N)) { in SelectAddrModeIndexed() 2354 if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow || in SelectCVTFixedPosOperand()
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D | AArch64ISelLowering.cpp | 838 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow"; in getTargetNodeName() 3395 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); in LowerGlobalAddress() 4142 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); in LowerJumpTable() 4182 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); in LowerConstantPool() 4205 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); in LowerBlockAddress()
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D | AArch64InstrInfo.td | 147 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
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