Searched refs:AFGR64RegClass (Results 1 – 10 of 10) sorted by relevance
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()68 const MCRegisterClass *AFGR64RegClass; variable
188 for (RegIter Reg = Mips::AFGR64RegClass.begin(), in getReservedRegs()189 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) in getReservedRegs()
141 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()206 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()279 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
295 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()357 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()437 if (Mips::AFGR64RegClass.contains(Reg)) { in emitPrologue()
259 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize(); in printSavedRegsBitmask()272 } else if (Mips::AFGR64RegClass.contains(Reg)) { in printSavedRegsBitmask()
353 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; in materializeFP()749 ResultReg = createResultReg(&Mips::AFGR64RegClass); in emitLoad()964 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass); in selectFPExt()988 RC = &Mips::AFGR64RegClass; in selectSelect()
3485 if (RC == &Mips::AFGR64RegClass) { in parseRegForInlineAsmConstraint()3539 return std::make_pair(0U, &Mips::AFGR64RegClass); in getRegForInlineAsmConstraint()
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
87 AFGR64RegClass->contains(CurrentSubReg) || in SetPhysRegUsed()
132 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()