| /external/vixl/test/aarch32/ |
| D | test-simulator-cond-rd-rn-rm-a32-sel.cc | 451 __ Mrs(saved_q_bit, APSR); in TestHelper()
463 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
485 __ Mrs(nzcv_bits, APSR); in TestHelper()
493 __ Mrs(q_bit, APSR); in TestHelper()
501 __ Mrs(ge_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-a32-q.cc | 458 __ Mrs(saved_q_bit, APSR); in TestHelper()
470 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
492 __ Mrs(nzcv_bits, APSR); in TestHelper()
500 __ Mrs(q_bit, APSR); in TestHelper()
508 __ Mrs(ge_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32-sel.cc | 451 __ Mrs(saved_q_bit, APSR); in TestHelper()
463 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
485 __ Mrs(nzcv_bits, APSR); in TestHelper()
493 __ Mrs(q_bit, APSR); in TestHelper()
501 __ Mrs(ge_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32-q.cc | 458 __ Mrs(saved_q_bit, APSR); in TestHelper()
470 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
492 __ Mrs(nzcv_bits, APSR); in TestHelper()
500 __ Mrs(q_bit, APSR); in TestHelper()
508 __ Mrs(ge_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32-ge.cc | 474 __ Mrs(saved_q_bit, APSR); in TestHelper()
486 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
508 __ Mrs(nzcv_bits, APSR); in TestHelper()
516 __ Mrs(q_bit, APSR); in TestHelper()
524 __ Mrs(ge_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-a32-ge.cc | 474 __ Mrs(saved_q_bit, APSR); in TestHelper()
486 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
508 __ Mrs(nzcv_bits, APSR); in TestHelper()
516 __ Mrs(q_bit, APSR); in TestHelper()
524 __ Mrs(ge_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-operand-const-a32.cc | 539 __ Mrs(saved_q_bit, APSR); in TestHelper()
553 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-operand-imm16-t32.cc | 492 __ Mrs(saved_q_bit, APSR); in TestHelper()
506 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-operand-const-t32.cc | 654 __ Mrs(saved_q_bit, APSR); in TestHelper()
668 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-utils-aarch32.cc | 80 __ Mrs(tmp, APSR); in Dump()
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| D | test-simulator-cond-rd-operand-rn-a32.cc | 670 __ Mrs(saved_q_bit, APSR); in TestHelper()
685 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-t32.cc | 670 __ Mrs(saved_q_bit, APSR); in TestHelper()
685 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 749 __ Mrs(saved_q_bit, APSR); in TestHelper()
764 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 749 __ Mrs(saved_q_bit, APSR); in TestHelper()
764 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32.cc | 1560 __ Mrs(saved_q_bit, APSR); in TestHelper()
1572 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
1594 __ Mrs(nzcv_bits, APSR); in TestHelper()
1602 __ Mrs(q_bit, APSR); in TestHelper()
1610 __ Mrs(ge_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-a32.cc | 1562 __ Mrs(saved_q_bit, APSR); in TestHelper()
1574 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
1596 __ Mrs(nzcv_bits, APSR); in TestHelper()
1604 __ Mrs(q_bit, APSR); in TestHelper()
1612 __ Mrs(ge_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 939 __ Mrs(saved_q_bit, APSR); in TestHelper()
955 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 1053 __ Mrs(saved_q_bit, APSR); in TestHelper()
1068 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 1156 __ Mrs(saved_q_bit, APSR); in TestHelper()
1172 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 1043 __ Mrs(saved_q_bit, APSR); in TestHelper()
1058 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 1053 __ Mrs(saved_q_bit, APSR); in TestHelper()
1068 __ Mrs(nzcv_bits, APSR); in TestHelper()
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| /external/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 29 ; CHECK-THUMB: msr {{APSR|apsr}}_nzcvq, [[TMP]] @ encoding: [0x8{{[0-9a-f]}},0xf3,0x00,0x88]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 161 // models the APSR when it's accessed by some special instructions. In such cases
164 def APSR : ARMReg<1, "apsr">;
216 // GPRs without the PC but with APSR. Some instructions allow accessing the
217 // APSR, while actually encoding PC in the register field. This is useful
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.def | 104 // APSR's NZCV fields). For example, EQ is 0, but corresponds to Z = 1, and NE
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 210 case APSR: in GetName()
|