| /external/llvm/test/CodeGen/ARM/ |
| D | special-reg-acore.ll | 30 ; ACORE: msr APSR_nzcvq, r0
36 ; ACORE: msr APSR_nzcvq, r0
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| D | special-reg.ll | 55 ; ACORE: msr APSR_nzcvq, r0
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| D | copy-cpsr.ll | 24 ; CHECK-ARM: msr APSR_nzcvq, [[TMP]] @ encoding: [0x0{{[0-9a-f]}},0xf0,0x28,0xe1]
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| /external/vixl/test/aarch32/ |
| D | test-simulator-cond-rd-rn-rm-a32-sel.cc | 456 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
468 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-a32-q.cc | 463 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
475 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32-sel.cc | 456 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
468 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32-q.cc | 463 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
475 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32-ge.cc | 479 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
491 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-a32-ge.cc | 479 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
491 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
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| D | test-simulator-cond-rd-operand-const-a32.cc | 544 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-imm16-t32.cc | 497 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-const-t32.cc | 659 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-a32.cc | 675 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-t32.cc | 675 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 754 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 754 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 944 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 1058 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 1161 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 222 case APSR_nzcvq: in GetName()
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| D | instructions-aarch32.h | 838 APSR_nzcvq = 0x08, enumerator
848 CPSR_f = APSR_nzcvq,
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1428 msr APSR_nzcvq, #5
1440 msr APSR_nzcvq, #42, #2
1447 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1448 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1449 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1451 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1452 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1464 @ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3]
1474 msr APSR_nzcvq, r0
1486 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
[all …]
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 914 msr APSR_nzcvq, #5
926 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
928 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
929 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
944 msr APSR_nzcvq, r0
956 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
958 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
959 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 850 # CHECK: msr APSR_nzcvq, #5
851 # CHECK: msr APSR_nzcvq, #5
862 # CHECK: msr APSR_nzcvq, #2147483658
884 # CHECK: msr APSR_nzcvq, r0
885 # CHECK: msr APSR_nzcvq, r0
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 749 # CHECK: msr APSR_nzcvq, #5
750 # CHECK: msr APSR_nzcvq, #5
779 # CHECK: msr APSR_nzcvq, r0
780 # CHECK: msr APSR_nzcvq, r0
|