Searched refs:APSR_nzcvqg (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/test/CodeGen/ARM/ |
| D | msr-it-block.ll | 23 ; V7A: msr APSR_nzcvqg, {{r[0-9]+}}
24 ; V7A: msr APSR_nzcvqg, {{r[0-9]+}}
44 ; V7A: msr APSR_nzcvqg, {{r[0-9]+}}
45 ; V7A: msr APSR_nzcvqg, {{r[0-9]+}}
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| D | special-reg-acore.ll | 32 ; ACORE: msr APSR_nzcvqg, r0
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 226 case APSR_nzcvqg: in GetName()
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| D | instructions-aarch32.h | 840 APSR_nzcvqg = 0x0c, enumerator
852 CPSR_fs = APSR_nzcvqg,
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| D | macro-assembler-aarch32.cc | 897 Msr(APSR_nzcvqg, tmp); in Printf()
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1453 @ CHECK: msr APSR_nzcvqg, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
1463 @ CHECK: msr APSR_nzcvqg, #16711680 @ encoding: [0xff,0xf8,0x2c,0xe3]
1465 @ CHECK: msr APSR_nzcvqg, #2147483658 @ encoding: [0x2a,0xf1,0x2c,0xe3]
1490 @ CHECK: msr APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
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| D | basic-thumb2-instructions.s | 1579 @ CHECK: msr APSR_nzcvqg, r5 @ encoding: [0x85,0xf3,0x00,0x8c]
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| /external/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 2814 __ Msr(APSR_nzcvqg, 0); in TEST()
2816 __ Msr(APSR_nzcvqg, 0xffffffff); in TEST()
2869 __ Msr(APSR_nzcvqg, r0); in TEST()
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 751 # CHECK: msr APSR_nzcvqg, #5
781 # CHECK: msr APSR_nzcvqg, r0
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| D | thumb2.txt | 1005 # CHECK: msr APSR_nzcvqg, r5
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 852 # CHECK: msr APSR_nzcvqg, #5
886 # CHECK: msr APSR_nzcvqg, r0
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| D | thumb2.txt | 1122 # CHECK: msr APSR_nzcvqg, r5
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 930 @ CHECK: msr APSR_nzcvqg, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
960 @ CHECK: msr APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
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| D | basic-thumb2-instructions.s | 1195 @ CHECK: msr APSR_nzcvqg, r5 @ encoding: [0x85,0xf3,0x00,0x8c]
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