Searched refs:AR5K_SIMR2 (Results 1 – 3 of 3) sorted by relevance
353 AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN); in ath5k_hw_reset_tx_queue()354 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, in ath5k_hw_reset_tx_queue()
572 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2) in ath5k_hw_set_imr()605 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2); in ath5k_hw_set_imr()
430 #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ macro