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Searched refs:AddrSurfInfoOut (Results 1 – 2 of 2) sorted by relevance

/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c151 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut, in compute_level() argument
186 AddrSurfInfoOut); in compute_level()
192 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); in compute_level()
193 surf_level->slice_size = AddrSurfInfoOut->sliceSize; in compute_level()
194 surf_level->nblk_x = AddrSurfInfoOut->pitch; in compute_level()
195 surf_level->nblk_y = AddrSurfInfoOut->height; in compute_level()
197 switch (AddrSurfInfoOut->tileMode) { in compute_level()
212 surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex; in compute_level()
214 surf->tiling_index[level] = AddrSurfInfoOut->tileIndex; in compute_level()
216 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize; in compute_level()
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/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c165 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut, in radv_compute_level() argument
198 AddrSurfInfoOut); in radv_compute_level()
203 surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign); in radv_compute_level()
204 surf_level->slice_size = AddrSurfInfoOut->sliceSize; in radv_compute_level()
205 surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe); in radv_compute_level()
209 surf_level->nblk_x = AddrSurfInfoOut->pitch; in radv_compute_level()
210 surf_level->nblk_y = AddrSurfInfoOut->height; in radv_compute_level()
212 surf_level->nblk_z = AddrSurfInfoOut->depth; in radv_compute_level()
216 switch (AddrSurfInfoOut->tileMode) { in radv_compute_level()
231 surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex; in radv_compute_level()
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