| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenCallingConv.inc | 134 if (unsigned Reg = State.AllocateReg(X86::ECX)) {
146 if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
178 if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
192 if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
229 if (unsigned Reg = State.AllocateReg(RegList6, 4)) {
247 if (unsigned Reg = State.AllocateReg(RegList7, 4)) {
308 if (unsigned Reg = State.AllocateReg(X86::EAX)) {
318 if (unsigned Reg = State.AllocateReg(RegList1, 2)) {
331 if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
368 if (unsigned Reg = State.AllocateReg(X86::EAX)) {
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
49 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS()
83 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
102 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
216 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
256 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
267 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate()
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| D | ARMISelLowering.cpp | 1993 unsigned Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2000 Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2013 while (State->AllocateReg(GPRArgRegs)) in HandleByVal()
2030 State->AllocateReg(GPRArgRegs); in HandleByVal()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMCallingConv.h | 35 if (unsigned Reg = State.AllocateReg(RegList, 4)) in f64AssignAPCS()
50 if (unsigned Reg = State.AllocateReg(RegList, 4)) in f64AssignAPCS()
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); in f64AssignAAPCS()
97 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
124 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); in f64RetAssign()
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| D | ARMISelLowering.cpp | 1562 unsigned reg = State->AllocateReg(GPRArgRegs, 4); in HandleByVal()
1581 while (State->AllocateReg(GPRArgRegs, 4)) in HandleByVal()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 242 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function
249 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function
259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() function
271 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg() function
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| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.h | 72 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
93 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 342 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function
349 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function
359 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() function
400 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg() function
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.h | 111 unsigned Reg = State.AllocateReg(SystemZ::ArgGPRs); in CC_SystemZ_I128Indirect()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 128 State.AllocateReg(Reg); in CC_AArch64_Custom_Block()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 678 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
679 CCInfo.AllocateReg(AMDGPU::VGPR1); in LowerFormalArguments()
702 CCInfo.AllocateReg(PrivateSegmentBufferReg); in LowerFormalArguments()
708 CCInfo.AllocateReg(DispatchPtrReg); in LowerFormalArguments()
714 CCInfo.AllocateReg(QueuePtrReg); in LowerFormalArguments()
720 CCInfo.AllocateReg(InputPtrReg); in LowerFormalArguments()
726 CCInfo.AllocateReg(FlatScratchInitReg); in LowerFormalArguments()
823 CCInfo.AllocateReg(Reg); in LowerFormalArguments()
829 CCInfo.AllocateReg(Reg); in LowerFormalArguments()
835 CCInfo.AllocateReg(Reg); in LowerFormalArguments()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1746 State.AllocateReg(IntRegs[r]); in CC_MipsO32()
1772 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1776 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1781 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1783 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1784 State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1789 Reg = State.AllocateReg(F32Regs, FloatRegsSize); in CC_MipsO32()
1791 State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1793 Reg = State.AllocateReg(F64Regs, FloatRegsSize); in CC_MipsO32()
1795 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 280 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Hexagon32()
294 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { in CC_Hexagon64()
305 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { in CC_Hexagon64()
339 if (unsigned Reg = State.AllocateReg(VecLstS)) { in CC_HexagonVector()
350 if (unsigned Reg = State.AllocateReg(VecLstD)) { in CC_HexagonVector()
362 if (unsigned Reg = State.AllocateReg(VecLstD)) { in CC_HexagonVector()
373 if (unsigned Reg = State.AllocateReg(VecLstS)) { in CC_HexagonVector()
450 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) { in RetCC_Hexagon32()
465 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { in RetCC_Hexagon64()
486 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) { in RetCC_HexagonVector()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2498 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2502 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2507 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2509 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2510 State.AllocateReg(IntRegs); in CC_MipsO32()
2515 Reg = State.AllocateReg(F32Regs); in CC_MipsO32()
2517 State.AllocateReg(IntRegs); in CC_MipsO32()
2519 Reg = State.AllocateReg(F64Regs); in CC_MipsO32()
2521 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32()
2523 State.AllocateReg(IntRegs); in CC_MipsO32()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 58 if (unsigned Reg = State.AllocateReg(RegList, 6)) { in CC_Sparc_Assign_f64()
69 if (unsigned Reg = State.AllocateReg(RegList, 6)) in CC_Sparc_Assign_f64()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 60 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
71 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
89 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
95 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 665 unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs); in CC_MBlaze_AssignReg()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 323 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1546 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignArgRegs()
1572 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignFPArgRegs()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2686 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
2712 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
|