Searched refs:Amt1 (Results 1 – 4 of 4) sorted by relevance
| /external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
| D | rotl-64.ll | 13 %Amt1 = zext i8 %Amt to i64
14 %tmp1 = lshr i64 %A, %Amt1
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | rotl-64.ll | 13 %Amt1 = zext i8 %Amt to i64
14 %tmp1 = lshr i64 %A, %Amt1
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 20047 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1}); in LowerShift() local
20049 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1); in LowerShift()
20125 SDValue Amt1 = Amt->getOperand(0); in LowerShift() local
20137 CanBeSimplified = Amt1 == Amt->getOperand(1) && in LowerShift()
20145 CanBeSimplified = Amt1 == Amt->getOperand(1); in LowerShift()
20154 CanBeSimplified = Amt1 == Amt->getOperand(i); in LowerShift()
20160 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) && in LowerShift()
20165 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT); in LowerShift()
20187 SDValue Amt0, Amt1, Amt2, Amt3; in LowerShift() local
20190 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1}); in LowerShift()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 9896 SDValue Amt1, Amt2; in LowerShift() local
9906 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, in LowerShift()
9912 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); in LowerShift()
9918 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); in LowerShift()
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