| /external/valgrind/VEX/priv/ |
| D | host_arm_defs.c | 2820 #define BITS4(zzb3,zzb2,zzb1,zzb0) \ macro
2822 #define X0000 BITS4(0,0,0,0)
2823 #define X0001 BITS4(0,0,0,1)
2824 #define X0010 BITS4(0,0,1,0)
2825 #define X0011 BITS4(0,0,1,1)
2826 #define X0100 BITS4(0,1,0,0)
2827 #define X0101 BITS4(0,1,0,1)
2828 #define X0110 BITS4(0,1,1,0)
2829 #define X0111 BITS4(0,1,1,1)
2830 #define X1000 BITS4(1,0,0,0)
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| D | guest_arm_toIR.c | 245 #define BITS4(_b3,_b2,_b1,_b0) \ macro
249 ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \
250 | BITS4((_b3),(_b2),(_b1),(_b0)))
5318 if ((INSN(11,8) & BITS4(1,0,1,0)) == BITS4(0,0,0,0)) { in dis_neon_data_2reg_and_scalar()
5424 if ((INSN(11,8) & BITS4(1,0,1,1)) == BITS4(0,0,1,0)) { in dis_neon_data_2reg_and_scalar()
5481 if ((INSN(11,8) & BITS4(1,0,1,1)) == BITS4(0,0,1,1) && !U) { in dis_neon_data_2reg_and_scalar()
5555 if ((INSN(11,8) & BITS4(1,1,1,0)) == BITS4(1,0,0,0)) { in dis_neon_data_2reg_and_scalar()
5652 if (INSN(11,8) == BITS4(1,0,1,0)) { in dis_neon_data_2reg_and_scalar()
5696 if (INSN(11,8) == BITS4(1,0,1,1) && !U) { in dis_neon_data_2reg_and_scalar()
5759 if (INSN(11,8) == BITS4(1,1,0,0)) { in dis_neon_data_2reg_and_scalar()
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| D | guest_arm64_toIR.c | 199 #define BITS4(_b3,_b2,_b1,_b0) \ macro
203 ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \
204 | BITS4((_b3),(_b2),(_b1),(_b0)))
3391 && INSN(15,12) == BITS4(0,0,1,0)) { in dis_ARM64_data_processing_register()
4594 case BITS4(1,1,1,0): goto fail; //ATC in gen_indexed_EA()
4595 case BITS4(0,1,1,0): in gen_indexed_EA()
4600 case BITS4(1,1,1,1): goto fail; //ATC in gen_indexed_EA()
4601 case BITS4(0,1,1,1): in gen_indexed_EA()
4606 case BITS4(0,1,0,0): in gen_indexed_EA()
4611 case BITS4(0,1,0,1): in gen_indexed_EA()
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| D | host_arm64_defs.c | 2654 #define BITS4(zzb3,zzb2,zzb1,zzb0) \ macro
2657 #define X00 BITS4(0,0, 0,0)
2658 #define X01 BITS4(0,0, 0,1)
2659 #define X10 BITS4(0,0, 1,0)
2660 #define X11 BITS4(0,0, 1,1)
2662 #define X000 BITS4(0, 0,0,0)
2663 #define X001 BITS4(0, 0,0,1)
2664 #define X010 BITS4(0, 0,1,0)
2665 #define X011 BITS4(0, 0,1,1)
2666 #define X100 BITS4(0, 1,0,0)
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| D | guest_mips_toIR.c | 449 #define BITS4(_b3,_b2,_b1,_b0) \ macro
453 (((_b4) << 4) | BITS4((_b3),(_b2),(_b1),(_b0)))
457 | BITS4((_b3),(_b2),(_b1),(_b0)))
460 ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \
461 | BITS4((_b3),(_b2),(_b1),(_b0)))
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