| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_vec4_live_variables.cpp | 83 BITSET_SET(bd->use, v); in setup_def_use()
91 BITSET_SET(bd->flag_use, c); in setup_def_use()
106 BITSET_SET(bd->def, v); in setup_def_use()
115 BITSET_SET(bd->flag_def, c); in setup_def_use()
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| D | brw_vec4_dead_code_eliminate.cpp | 139 BITSET_SET(live, v); in dead_code_eliminate()
147 BITSET_SET(flag_live, c); in dead_code_eliminate()
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| D | brw_fs_live_variables.cpp | 70 BITSET_SET(bd->use, var); in setup_one_read()
88 BITSET_SET(bd->def, var); in setup_one_write()
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| D | brw_fs_dead_code_eliminate.cpp | 132 BITSET_SET(live, var + j); in dead_code_eliminate()
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| D | brw_schedule_instructions.cpp | 639 BITSET_SET(livein[block], vgrf); in setup_liveness()
644 BITSET_SET(liveout[block], v->live_intervals->vgrf_from_var[i]); in setup_liveness()
658 BITSET_SET(livein[block + 1], i); in setup_liveness()
661 BITSET_SET(liveout[block], i); in setup_liveness()
678 BITSET_SET(hw_liveout[block], i); in setup_liveness()
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| D | brw_fs_copy_propagation.cpp | 136 BITSET_SET(bd[block->num].copy, next_acp); in fs_copy_prop_dataflow()
168 BITSET_SET(bd[block->num].kill, i); in setup_initial_values()
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| /external/mesa3d/src/compiler/nir/ |
| D | nir_worklist.c | 75 BITSET_SET(w->blocks_present, block->index); in nir_block_worklist_push_head()
114 BITSET_SET(w->blocks_present, block->index); in nir_block_worklist_push_tail()
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| D | nir_repair_ssa.c | 85 BITSET_SET(state->def_set, def->parent_instr->block->index); in repair_ssa_def()
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| D | nir_liveness.c | 96 BITSET_SET(live, src->ssa->live_index); in set_src_live()
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| D | nir_lower_regs_to_ssa.c | 245 BITSET_SET(defs, dest->reg.parent_instr->block->index); in nir_lower_regs_to_ssa_impl()
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| D | nir_lower_vars_to_ssa.c | 717 BITSET_SET(store_blocks, store->instr.block->index); in nir_lower_vars_to_ssa_impl()
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| D | nir_validate.c | 290 BITSET_SET(state->ssa_defs_found, def->index); in validate_ssa_def()
862 BITSET_SET(state->regs_found, reg->index); in prevalidate_reg_decl()
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| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| D | nouveau_context.h | 104 BITSET_SET(to_nouveau_context(ctx)->dirty, NOUVEAU_STATE_##s)
106 BITSET_SET(to_nouveau_context(ctx)->dirty, NOUVEAU_STATE_##s##0 + i)
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| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qir_live_variables.c | 74 BITSET_SET(block->use, var); in qir_setup_use()
127 BITSET_SET(block->def, var); in qir_setup_def()
170 BITSET_SET(block->def, var); in qir_setup_def()
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| D | vc4_qir_schedule.c | 679 BITSET_SET(state->temp_live, inst->src[i].index); in schedule_instructions()
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| /external/mesa3d/src/util/ |
| D | register_allocate.c | 198 BITSET_SET(regs->regs[i].conflicts, i); in ra_alloc_reg_set()
244 BITSET_SET(reg1->conflicts, r2); in ra_add_conflict_list()
322 BITSET_SET(class->regs, r); in ra_class_add_reg()
393 BITSET_SET(g->nodes[n1].adjacency, n2); in ra_add_node_adjacency()
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| D | bitset.h | 61 #define BITSET_SET(x, b) ((x)[BITSET_BITWORD(b)] |= BITSET_BIT(b)) macro
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| /external/mesa3d/src/compiler/glsl/ |
| D | ir_array_refcount.cpp | 124 BITSET_SET(bits, linearized_index); in mark_array_elements_referenced()
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| /external/mesa3d/src/mesa/main/ |
| D | performance_monitor.c | 511 BITSET_SET(m->ActiveCounters[group], counterList[i]); in _mesa_SelectPerfMonitorCountersAMD()
1071 BITSET_SET(m->ActiveCounters[group], i); in _mesa_CreatePerfQueryINTEL()
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| D | texstate.c | 592 BITSET_SET(enabled_texture_units, unit); in update_program_texture_state()
676 BITSET_SET(enabled_texture_units, unit); in update_ff_texture_state()
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| /external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| D | ir3_ra.c | 617 BITSET_SET(bd->def, name); \ in ra_block_compute_live_ranges()
624 BITSET_SET(bd->use, name); \ in ra_block_compute_live_ranges()
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| /external/mesa3d/src/intel/vulkan/ |
| D | anv_nir_apply_pipeline_layout.c | 47 BITSET_SET(state->set[set].used, binding); in add_binding()
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| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | fd5_program.c | 467 BITSET_SET(varbs, l.var[i].loc + j); in fd5_program_emit()
|