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1 /*
2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3  Intel funded Tungsten Graphics to
4  develop this 3D driver.
5 
6  Permission is hereby granted, free of charge, to any person obtaining
7  a copy of this software and associated documentation files (the
8  "Software"), to deal in the Software without restriction, including
9  without limitation the rights to use, copy, modify, merge, publish,
10  distribute, sublicense, and/or sell copies of the Software, and to
11  permit persons to whom the Software is furnished to do so, subject to
12  the following conditions:
13 
14  The above copyright notice and this permission notice (including the
15  next paragraph) shall be included in all copies or substantial
16  portions of the Software.
17 
18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 
26  **********************************************************************/
27  /*
28   * Authors:
29   *   Keith Whitwell <keithw@vmware.com>
30   */
31 
32 #ifndef BRW_DEFINES_H
33 #define BRW_DEFINES_H
34 
35 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
36 /* Using the GNU statement expression extension */
37 #define SET_FIELD(value, field)                                         \
38    ({                                                                   \
39       uint32_t fieldval = (value) << field ## _SHIFT;                   \
40       assert((fieldval & ~ field ## _MASK) == 0);                       \
41       fieldval & field ## _MASK;                                        \
42    })
43 
44 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
45 #define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
46 
47 /**
48  * For use with masked MMIO registers where the upper 16 bits control which
49  * of the lower bits are committed to the register.
50  */
51 #define REG_MASK(value) ((value) << 16)
52 
53 /* 3D state:
54  */
55 #define CMD_3D_PRIM                                 0x7b00 /* 3DPRIMITIVE */
56 /* DW0 */
57 # define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT            10
58 # define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 15)
59 # define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM     (1 << 15)
60 # define GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE      (1 << 10)
61 # define GEN7_3DPRIM_PREDICATE_ENABLE               (1 << 8)
62 /* DW1 */
63 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8)
64 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM     (1 << 8)
65 
66 #define _3DPRIM_POINTLIST         0x01
67 #define _3DPRIM_LINELIST          0x02
68 #define _3DPRIM_LINESTRIP         0x03
69 #define _3DPRIM_TRILIST           0x04
70 #define _3DPRIM_TRISTRIP          0x05
71 #define _3DPRIM_TRIFAN            0x06
72 #define _3DPRIM_QUADLIST          0x07
73 #define _3DPRIM_QUADSTRIP         0x08
74 #define _3DPRIM_LINELIST_ADJ      0x09 /* G45+ */
75 #define _3DPRIM_LINESTRIP_ADJ     0x0A /* G45+ */
76 #define _3DPRIM_TRILIST_ADJ       0x0B /* G45+ */
77 #define _3DPRIM_TRISTRIP_ADJ      0x0C /* G45+ */
78 #define _3DPRIM_TRISTRIP_REVERSE  0x0D
79 #define _3DPRIM_POLYGON           0x0E
80 #define _3DPRIM_RECTLIST          0x0F
81 #define _3DPRIM_LINELOOP          0x10
82 #define _3DPRIM_POINTLIST_BF      0x11
83 #define _3DPRIM_LINESTRIP_CONT    0x12
84 #define _3DPRIM_LINESTRIP_BF      0x13
85 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
86 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
87 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
88 
89 
90 /* We use this offset to be able to pass native primitive types in struct
91  * _mesa_prim::mode.  Native primitive types are BRW_PRIM_OFFSET +
92  * native_type, which should be different from all GL types and still fit in
93  * the 8 bits avialable. */
94 
95 #define BRW_PRIM_OFFSET           0x80
96 
97 #define BRW_ANISORATIO_2     0
98 #define BRW_ANISORATIO_4     1
99 #define BRW_ANISORATIO_6     2
100 #define BRW_ANISORATIO_8     3
101 #define BRW_ANISORATIO_10    4
102 #define BRW_ANISORATIO_12    5
103 #define BRW_ANISORATIO_14    6
104 #define BRW_ANISORATIO_16    7
105 
106 #define BRW_BLENDFACTOR_ONE                 0x1
107 #define BRW_BLENDFACTOR_SRC_COLOR           0x2
108 #define BRW_BLENDFACTOR_SRC_ALPHA           0x3
109 #define BRW_BLENDFACTOR_DST_ALPHA           0x4
110 #define BRW_BLENDFACTOR_DST_COLOR           0x5
111 #define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE  0x6
112 #define BRW_BLENDFACTOR_CONST_COLOR         0x7
113 #define BRW_BLENDFACTOR_CONST_ALPHA         0x8
114 #define BRW_BLENDFACTOR_SRC1_COLOR          0x9
115 #define BRW_BLENDFACTOR_SRC1_ALPHA          0x0A
116 #define BRW_BLENDFACTOR_ZERO                0x11
117 #define BRW_BLENDFACTOR_INV_SRC_COLOR       0x12
118 #define BRW_BLENDFACTOR_INV_SRC_ALPHA       0x13
119 #define BRW_BLENDFACTOR_INV_DST_ALPHA       0x14
120 #define BRW_BLENDFACTOR_INV_DST_COLOR       0x15
121 #define BRW_BLENDFACTOR_INV_CONST_COLOR     0x17
122 #define BRW_BLENDFACTOR_INV_CONST_ALPHA     0x18
123 #define BRW_BLENDFACTOR_INV_SRC1_COLOR      0x19
124 #define BRW_BLENDFACTOR_INV_SRC1_ALPHA      0x1A
125 
126 #define BRW_BLENDFUNCTION_ADD               0
127 #define BRW_BLENDFUNCTION_SUBTRACT          1
128 #define BRW_BLENDFUNCTION_REVERSE_SUBTRACT  2
129 #define BRW_BLENDFUNCTION_MIN               3
130 #define BRW_BLENDFUNCTION_MAX               4
131 
132 #define BRW_ALPHATEST_FORMAT_UNORM8         0
133 #define BRW_ALPHATEST_FORMAT_FLOAT32        1
134 
135 #define BRW_CHROMAKEY_KILL_ON_ANY_MATCH  0
136 #define BRW_CHROMAKEY_REPLACE_BLACK      1
137 
138 #define BRW_CLIP_API_OGL     0
139 #define BRW_CLIP_API_DX      1
140 
141 #define BRW_CLIPMODE_NORMAL              0
142 #define BRW_CLIPMODE_CLIP_ALL            1
143 #define BRW_CLIPMODE_CLIP_NON_REJECTED   2
144 #define BRW_CLIPMODE_REJECT_ALL          3
145 #define BRW_CLIPMODE_ACCEPT_ALL          4
146 #define BRW_CLIPMODE_KERNEL_CLIP         5
147 
148 #define BRW_CLIP_NDCSPACE     0
149 #define BRW_CLIP_SCREENSPACE  1
150 
151 #define BRW_COMPAREFUNCTION_ALWAYS       0
152 #define BRW_COMPAREFUNCTION_NEVER        1
153 #define BRW_COMPAREFUNCTION_LESS         2
154 #define BRW_COMPAREFUNCTION_EQUAL        3
155 #define BRW_COMPAREFUNCTION_LEQUAL       4
156 #define BRW_COMPAREFUNCTION_GREATER      5
157 #define BRW_COMPAREFUNCTION_NOTEQUAL     6
158 #define BRW_COMPAREFUNCTION_GEQUAL       7
159 
160 #define BRW_COVERAGE_PIXELS_HALF     0
161 #define BRW_COVERAGE_PIXELS_1        1
162 #define BRW_COVERAGE_PIXELS_2        2
163 #define BRW_COVERAGE_PIXELS_4        3
164 
165 #define BRW_CULLMODE_BOTH        0
166 #define BRW_CULLMODE_NONE        1
167 #define BRW_CULLMODE_FRONT       2
168 #define BRW_CULLMODE_BACK        3
169 
170 #define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM      0
171 #define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT  1
172 
173 #define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT     0
174 #define BRW_DEPTHFORMAT_D32_FLOAT                1
175 #define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT        2
176 #define BRW_DEPTHFORMAT_D24_UNORM_X8_UINT        3 /* GEN5 */
177 #define BRW_DEPTHFORMAT_D16_UNORM                5
178 
179 #define BRW_FLOATING_POINT_IEEE_754        0
180 #define BRW_FLOATING_POINT_NON_IEEE_754    1
181 
182 #define BRW_FRONTWINDING_CW      0
183 #define BRW_FRONTWINDING_CCW     1
184 
185 #define BRW_SPRITE_POINT_ENABLE  16
186 
187 #define BRW_CUT_INDEX_ENABLE     (1 << 10)
188 
189 #define BRW_INDEX_BYTE     0
190 #define BRW_INDEX_WORD     1
191 #define BRW_INDEX_DWORD    2
192 
193 #define BRW_LOGICOPFUNCTION_CLEAR            0
194 #define BRW_LOGICOPFUNCTION_NOR              1
195 #define BRW_LOGICOPFUNCTION_AND_INVERTED     2
196 #define BRW_LOGICOPFUNCTION_COPY_INVERTED    3
197 #define BRW_LOGICOPFUNCTION_AND_REVERSE      4
198 #define BRW_LOGICOPFUNCTION_INVERT           5
199 #define BRW_LOGICOPFUNCTION_XOR              6
200 #define BRW_LOGICOPFUNCTION_NAND             7
201 #define BRW_LOGICOPFUNCTION_AND              8
202 #define BRW_LOGICOPFUNCTION_EQUIV            9
203 #define BRW_LOGICOPFUNCTION_NOOP             10
204 #define BRW_LOGICOPFUNCTION_OR_INVERTED      11
205 #define BRW_LOGICOPFUNCTION_COPY             12
206 #define BRW_LOGICOPFUNCTION_OR_REVERSE       13
207 #define BRW_LOGICOPFUNCTION_OR               14
208 #define BRW_LOGICOPFUNCTION_SET              15
209 
210 #define BRW_MAPFILTER_NEAREST        0x0
211 #define BRW_MAPFILTER_LINEAR         0x1
212 #define BRW_MAPFILTER_ANISOTROPIC    0x2
213 
214 #define BRW_MIPFILTER_NONE        0
215 #define BRW_MIPFILTER_NEAREST     1
216 #define BRW_MIPFILTER_LINEAR      3
217 
218 #define BRW_ADDRESS_ROUNDING_ENABLE_U_MAG	0x20
219 #define BRW_ADDRESS_ROUNDING_ENABLE_U_MIN	0x10
220 #define BRW_ADDRESS_ROUNDING_ENABLE_V_MAG	0x08
221 #define BRW_ADDRESS_ROUNDING_ENABLE_V_MIN	0x04
222 #define BRW_ADDRESS_ROUNDING_ENABLE_R_MAG	0x02
223 #define BRW_ADDRESS_ROUNDING_ENABLE_R_MIN	0x01
224 
225 #define BRW_POLYGON_FRONT_FACING     0
226 #define BRW_POLYGON_BACK_FACING      1
227 
228 #define BRW_PREFILTER_ALWAYS     0x0
229 #define BRW_PREFILTER_NEVER      0x1
230 #define BRW_PREFILTER_LESS       0x2
231 #define BRW_PREFILTER_EQUAL      0x3
232 #define BRW_PREFILTER_LEQUAL     0x4
233 #define BRW_PREFILTER_GREATER    0x5
234 #define BRW_PREFILTER_NOTEQUAL   0x6
235 #define BRW_PREFILTER_GEQUAL     0x7
236 
237 #define BRW_PROVOKING_VERTEX_0    0
238 #define BRW_PROVOKING_VERTEX_1    1
239 #define BRW_PROVOKING_VERTEX_2    2
240 
241 #define BRW_RASTRULE_UPPER_LEFT  0
242 #define BRW_RASTRULE_UPPER_RIGHT 1
243 /* These are listed as "Reserved, but not seen as useful"
244  * in Intel documentation (page 212, "Point Rasterization Rule",
245  * section 7.4 "SF Pipeline State Summary", of document
246  * "Intel® 965 Express Chipset Family and Intel® G35 Express
247  * Chipset Graphics Controller Programmer's Reference Manual,
248  * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
249  * available at
250  *     https://01.org/linuxgraphics/documentation/hardware-specification-prms
251  * at the time of this writing).
252  *
253  * These appear to be supported on at least some
254  * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT
255  * is useful when using OpenGL to render to a FBO
256  * (which has the pixel coordinate Y orientation inverted
257  * with respect to the normal OpenGL pixel coordinate system).
258  */
259 #define BRW_RASTRULE_LOWER_LEFT  2
260 #define BRW_RASTRULE_LOWER_RIGHT 3
261 
262 #define BRW_RENDERTARGET_CLAMPRANGE_UNORM    0
263 #define BRW_RENDERTARGET_CLAMPRANGE_SNORM    1
264 #define BRW_RENDERTARGET_CLAMPRANGE_FORMAT   2
265 
266 #define BRW_STENCILOP_KEEP               0
267 #define BRW_STENCILOP_ZERO               1
268 #define BRW_STENCILOP_REPLACE            2
269 #define BRW_STENCILOP_INCRSAT            3
270 #define BRW_STENCILOP_DECRSAT            4
271 #define BRW_STENCILOP_INCR               5
272 #define BRW_STENCILOP_DECR               6
273 #define BRW_STENCILOP_INVERT             7
274 
275 /* Surface state DW0 */
276 #define GEN8_SURFACE_IS_ARRAY                       (1 << 28)
277 #define GEN8_SURFACE_VALIGN_4                       (1 << 16)
278 #define GEN8_SURFACE_VALIGN_8                       (2 << 16)
279 #define GEN8_SURFACE_VALIGN_16                      (3 << 16)
280 #define GEN8_SURFACE_HALIGN_4                       (1 << 14)
281 #define GEN8_SURFACE_HALIGN_8                       (2 << 14)
282 #define GEN8_SURFACE_HALIGN_16                      (3 << 14)
283 #define GEN8_SURFACE_TILING_NONE                    (0 << 12)
284 #define GEN8_SURFACE_TILING_W                       (1 << 12)
285 #define GEN8_SURFACE_TILING_X                       (2 << 12)
286 #define GEN8_SURFACE_TILING_Y                       (3 << 12)
287 #define GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE      (1 << 9)
288 #define BRW_SURFACE_RC_READ_WRITE	(1 << 8)
289 #define BRW_SURFACE_MIPLAYOUT_SHIFT	10
290 #define BRW_SURFACE_MIPMAPLAYOUT_BELOW   0
291 #define BRW_SURFACE_MIPMAPLAYOUT_RIGHT   1
292 #define BRW_SURFACE_CUBEFACE_ENABLES	0x3f
293 #define BRW_SURFACE_BLEND_ENABLED	(1 << 13)
294 #define BRW_SURFACE_WRITEDISABLE_B_SHIFT	14
295 #define BRW_SURFACE_WRITEDISABLE_G_SHIFT	15
296 #define BRW_SURFACE_WRITEDISABLE_R_SHIFT	16
297 #define BRW_SURFACE_WRITEDISABLE_A_SHIFT	17
298 
299 #define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT             0x000
300 #define BRW_SURFACEFORMAT_R32G32B32A32_SINT              0x001
301 #define BRW_SURFACEFORMAT_R32G32B32A32_UINT              0x002
302 #define BRW_SURFACEFORMAT_R32G32B32A32_UNORM             0x003
303 #define BRW_SURFACEFORMAT_R32G32B32A32_SNORM             0x004
304 #define BRW_SURFACEFORMAT_R64G64_FLOAT                   0x005
305 #define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT             0x006
306 #define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED           0x007
307 #define BRW_SURFACEFORMAT_R32G32B32A32_USCALED           0x008
308 #define BRW_SURFACEFORMAT_R32G32B32A32_SFIXED            0x020
309 #define BRW_SURFACEFORMAT_R64G64_PASSTHRU                0x021
310 #define BRW_SURFACEFORMAT_R32G32B32_FLOAT                0x040
311 #define BRW_SURFACEFORMAT_R32G32B32_SINT                 0x041
312 #define BRW_SURFACEFORMAT_R32G32B32_UINT                 0x042
313 #define BRW_SURFACEFORMAT_R32G32B32_UNORM                0x043
314 #define BRW_SURFACEFORMAT_R32G32B32_SNORM                0x044
315 #define BRW_SURFACEFORMAT_R32G32B32_SSCALED              0x045
316 #define BRW_SURFACEFORMAT_R32G32B32_USCALED              0x046
317 #define BRW_SURFACEFORMAT_R32G32B32_SFIXED               0x050
318 #define BRW_SURFACEFORMAT_R16G16B16A16_UNORM             0x080
319 #define BRW_SURFACEFORMAT_R16G16B16A16_SNORM             0x081
320 #define BRW_SURFACEFORMAT_R16G16B16A16_SINT              0x082
321 #define BRW_SURFACEFORMAT_R16G16B16A16_UINT              0x083
322 #define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT             0x084
323 #define BRW_SURFACEFORMAT_R32G32_FLOAT                   0x085
324 #define BRW_SURFACEFORMAT_R32G32_SINT                    0x086
325 #define BRW_SURFACEFORMAT_R32G32_UINT                    0x087
326 #define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS       0x088
327 #define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT        0x089
328 #define BRW_SURFACEFORMAT_L32A32_FLOAT                   0x08A
329 #define BRW_SURFACEFORMAT_R32G32_UNORM                   0x08B
330 #define BRW_SURFACEFORMAT_R32G32_SNORM                   0x08C
331 #define BRW_SURFACEFORMAT_R64_FLOAT                      0x08D
332 #define BRW_SURFACEFORMAT_R16G16B16X16_UNORM             0x08E
333 #define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT             0x08F
334 #define BRW_SURFACEFORMAT_A32X32_FLOAT                   0x090
335 #define BRW_SURFACEFORMAT_L32X32_FLOAT                   0x091
336 #define BRW_SURFACEFORMAT_I32X32_FLOAT                   0x092
337 #define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED           0x093
338 #define BRW_SURFACEFORMAT_R16G16B16A16_USCALED           0x094
339 #define BRW_SURFACEFORMAT_R32G32_SSCALED                 0x095
340 #define BRW_SURFACEFORMAT_R32G32_USCALED                 0x096
341 #define BRW_SURFACEFORMAT_R32G32_FLOAT_LD                0x097
342 #define BRW_SURFACEFORMAT_R32G32_SFIXED                  0x0A0
343 #define BRW_SURFACEFORMAT_R64_PASSTHRU                   0x0A1
344 #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM                 0x0C0
345 #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB            0x0C1
346 #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM              0x0C2
347 #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB         0x0C3
348 #define BRW_SURFACEFORMAT_R10G10B10A2_UINT               0x0C4
349 #define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM       0x0C5
350 #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM                 0x0C7
351 #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB            0x0C8
352 #define BRW_SURFACEFORMAT_R8G8B8A8_SNORM                 0x0C9
353 #define BRW_SURFACEFORMAT_R8G8B8A8_SINT                  0x0CA
354 #define BRW_SURFACEFORMAT_R8G8B8A8_UINT                  0x0CB
355 #define BRW_SURFACEFORMAT_R16G16_UNORM                   0x0CC
356 #define BRW_SURFACEFORMAT_R16G16_SNORM                   0x0CD
357 #define BRW_SURFACEFORMAT_R16G16_SINT                    0x0CE
358 #define BRW_SURFACEFORMAT_R16G16_UINT                    0x0CF
359 #define BRW_SURFACEFORMAT_R16G16_FLOAT                   0x0D0
360 #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM              0x0D1
361 #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB         0x0D2
362 #define BRW_SURFACEFORMAT_R11G11B10_FLOAT                0x0D3
363 #define BRW_SURFACEFORMAT_R32_SINT                       0x0D6
364 #define BRW_SURFACEFORMAT_R32_UINT                       0x0D7
365 #define BRW_SURFACEFORMAT_R32_FLOAT                      0x0D8
366 #define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS          0x0D9
367 #define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT           0x0DA
368 #define BRW_SURFACEFORMAT_L16A16_UNORM                   0x0DF
369 #define BRW_SURFACEFORMAT_I24X8_UNORM                    0x0E0
370 #define BRW_SURFACEFORMAT_L24X8_UNORM                    0x0E1
371 #define BRW_SURFACEFORMAT_A24X8_UNORM                    0x0E2
372 #define BRW_SURFACEFORMAT_I32_FLOAT                      0x0E3
373 #define BRW_SURFACEFORMAT_L32_FLOAT                      0x0E4
374 #define BRW_SURFACEFORMAT_A32_FLOAT                      0x0E5
375 #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM                 0x0E9
376 #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB            0x0EA
377 #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM                 0x0EB
378 #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB            0x0EC
379 #define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP             0x0ED
380 #define BRW_SURFACEFORMAT_B10G10R10X2_UNORM              0x0EE
381 #define BRW_SURFACEFORMAT_L16A16_FLOAT                   0x0F0
382 #define BRW_SURFACEFORMAT_R32_UNORM                      0x0F1
383 #define BRW_SURFACEFORMAT_R32_SNORM                      0x0F2
384 #define BRW_SURFACEFORMAT_R10G10B10X2_USCALED            0x0F3
385 #define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED               0x0F4
386 #define BRW_SURFACEFORMAT_R8G8B8A8_USCALED               0x0F5
387 #define BRW_SURFACEFORMAT_R16G16_SSCALED                 0x0F6
388 #define BRW_SURFACEFORMAT_R16G16_USCALED                 0x0F7
389 #define BRW_SURFACEFORMAT_R32_SSCALED                    0x0F8
390 #define BRW_SURFACEFORMAT_R32_USCALED                    0x0F9
391 #define BRW_SURFACEFORMAT_B5G6R5_UNORM                   0x100
392 #define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB              0x101
393 #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM                 0x102
394 #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB            0x103
395 #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM                 0x104
396 #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB            0x105
397 #define BRW_SURFACEFORMAT_R8G8_UNORM                     0x106
398 #define BRW_SURFACEFORMAT_R8G8_SNORM                     0x107
399 #define BRW_SURFACEFORMAT_R8G8_SINT                      0x108
400 #define BRW_SURFACEFORMAT_R8G8_UINT                      0x109
401 #define BRW_SURFACEFORMAT_R16_UNORM                      0x10A
402 #define BRW_SURFACEFORMAT_R16_SNORM                      0x10B
403 #define BRW_SURFACEFORMAT_R16_SINT                       0x10C
404 #define BRW_SURFACEFORMAT_R16_UINT                       0x10D
405 #define BRW_SURFACEFORMAT_R16_FLOAT                      0x10E
406 #define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE0            0x10F
407 #define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE1            0x110
408 #define BRW_SURFACEFORMAT_I16_UNORM                      0x111
409 #define BRW_SURFACEFORMAT_L16_UNORM                      0x112
410 #define BRW_SURFACEFORMAT_A16_UNORM                      0x113
411 #define BRW_SURFACEFORMAT_L8A8_UNORM                     0x114
412 #define BRW_SURFACEFORMAT_I16_FLOAT                      0x115
413 #define BRW_SURFACEFORMAT_L16_FLOAT                      0x116
414 #define BRW_SURFACEFORMAT_A16_FLOAT                      0x117
415 #define BRW_SURFACEFORMAT_L8A8_UNORM_SRGB                0x118
416 #define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM            0x119
417 #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM                 0x11A
418 #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB            0x11B
419 #define BRW_SURFACEFORMAT_R8G8_SSCALED                   0x11C
420 #define BRW_SURFACEFORMAT_R8G8_USCALED                   0x11D
421 #define BRW_SURFACEFORMAT_R16_SSCALED                    0x11E
422 #define BRW_SURFACEFORMAT_R16_USCALED                    0x11F
423 #define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE0            0x122
424 #define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE1            0x123
425 #define BRW_SURFACEFORMAT_A1B5G5R5_UNORM                 0x124
426 #define BRW_SURFACEFORMAT_A4B4G4R4_UNORM                 0x125
427 #define BRW_SURFACEFORMAT_L8A8_UINT                      0x126
428 #define BRW_SURFACEFORMAT_L8A8_SINT                      0x127
429 #define BRW_SURFACEFORMAT_R8_UNORM                       0x140
430 #define BRW_SURFACEFORMAT_R8_SNORM                       0x141
431 #define BRW_SURFACEFORMAT_R8_SINT                        0x142
432 #define BRW_SURFACEFORMAT_R8_UINT                        0x143
433 #define BRW_SURFACEFORMAT_A8_UNORM                       0x144
434 #define BRW_SURFACEFORMAT_I8_UNORM                       0x145
435 #define BRW_SURFACEFORMAT_L8_UNORM                       0x146
436 #define BRW_SURFACEFORMAT_P4A4_UNORM                     0x147
437 #define BRW_SURFACEFORMAT_A4P4_UNORM                     0x148
438 #define BRW_SURFACEFORMAT_R8_SSCALED                     0x149
439 #define BRW_SURFACEFORMAT_R8_USCALED                     0x14A
440 #define BRW_SURFACEFORMAT_P8_UNORM_PALETTE0              0x14B
441 #define BRW_SURFACEFORMAT_L8_UNORM_SRGB                  0x14C
442 #define BRW_SURFACEFORMAT_P8_UNORM_PALETTE1              0x14D
443 #define BRW_SURFACEFORMAT_P4A4_UNORM_PALETTE1            0x14E
444 #define BRW_SURFACEFORMAT_A4P4_UNORM_PALETTE1            0x14F
445 #define BRW_SURFACEFORMAT_Y8_SNORM                       0x150
446 #define BRW_SURFACEFORMAT_L8_UINT                        0x152
447 #define BRW_SURFACEFORMAT_L8_SINT                        0x153
448 #define BRW_SURFACEFORMAT_I8_UINT                        0x154
449 #define BRW_SURFACEFORMAT_I8_SINT                        0x155
450 #define BRW_SURFACEFORMAT_DXT1_RGB_SRGB                  0x180
451 #define BRW_SURFACEFORMAT_R1_UINT                        0x181
452 #define BRW_SURFACEFORMAT_YCRCB_NORMAL                   0x182
453 #define BRW_SURFACEFORMAT_YCRCB_SWAPUVY                  0x183
454 #define BRW_SURFACEFORMAT_P2_UNORM_PALETTE0              0x184
455 #define BRW_SURFACEFORMAT_P2_UNORM_PALETTE1              0x185
456 #define BRW_SURFACEFORMAT_BC1_UNORM                      0x186
457 #define BRW_SURFACEFORMAT_BC2_UNORM                      0x187
458 #define BRW_SURFACEFORMAT_BC3_UNORM                      0x188
459 #define BRW_SURFACEFORMAT_BC4_UNORM                      0x189
460 #define BRW_SURFACEFORMAT_BC5_UNORM                      0x18A
461 #define BRW_SURFACEFORMAT_BC1_UNORM_SRGB                 0x18B
462 #define BRW_SURFACEFORMAT_BC2_UNORM_SRGB                 0x18C
463 #define BRW_SURFACEFORMAT_BC3_UNORM_SRGB                 0x18D
464 #define BRW_SURFACEFORMAT_MONO8                          0x18E
465 #define BRW_SURFACEFORMAT_YCRCB_SWAPUV                   0x18F
466 #define BRW_SURFACEFORMAT_YCRCB_SWAPY                    0x190
467 #define BRW_SURFACEFORMAT_DXT1_RGB                       0x191
468 #define BRW_SURFACEFORMAT_FXT1                           0x192
469 #define BRW_SURFACEFORMAT_R8G8B8_UNORM                   0x193
470 #define BRW_SURFACEFORMAT_R8G8B8_SNORM                   0x194
471 #define BRW_SURFACEFORMAT_R8G8B8_SSCALED                 0x195
472 #define BRW_SURFACEFORMAT_R8G8B8_USCALED                 0x196
473 #define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT             0x197
474 #define BRW_SURFACEFORMAT_R64G64B64_FLOAT                0x198
475 #define BRW_SURFACEFORMAT_BC4_SNORM                      0x199
476 #define BRW_SURFACEFORMAT_BC5_SNORM                      0x19A
477 #define BRW_SURFACEFORMAT_R16G16B16_FLOAT                0x19B
478 #define BRW_SURFACEFORMAT_R16G16B16_UNORM                0x19C
479 #define BRW_SURFACEFORMAT_R16G16B16_SNORM                0x19D
480 #define BRW_SURFACEFORMAT_R16G16B16_SSCALED              0x19E
481 #define BRW_SURFACEFORMAT_R16G16B16_USCALED              0x19F
482 #define BRW_SURFACEFORMAT_BC6H_SF16                      0x1A1
483 #define BRW_SURFACEFORMAT_BC7_UNORM                      0x1A2
484 #define BRW_SURFACEFORMAT_BC7_UNORM_SRGB                 0x1A3
485 #define BRW_SURFACEFORMAT_BC6H_UF16                      0x1A4
486 #define BRW_SURFACEFORMAT_PLANAR_420_8                   0x1A5
487 #define BRW_SURFACEFORMAT_R8G8B8_UNORM_SRGB              0x1A8
488 #define BRW_SURFACEFORMAT_ETC1_RGB8                      0x1A9
489 #define BRW_SURFACEFORMAT_ETC2_RGB8                      0x1AA
490 #define BRW_SURFACEFORMAT_EAC_R11                        0x1AB
491 #define BRW_SURFACEFORMAT_EAC_RG11                       0x1AC
492 #define BRW_SURFACEFORMAT_EAC_SIGNED_R11                 0x1AD
493 #define BRW_SURFACEFORMAT_EAC_SIGNED_RG11                0x1AE
494 #define BRW_SURFACEFORMAT_ETC2_SRGB8                     0x1AF
495 #define BRW_SURFACEFORMAT_R16G16B16_UINT                 0x1B0
496 #define BRW_SURFACEFORMAT_R16G16B16_SINT                 0x1B1
497 #define BRW_SURFACEFORMAT_R32_SFIXED                     0x1B2
498 #define BRW_SURFACEFORMAT_R10G10B10A2_SNORM              0x1B3
499 #define BRW_SURFACEFORMAT_R10G10B10A2_USCALED            0x1B4
500 #define BRW_SURFACEFORMAT_R10G10B10A2_SSCALED            0x1B5
501 #define BRW_SURFACEFORMAT_R10G10B10A2_SINT               0x1B6
502 #define BRW_SURFACEFORMAT_B10G10R10A2_SNORM              0x1B7
503 #define BRW_SURFACEFORMAT_B10G10R10A2_USCALED            0x1B8
504 #define BRW_SURFACEFORMAT_B10G10R10A2_SSCALED            0x1B9
505 #define BRW_SURFACEFORMAT_B10G10R10A2_UINT               0x1BA
506 #define BRW_SURFACEFORMAT_B10G10R10A2_SINT               0x1BB
507 #define BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU          0x1BC
508 #define BRW_SURFACEFORMAT_R64G64B64_PASSTHRU             0x1BD
509 #define BRW_SURFACEFORMAT_ETC2_RGB8_PTA                  0x1C0
510 #define BRW_SURFACEFORMAT_ETC2_SRGB8_PTA                 0x1C1
511 #define BRW_SURFACEFORMAT_ETC2_EAC_RGBA8                 0x1C2
512 #define BRW_SURFACEFORMAT_ETC2_EAC_SRGB8_A8              0x1C3
513 #define BRW_SURFACEFORMAT_R8G8B8_UINT                    0x1C8
514 #define BRW_SURFACEFORMAT_R8G8B8_SINT                    0x1C9
515 #define BRW_SURFACEFORMAT_RAW                            0x1FF
516 
517 #define GEN9_SURFACE_ASTC_HDR_FORMAT_BIT                 0x100
518 
519 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_4x4_U8sRGB         0x200
520 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x4_U8sRGB         0x208
521 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x5_U8sRGB         0x209
522 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x5_U8sRGB         0x211
523 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x6_U8sRGB         0x212
524 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x5_U8sRGB         0x221
525 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x6_U8sRGB         0x222
526 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x8_U8sRGB         0x224
527 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x5_U8sRGB        0x231
528 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x6_U8sRGB        0x232
529 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x8_U8sRGB        0x234
530 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x10_U8sRGB       0x236
531 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x10_U8sRGB       0x23E
532 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x12_U8sRGB       0x23F
533 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_4x4_FLT16          0x240
534 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x4_FLT16          0x248
535 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_5x5_FLT16          0x249
536 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x5_FLT16          0x251
537 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_6x6_FLT16          0x252
538 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x5_FLT16          0x261
539 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x6_FLT16          0x262
540 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_8x8_FLT16          0x264
541 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x5_FLT16         0x271
542 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x6_FLT16         0x272
543 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x8_FLT16         0x274
544 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_10x10_FLT16        0x276
545 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x10_FLT16        0x27E
546 #define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x12_FLT16        0x27F
547 
548 #define BRW_SURFACE_FORMAT_SHIFT	18
549 #define BRW_SURFACE_FORMAT_MASK		INTEL_MASK(26, 18)
550 
551 #define BRW_SURFACERETURNFORMAT_FLOAT32  0
552 #define BRW_SURFACERETURNFORMAT_S1       1
553 
554 #define BRW_SURFACE_TYPE_SHIFT		29
555 #define BRW_SURFACE_TYPE_MASK		INTEL_MASK(31, 29)
556 #define BRW_SURFACE_1D      0
557 #define BRW_SURFACE_2D      1
558 #define BRW_SURFACE_3D      2
559 #define BRW_SURFACE_CUBE    3
560 #define BRW_SURFACE_BUFFER  4
561 #define BRW_SURFACE_NULL    7
562 
563 #define GEN7_SURFACE_IS_ARRAY           (1 << 28)
564 #define GEN7_SURFACE_VALIGN_2           (0 << 16)
565 #define GEN7_SURFACE_VALIGN_4           (1 << 16)
566 #define GEN7_SURFACE_HALIGN_4           (0 << 15)
567 #define GEN7_SURFACE_HALIGN_8           (1 << 15)
568 #define GEN7_SURFACE_TILING_NONE        (0 << 13)
569 #define GEN7_SURFACE_TILING_X           (2 << 13)
570 #define GEN7_SURFACE_TILING_Y           (3 << 13)
571 #define GEN7_SURFACE_ARYSPC_FULL	(0 << 10)
572 #define GEN7_SURFACE_ARYSPC_LOD0	(1 << 10)
573 
574 /* Surface state DW1 */
575 #define GEN8_SURFACE_MOCS_SHIFT         24
576 #define GEN8_SURFACE_MOCS_MASK          INTEL_MASK(30, 24)
577 #define GEN8_SURFACE_QPITCH_SHIFT       0
578 #define GEN8_SURFACE_QPITCH_MASK        INTEL_MASK(14, 0)
579 
580 /* Surface state DW2 */
581 #define BRW_SURFACE_HEIGHT_SHIFT	19
582 #define BRW_SURFACE_HEIGHT_MASK		INTEL_MASK(31, 19)
583 #define BRW_SURFACE_WIDTH_SHIFT		6
584 #define BRW_SURFACE_WIDTH_MASK		INTEL_MASK(18, 6)
585 #define BRW_SURFACE_LOD_SHIFT		2
586 #define BRW_SURFACE_LOD_MASK		INTEL_MASK(5, 2)
587 #define GEN7_SURFACE_HEIGHT_SHIFT       16
588 #define GEN7_SURFACE_HEIGHT_MASK        INTEL_MASK(29, 16)
589 #define GEN7_SURFACE_WIDTH_SHIFT        0
590 #define GEN7_SURFACE_WIDTH_MASK         INTEL_MASK(13, 0)
591 
592 /* Surface state DW3 */
593 #define BRW_SURFACE_DEPTH_SHIFT		21
594 #define BRW_SURFACE_DEPTH_MASK		INTEL_MASK(31, 21)
595 #define BRW_SURFACE_PITCH_SHIFT		3
596 #define BRW_SURFACE_PITCH_MASK		INTEL_MASK(19, 3)
597 #define BRW_SURFACE_TILED		(1 << 1)
598 #define BRW_SURFACE_TILED_Y		(1 << 0)
599 #define HSW_SURFACE_IS_INTEGER_FORMAT   (1 << 18)
600 
601 /* Surface state DW4 */
602 #define BRW_SURFACE_MIN_LOD_SHIFT	28
603 #define BRW_SURFACE_MIN_LOD_MASK	INTEL_MASK(31, 28)
604 #define BRW_SURFACE_MIN_ARRAY_ELEMENT_SHIFT	17
605 #define BRW_SURFACE_MIN_ARRAY_ELEMENT_MASK	INTEL_MASK(27, 17)
606 #define BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT	8
607 #define BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT_MASK	INTEL_MASK(16, 8)
608 #define BRW_SURFACE_MULTISAMPLECOUNT_1  (0 << 4)
609 #define BRW_SURFACE_MULTISAMPLECOUNT_4  (2 << 4)
610 #define GEN7_SURFACE_MULTISAMPLECOUNT_1         (0 << 3)
611 #define GEN8_SURFACE_MULTISAMPLECOUNT_2         (1 << 3)
612 #define GEN7_SURFACE_MULTISAMPLECOUNT_4         (2 << 3)
613 #define GEN7_SURFACE_MULTISAMPLECOUNT_8         (3 << 3)
614 #define GEN8_SURFACE_MULTISAMPLECOUNT_16        (4 << 3)
615 #define GEN7_SURFACE_MSFMT_MSS                  (0 << 6)
616 #define GEN7_SURFACE_MSFMT_DEPTH_STENCIL        (1 << 6)
617 #define GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT	18
618 #define GEN7_SURFACE_MIN_ARRAY_ELEMENT_MASK     INTEL_MASK(28, 18)
619 #define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT	7
620 #define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_MASK   INTEL_MASK(17, 7)
621 
622 /* Surface state DW5 */
623 #define BRW_SURFACE_X_OFFSET_SHIFT		25
624 #define BRW_SURFACE_X_OFFSET_MASK		INTEL_MASK(31, 25)
625 #define BRW_SURFACE_VERTICAL_ALIGN_ENABLE	(1 << 24)
626 #define BRW_SURFACE_Y_OFFSET_SHIFT		20
627 #define BRW_SURFACE_Y_OFFSET_MASK		INTEL_MASK(23, 20)
628 #define GEN7_SURFACE_MIN_LOD_SHIFT              4
629 #define GEN7_SURFACE_MIN_LOD_MASK               INTEL_MASK(7, 4)
630 #define GEN8_SURFACE_Y_OFFSET_SHIFT		21
631 #define GEN8_SURFACE_Y_OFFSET_MASK		INTEL_MASK(23, 21)
632 
633 #define GEN7_SURFACE_MOCS_SHIFT                 16
634 #define GEN7_SURFACE_MOCS_MASK                  INTEL_MASK(19, 16)
635 
636 #define GEN9_SURFACE_TRMODE_SHIFT          18
637 #define GEN9_SURFACE_TRMODE_MASK           INTEL_MASK(19, 18)
638 #define GEN9_SURFACE_TRMODE_NONE           0
639 #define GEN9_SURFACE_TRMODE_TILEYF         1
640 #define GEN9_SURFACE_TRMODE_TILEYS         2
641 
642 #define GEN9_SURFACE_MIP_TAIL_START_LOD_SHIFT      8
643 #define GEN9_SURFACE_MIP_TAIL_START_LOD_MASK       INTEL_MASK(11, 8)
644 
645 /* Surface state DW6 */
646 #define GEN7_SURFACE_MCS_ENABLE                 (1 << 0)
647 #define GEN7_SURFACE_MCS_PITCH_SHIFT            3
648 #define GEN7_SURFACE_MCS_PITCH_MASK             INTEL_MASK(11, 3)
649 #define GEN8_SURFACE_AUX_QPITCH_SHIFT           16
650 #define GEN8_SURFACE_AUX_QPITCH_MASK            INTEL_MASK(30, 16)
651 #define GEN8_SURFACE_AUX_PITCH_SHIFT            3
652 #define GEN8_SURFACE_AUX_PITCH_MASK             INTEL_MASK(11, 3)
653 #define GEN8_SURFACE_AUX_MODE_MASK              INTEL_MASK(2, 0)
654 
655 #define GEN8_SURFACE_AUX_MODE_NONE              0
656 #define GEN8_SURFACE_AUX_MODE_MCS               1
657 #define GEN8_SURFACE_AUX_MODE_APPEND            2
658 #define GEN8_SURFACE_AUX_MODE_HIZ               3
659 #define GEN9_SURFACE_AUX_MODE_CCS_E             5
660 
661 /* Surface state DW7 */
662 #define GEN9_SURFACE_RT_COMPRESSION_SHIFT       30
663 #define GEN9_SURFACE_RT_COMPRESSION_MASK        INTEL_MASK(30, 30)
664 #define GEN7_SURFACE_CLEAR_COLOR_SHIFT		28
665 #define GEN7_SURFACE_SCS_R_SHIFT                25
666 #define GEN7_SURFACE_SCS_R_MASK                 INTEL_MASK(27, 25)
667 #define GEN7_SURFACE_SCS_G_SHIFT                22
668 #define GEN7_SURFACE_SCS_G_MASK                 INTEL_MASK(24, 22)
669 #define GEN7_SURFACE_SCS_B_SHIFT                19
670 #define GEN7_SURFACE_SCS_B_MASK                 INTEL_MASK(21, 19)
671 #define GEN7_SURFACE_SCS_A_SHIFT                16
672 #define GEN7_SURFACE_SCS_A_MASK                 INTEL_MASK(18, 16)
673 
674 /* The actual swizzle values/what channel to use */
675 #define HSW_SCS_ZERO                     0
676 #define HSW_SCS_ONE                      1
677 #define HSW_SCS_RED                      4
678 #define HSW_SCS_GREEN                    5
679 #define HSW_SCS_BLUE                     6
680 #define HSW_SCS_ALPHA                    7
681 
682 /* SAMPLER_STATE DW0 */
683 #define BRW_SAMPLER_DISABLE                     (1 << 31)
684 #define BRW_SAMPLER_LOD_PRECLAMP_ENABLE         (1 << 28)
685 #define GEN6_SAMPLER_MIN_MAG_NOT_EQUAL          (1 << 27) /* Gen6 only */
686 #define BRW_SAMPLER_BASE_MIPLEVEL_MASK          INTEL_MASK(26, 22)
687 #define BRW_SAMPLER_BASE_MIPLEVEL_SHIFT         22
688 #define BRW_SAMPLER_MIP_FILTER_MASK             INTEL_MASK(21, 20)
689 #define BRW_SAMPLER_MIP_FILTER_SHIFT            20
690 #define BRW_SAMPLER_MAG_FILTER_MASK             INTEL_MASK(19, 17)
691 #define BRW_SAMPLER_MAG_FILTER_SHIFT            17
692 #define BRW_SAMPLER_MIN_FILTER_MASK             INTEL_MASK(16, 14)
693 #define BRW_SAMPLER_MIN_FILTER_SHIFT            14
694 #define GEN4_SAMPLER_LOD_BIAS_MASK              INTEL_MASK(13, 3)
695 #define GEN4_SAMPLER_LOD_BIAS_SHIFT             3
696 #define GEN4_SAMPLER_SHADOW_FUNCTION_MASK       INTEL_MASK(2, 0)
697 #define GEN4_SAMPLER_SHADOW_FUNCTION_SHIFT      0
698 
699 #define GEN7_SAMPLER_LOD_BIAS_MASK              INTEL_MASK(13, 1)
700 #define GEN7_SAMPLER_LOD_BIAS_SHIFT             1
701 #define GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHM  (1 << 0)
702 
703 /* SAMPLER_STATE DW1 */
704 #define GEN4_SAMPLER_MIN_LOD_MASK               INTEL_MASK(31, 22)
705 #define GEN4_SAMPLER_MIN_LOD_SHIFT              22
706 #define GEN4_SAMPLER_MAX_LOD_MASK               INTEL_MASK(21, 12)
707 #define GEN4_SAMPLER_MAX_LOD_SHIFT              12
708 #define GEN4_SAMPLER_CUBE_CONTROL_OVERRIDE      (1 << 9)
709 /* Wrap modes are in DW1 on Gen4-6 and DW3 on Gen7+ */
710 #define BRW_SAMPLER_TCX_WRAP_MODE_MASK          INTEL_MASK(8, 6)
711 #define BRW_SAMPLER_TCX_WRAP_MODE_SHIFT         6
712 #define BRW_SAMPLER_TCY_WRAP_MODE_MASK          INTEL_MASK(5, 3)
713 #define BRW_SAMPLER_TCY_WRAP_MODE_SHIFT         3
714 #define BRW_SAMPLER_TCZ_WRAP_MODE_MASK          INTEL_MASK(2, 0)
715 #define BRW_SAMPLER_TCZ_WRAP_MODE_SHIFT         0
716 
717 #define GEN7_SAMPLER_MIN_LOD_MASK               INTEL_MASK(31, 20)
718 #define GEN7_SAMPLER_MIN_LOD_SHIFT              20
719 #define GEN7_SAMPLER_MAX_LOD_MASK               INTEL_MASK(19, 8)
720 #define GEN7_SAMPLER_MAX_LOD_SHIFT              8
721 #define GEN7_SAMPLER_SHADOW_FUNCTION_MASK       INTEL_MASK(3, 1)
722 #define GEN7_SAMPLER_SHADOW_FUNCTION_SHIFT      1
723 #define GEN7_SAMPLER_CUBE_CONTROL_OVERRIDE      (1 << 0)
724 
725 /* SAMPLER_STATE DW2 - border color pointer */
726 
727 /* SAMPLER_STATE DW3 */
728 #define BRW_SAMPLER_MAX_ANISOTROPY_MASK         INTEL_MASK(21, 19)
729 #define BRW_SAMPLER_MAX_ANISOTROPY_SHIFT        19
730 #define BRW_SAMPLER_ADDRESS_ROUNDING_MASK       INTEL_MASK(18, 13)
731 #define BRW_SAMPLER_ADDRESS_ROUNDING_SHIFT      13
732 #define GEN7_SAMPLER_NON_NORMALIZED_COORDINATES (1 << 10)
733 /* Gen7+ wrap modes reuse the same BRW_SAMPLER_TC*_WRAP_MODE enums. */
734 #define GEN6_SAMPLER_NON_NORMALIZED_COORDINATES (1 << 0)
735 
736 enum brw_wrap_mode {
737    BRW_TEXCOORDMODE_WRAP         = 0,
738    BRW_TEXCOORDMODE_MIRROR       = 1,
739    BRW_TEXCOORDMODE_CLAMP        = 2,
740    BRW_TEXCOORDMODE_CUBE         = 3,
741    BRW_TEXCOORDMODE_CLAMP_BORDER = 4,
742    BRW_TEXCOORDMODE_MIRROR_ONCE  = 5,
743    GEN8_TEXCOORDMODE_HALF_BORDER = 6,
744 };
745 
746 #define BRW_THREAD_PRIORITY_NORMAL   0
747 #define BRW_THREAD_PRIORITY_HIGH     1
748 
749 #define BRW_TILEWALK_XMAJOR                 0
750 #define BRW_TILEWALK_YMAJOR                 1
751 
752 #define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS  0
753 #define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS  1
754 
755 /* Execution Unit (EU) defines
756  */
757 
758 #define BRW_ALIGN_1   0
759 #define BRW_ALIGN_16  1
760 
761 #define BRW_ADDRESS_DIRECT                        0
762 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER    1
763 
764 #define BRW_CHANNEL_X     0
765 #define BRW_CHANNEL_Y     1
766 #define BRW_CHANNEL_Z     2
767 #define BRW_CHANNEL_W     3
768 
769 enum brw_compression {
770    BRW_COMPRESSION_NONE       = 0,
771    BRW_COMPRESSION_2NDHALF    = 1,
772    BRW_COMPRESSION_COMPRESSED = 2,
773 };
774 
775 #define GEN6_COMPRESSION_1Q		0
776 #define GEN6_COMPRESSION_2Q		1
777 #define GEN6_COMPRESSION_3Q		2
778 #define GEN6_COMPRESSION_4Q		3
779 #define GEN6_COMPRESSION_1H		0
780 #define GEN6_COMPRESSION_2H		2
781 
782 enum PACKED brw_conditional_mod {
783    BRW_CONDITIONAL_NONE = 0,
784    BRW_CONDITIONAL_Z    = 1,
785    BRW_CONDITIONAL_NZ   = 2,
786    BRW_CONDITIONAL_EQ   = 1,	/* Z */
787    BRW_CONDITIONAL_NEQ  = 2,	/* NZ */
788    BRW_CONDITIONAL_G    = 3,
789    BRW_CONDITIONAL_GE   = 4,
790    BRW_CONDITIONAL_L    = 5,
791    BRW_CONDITIONAL_LE   = 6,
792    BRW_CONDITIONAL_R    = 7,    /* Gen <= 5 */
793    BRW_CONDITIONAL_O    = 8,
794    BRW_CONDITIONAL_U    = 9,
795 };
796 
797 #define BRW_DEBUG_NONE        0
798 #define BRW_DEBUG_BREAKPOINT  1
799 
800 #define BRW_DEPENDENCY_NORMAL         0
801 #define BRW_DEPENDENCY_NOTCLEARED     1
802 #define BRW_DEPENDENCY_NOTCHECKED     2
803 #define BRW_DEPENDENCY_DISABLE        3
804 
805 enum PACKED brw_execution_size {
806    BRW_EXECUTE_1  = 0,
807    BRW_EXECUTE_2  = 1,
808    BRW_EXECUTE_4  = 2,
809    BRW_EXECUTE_8  = 3,
810    BRW_EXECUTE_16 = 4,
811    BRW_EXECUTE_32 = 5,
812 };
813 
814 enum PACKED brw_horizontal_stride {
815    BRW_HORIZONTAL_STRIDE_0 = 0,
816    BRW_HORIZONTAL_STRIDE_1 = 1,
817    BRW_HORIZONTAL_STRIDE_2 = 2,
818    BRW_HORIZONTAL_STRIDE_4 = 3,
819 };
820 
821 #define BRW_INSTRUCTION_NORMAL    0
822 #define BRW_INSTRUCTION_SATURATE  1
823 
824 #define BRW_MASK_ENABLE   0
825 #define BRW_MASK_DISABLE  1
826 
827 /** @{
828  *
829  * Gen6 has replaced "mask enable/disable" with WECtrl, which is
830  * effectively the same but much simpler to think about.  Now, there
831  * are two contributors ANDed together to whether channels are
832  * executed: The predication on the instruction, and the channel write
833  * enable.
834  */
835 /**
836  * This is the default value.  It means that a channel's write enable is set
837  * if the per-channel IP is pointing at this instruction.
838  */
839 #define BRW_WE_NORMAL		0
840 /**
841  * This is used like BRW_MASK_DISABLE, and causes all channels to have
842  * their write enable set.  Note that predication still contributes to
843  * whether the channel actually gets written.
844  */
845 #define BRW_WE_ALL		1
846 /** @} */
847 
848 enum opcode {
849    /* These are the actual hardware opcodes. */
850    BRW_OPCODE_ILLEGAL = 0,
851    BRW_OPCODE_MOV =	1,
852    BRW_OPCODE_SEL =	2,
853    BRW_OPCODE_MOVI =	3,   /**< G45+ */
854    BRW_OPCODE_NOT =	4,
855    BRW_OPCODE_AND =	5,
856    BRW_OPCODE_OR =	6,
857    BRW_OPCODE_XOR =	7,
858    BRW_OPCODE_SHR =	8,
859    BRW_OPCODE_SHL =	9,
860    BRW_OPCODE_DIM =	10,  /**< Gen7.5 only */ /* Reused */
861    // BRW_OPCODE_SMOV =	10,  /**< Gen8+       */ /* Reused */
862    /* Reserved - 11 */
863    BRW_OPCODE_ASR =	12,
864    /* Reserved - 13-15 */
865    BRW_OPCODE_CMP =	16,
866    BRW_OPCODE_CMPN =	17,
867    BRW_OPCODE_CSEL =	18,  /**< Gen8+ */
868    BRW_OPCODE_F32TO16 = 19,  /**< Gen7 only */
869    BRW_OPCODE_F16TO32 = 20,  /**< Gen7 only */
870    /* Reserved - 21-22 */
871    BRW_OPCODE_BFREV =	23,  /**< Gen7+ */
872    BRW_OPCODE_BFE =	24,  /**< Gen7+ */
873    BRW_OPCODE_BFI1 =	25,  /**< Gen7+ */
874    BRW_OPCODE_BFI2 =	26,  /**< Gen7+ */
875    /* Reserved - 27-31 */
876    BRW_OPCODE_JMPI =	32,
877    // BRW_OPCODE_BRD =	33,  /**< Gen7+ */
878    BRW_OPCODE_IF =	34,
879    BRW_OPCODE_IFF =	35,  /**< Pre-Gen6    */ /* Reused */
880    // BRW_OPCODE_BRC =	35,  /**< Gen7+       */ /* Reused */
881    BRW_OPCODE_ELSE =	36,
882    BRW_OPCODE_ENDIF =	37,
883    BRW_OPCODE_DO =	38,  /**< Pre-Gen6    */ /* Reused */
884    // BRW_OPCODE_CASE =	38,  /**< Gen6 only   */ /* Reused */
885    BRW_OPCODE_WHILE =	39,
886    BRW_OPCODE_BREAK =	40,
887    BRW_OPCODE_CONTINUE = 41,
888    BRW_OPCODE_HALT =	42,
889    // BRW_OPCODE_CALLA =	43,  /**< Gen7.5+     */
890    // BRW_OPCODE_MSAVE =	44,  /**< Pre-Gen6    */ /* Reused */
891    // BRW_OPCODE_CALL =	44,  /**< Gen6+       */ /* Reused */
892    // BRW_OPCODE_MREST =	45,  /**< Pre-Gen6    */ /* Reused */
893    // BRW_OPCODE_RET =	45,  /**< Gen6+       */ /* Reused */
894    // BRW_OPCODE_PUSH =	46,  /**< Pre-Gen6    */ /* Reused */
895    // BRW_OPCODE_FORK =	46,  /**< Gen6 only   */ /* Reused */
896    // BRW_OPCODE_GOTO =	46,  /**< Gen8+       */ /* Reused */
897    // BRW_OPCODE_POP =	47,  /**< Pre-Gen6    */
898    BRW_OPCODE_WAIT =	48,
899    BRW_OPCODE_SEND =	49,
900    BRW_OPCODE_SENDC =	50,
901    BRW_OPCODE_SENDS =	51,  /**< Gen9+ */
902    BRW_OPCODE_SENDSC =	52,  /**< Gen9+ */
903    /* Reserved 53-55 */
904    BRW_OPCODE_MATH =	56,  /**< Gen6+ */
905    /* Reserved 57-63 */
906    BRW_OPCODE_ADD =	64,
907    BRW_OPCODE_MUL =	65,
908    BRW_OPCODE_AVG =	66,
909    BRW_OPCODE_FRC =	67,
910    BRW_OPCODE_RNDU =	68,
911    BRW_OPCODE_RNDD =	69,
912    BRW_OPCODE_RNDE =	70,
913    BRW_OPCODE_RNDZ =	71,
914    BRW_OPCODE_MAC =	72,
915    BRW_OPCODE_MACH =	73,
916    BRW_OPCODE_LZD =	74,
917    BRW_OPCODE_FBH =	75,  /**< Gen7+ */
918    BRW_OPCODE_FBL =	76,  /**< Gen7+ */
919    BRW_OPCODE_CBIT =	77,  /**< Gen7+ */
920    BRW_OPCODE_ADDC =	78,  /**< Gen7+ */
921    BRW_OPCODE_SUBB =	79,  /**< Gen7+ */
922    BRW_OPCODE_SAD2 =	80,
923    BRW_OPCODE_SADA2 =	81,
924    /* Reserved 82-83 */
925    BRW_OPCODE_DP4 =	84,
926    BRW_OPCODE_DPH =	85,
927    BRW_OPCODE_DP3 =	86,
928    BRW_OPCODE_DP2 =	87,
929    /* Reserved 88 */
930    BRW_OPCODE_LINE =	89,
931    BRW_OPCODE_PLN =	90,  /**< G45+ */
932    BRW_OPCODE_MAD =	91,  /**< Gen6+ */
933    BRW_OPCODE_LRP =	92,  /**< Gen6+ */
934    // BRW_OPCODE_MADM =	93,  /**< Gen8+ */
935    /* Reserved 94-124 */
936    BRW_OPCODE_NENOP =	125, /**< G45 only */
937    BRW_OPCODE_NOP =	126,
938    /* Reserved 127 */
939 
940    /* These are compiler backend opcodes that get translated into other
941     * instructions.
942     */
943    FS_OPCODE_FB_WRITE = 128,
944 
945    /**
946     * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
947     * individual sources instead of as a single payload blob. The
948     * position/ordering of the arguments are defined by the enum
949     * fb_write_logical_srcs.
950     */
951    FS_OPCODE_FB_WRITE_LOGICAL,
952 
953    FS_OPCODE_REP_FB_WRITE,
954 
955    FS_OPCODE_FB_READ,
956    FS_OPCODE_FB_READ_LOGICAL,
957 
958    SHADER_OPCODE_RCP,
959    SHADER_OPCODE_RSQ,
960    SHADER_OPCODE_SQRT,
961    SHADER_OPCODE_EXP2,
962    SHADER_OPCODE_LOG2,
963    SHADER_OPCODE_POW,
964    SHADER_OPCODE_INT_QUOTIENT,
965    SHADER_OPCODE_INT_REMAINDER,
966    SHADER_OPCODE_SIN,
967    SHADER_OPCODE_COS,
968 
969    /**
970     * Texture sampling opcodes.
971     *
972     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
973     * opcode but instead of taking a single payload blob they expect their
974     * arguments separately as individual sources. The position/ordering of the
975     * arguments are defined by the enum tex_logical_srcs.
976     */
977    SHADER_OPCODE_TEX,
978    SHADER_OPCODE_TEX_LOGICAL,
979    SHADER_OPCODE_TXD,
980    SHADER_OPCODE_TXD_LOGICAL,
981    SHADER_OPCODE_TXF,
982    SHADER_OPCODE_TXF_LOGICAL,
983    SHADER_OPCODE_TXF_LZ,
984    SHADER_OPCODE_TXL,
985    SHADER_OPCODE_TXL_LOGICAL,
986    SHADER_OPCODE_TXL_LZ,
987    SHADER_OPCODE_TXS,
988    SHADER_OPCODE_TXS_LOGICAL,
989    FS_OPCODE_TXB,
990    FS_OPCODE_TXB_LOGICAL,
991    SHADER_OPCODE_TXF_CMS,
992    SHADER_OPCODE_TXF_CMS_LOGICAL,
993    SHADER_OPCODE_TXF_CMS_W,
994    SHADER_OPCODE_TXF_CMS_W_LOGICAL,
995    SHADER_OPCODE_TXF_UMS,
996    SHADER_OPCODE_TXF_UMS_LOGICAL,
997    SHADER_OPCODE_TXF_MCS,
998    SHADER_OPCODE_TXF_MCS_LOGICAL,
999    SHADER_OPCODE_LOD,
1000    SHADER_OPCODE_LOD_LOGICAL,
1001    SHADER_OPCODE_TG4,
1002    SHADER_OPCODE_TG4_LOGICAL,
1003    SHADER_OPCODE_TG4_OFFSET,
1004    SHADER_OPCODE_TG4_OFFSET_LOGICAL,
1005    SHADER_OPCODE_SAMPLEINFO,
1006    SHADER_OPCODE_SAMPLEINFO_LOGICAL,
1007 
1008    /**
1009     * Combines multiple sources of size 1 into a larger virtual GRF.
1010     * For example, parameters for a send-from-GRF message.  Or, updating
1011     * channels of a size 4 VGRF used to store vec4s such as texturing results.
1012     *
1013     * This will be lowered into MOVs from each source to consecutive offsets
1014     * of the destination VGRF.
1015     *
1016     * src[0] may be BAD_FILE.  If so, the lowering pass skips emitting the MOV,
1017     * but still reserves the first channel of the destination VGRF.  This can be
1018     * used to reserve space for, say, a message header set up by the generators.
1019     */
1020    SHADER_OPCODE_LOAD_PAYLOAD,
1021 
1022    /**
1023     * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
1024     * acts intra-channel, obtaining the final value for each channel by
1025     * combining the sources values for the same channel, the first source
1026     * occupying the lowest bits and the last source occupying the highest
1027     * bits.
1028     */
1029    FS_OPCODE_PACK,
1030 
1031    SHADER_OPCODE_SHADER_TIME_ADD,
1032 
1033    /**
1034     * Typed and untyped surface access opcodes.
1035     *
1036     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
1037     * opcode but instead of taking a single payload blob they expect their
1038     * arguments separately as individual sources:
1039     *
1040     * Source 0: [required] Surface coordinates.
1041     * Source 1: [optional] Operation source.
1042     * Source 2: [required] Surface index.
1043     * Source 3: [required] Number of coordinate components (as UD immediate).
1044     * Source 4: [required] Opcode-specific control immediate, same as source 2
1045     *                      of the matching non-LOGICAL opcode.
1046     */
1047    SHADER_OPCODE_UNTYPED_ATOMIC,
1048    SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
1049    SHADER_OPCODE_UNTYPED_SURFACE_READ,
1050    SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
1051    SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
1052    SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
1053 
1054    SHADER_OPCODE_TYPED_ATOMIC,
1055    SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
1056    SHADER_OPCODE_TYPED_SURFACE_READ,
1057    SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
1058    SHADER_OPCODE_TYPED_SURFACE_WRITE,
1059    SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
1060 
1061    SHADER_OPCODE_MEMORY_FENCE,
1062 
1063    SHADER_OPCODE_GEN4_SCRATCH_READ,
1064    SHADER_OPCODE_GEN4_SCRATCH_WRITE,
1065    SHADER_OPCODE_GEN7_SCRATCH_READ,
1066 
1067    /**
1068     * Gen8+ SIMD8 URB Read messages.
1069     */
1070    SHADER_OPCODE_URB_READ_SIMD8,
1071    SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
1072 
1073    SHADER_OPCODE_URB_WRITE_SIMD8,
1074    SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
1075    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
1076    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
1077 
1078    /**
1079     * Return the index of an arbitrary live channel (i.e. one of the channels
1080     * enabled in the current execution mask) and assign it to the first
1081     * component of the destination.  Expected to be used as input for the
1082     * BROADCAST pseudo-opcode.
1083     */
1084    SHADER_OPCODE_FIND_LIVE_CHANNEL,
1085 
1086    /**
1087     * Pick the channel from its first source register given by the index
1088     * specified as second source.  Useful for variable indexing of surfaces.
1089     *
1090     * Note that because the result of this instruction is by definition
1091     * uniform and it can always be splatted to multiple channels using a
1092     * scalar regioning mode, only the first channel of the destination region
1093     * is guaranteed to be updated, which implies that BROADCAST instructions
1094     * should usually be marked force_writemask_all.
1095     */
1096    SHADER_OPCODE_BROADCAST,
1097 
1098    VEC4_OPCODE_MOV_BYTES,
1099    VEC4_OPCODE_PACK_BYTES,
1100    VEC4_OPCODE_UNPACK_UNIFORM,
1101    VEC4_OPCODE_FROM_DOUBLE,
1102    VEC4_OPCODE_TO_DOUBLE,
1103    VEC4_OPCODE_PICK_LOW_32BIT,
1104    VEC4_OPCODE_PICK_HIGH_32BIT,
1105    VEC4_OPCODE_SET_LOW_32BIT,
1106    VEC4_OPCODE_SET_HIGH_32BIT,
1107 
1108    FS_OPCODE_DDX_COARSE,
1109    FS_OPCODE_DDX_FINE,
1110    /**
1111     * Compute dFdy(), dFdyCoarse(), or dFdyFine().
1112     */
1113    FS_OPCODE_DDY_COARSE,
1114    FS_OPCODE_DDY_FINE,
1115    FS_OPCODE_CINTERP,
1116    FS_OPCODE_LINTERP,
1117    FS_OPCODE_PIXEL_X,
1118    FS_OPCODE_PIXEL_Y,
1119    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
1120    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
1121    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
1122    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
1123    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
1124    FS_OPCODE_GET_BUFFER_SIZE,
1125    FS_OPCODE_MOV_DISPATCH_TO_FLAGS,
1126    FS_OPCODE_DISCARD_JUMP,
1127    FS_OPCODE_SET_SAMPLE_ID,
1128    FS_OPCODE_PACK_HALF_2x16_SPLIT,
1129    FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X,
1130    FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y,
1131    FS_OPCODE_PLACEHOLDER_HALT,
1132    FS_OPCODE_INTERPOLATE_AT_SAMPLE,
1133    FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
1134    FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
1135 
1136    VS_OPCODE_URB_WRITE,
1137    VS_OPCODE_PULL_CONSTANT_LOAD,
1138    VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
1139    VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
1140 
1141    VS_OPCODE_GET_BUFFER_SIZE,
1142 
1143    VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
1144 
1145    /**
1146     * Write geometry shader output data to the URB.
1147     *
1148     * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
1149     * R0 to the first MRF.  This allows the geometry shader to override the
1150     * "Slot {0,1} Offset" fields in the message header.
1151     */
1152    GS_OPCODE_URB_WRITE,
1153 
1154    /**
1155     * Write geometry shader output data to the URB and request a new URB
1156     * handle (gen6).
1157     *
1158     * This opcode doesn't do an implied move from R0 to the first MRF.
1159     */
1160    GS_OPCODE_URB_WRITE_ALLOCATE,
1161 
1162    /**
1163     * Terminate the geometry shader thread by doing an empty URB write.
1164     *
1165     * This opcode doesn't do an implied move from R0 to the first MRF.  This
1166     * allows the geometry shader to override the "GS Number of Output Vertices
1167     * for Slot {0,1}" fields in the message header.
1168     */
1169    GS_OPCODE_THREAD_END,
1170 
1171    /**
1172     * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
1173     *
1174     * - dst is the MRF containing the message header.
1175     *
1176     * - src0.x indicates which portion of the URB should be written to (e.g. a
1177     *   vertex number)
1178     *
1179     * - src1 is an immediate multiplier which will be applied to src0
1180     *   (e.g. the size of a single vertex in the URB).
1181     *
1182     * Note: the hardware will apply this offset *in addition to* the offset in
1183     * vec4_instruction::offset.
1184     */
1185    GS_OPCODE_SET_WRITE_OFFSET,
1186 
1187    /**
1188     * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
1189     * URB_WRITE message header.
1190     *
1191     * - dst is the MRF containing the message header.
1192     *
1193     * - src0.x is the vertex count.  The upper 16 bits will be ignored.
1194     */
1195    GS_OPCODE_SET_VERTEX_COUNT,
1196 
1197    /**
1198     * Set DWORD 2 of dst to the value in src.
1199     */
1200    GS_OPCODE_SET_DWORD_2,
1201 
1202    /**
1203     * Prepare the dst register for storage in the "Channel Mask" fields of a
1204     * URB_WRITE message header.
1205     *
1206     * DWORD 4 of dst is shifted left by 4 bits, so that later,
1207     * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
1208     * final channel mask.
1209     *
1210     * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
1211     * form the final channel mask, DWORDs 0 and 4 of the dst register must not
1212     * have any extraneous bits set prior to execution of this opcode (that is,
1213     * they should be in the range 0x0 to 0xf).
1214     */
1215    GS_OPCODE_PREPARE_CHANNEL_MASKS,
1216 
1217    /**
1218     * Set the "Channel Mask" fields of a URB_WRITE message header.
1219     *
1220     * - dst is the MRF containing the message header.
1221     *
1222     * - src.x is the channel mask, as prepared by
1223     *   GS_OPCODE_PREPARE_CHANNEL_MASKS.  DWORDs 0 and 4 are OR'ed together to
1224     *   form the final channel mask.
1225     */
1226    GS_OPCODE_SET_CHANNEL_MASKS,
1227 
1228    /**
1229     * Get the "Instance ID" fields from the payload.
1230     *
1231     * - dst is the GRF for gl_InvocationID.
1232     */
1233    GS_OPCODE_GET_INSTANCE_ID,
1234 
1235    /**
1236     * Send a FF_SYNC message to allocate initial URB handles (gen6).
1237     *
1238     * - dst will be used as the writeback register for the FF_SYNC operation.
1239     *
1240     * - src0 is the number of primitives written.
1241     *
1242     * - src1 is the value to hold in M0.0: number of SO vertices to write
1243     *   and number of SO primitives needed. Its value will be overwritten
1244     *   with the SVBI values if transform feedback is enabled.
1245     *
1246     * Note: This opcode uses an implicit MRF register for the ff_sync message
1247     * header, so the caller is expected to set inst->base_mrf and initialize
1248     * that MRF register to r0. This opcode will also write to this MRF register
1249     * to include the allocated URB handle so it can then be reused directly as
1250     * the header in the URB write operation we are allocating the handle for.
1251     */
1252    GS_OPCODE_FF_SYNC,
1253 
1254    /**
1255     * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
1256     * register.
1257     *
1258     * - dst is the GRF where PrimitiveID information will be moved.
1259     */
1260    GS_OPCODE_SET_PRIMITIVE_ID,
1261 
1262    /**
1263     * Write transform feedback data to the SVB by sending a SVB WRITE message.
1264     * Used in gen6.
1265     *
1266     * - dst is the MRF register containing the message header.
1267     *
1268     * - src0 is the register where the vertex data is going to be copied from.
1269     *
1270     * - src1 is the destination register when write commit occurs.
1271     */
1272    GS_OPCODE_SVB_WRITE,
1273 
1274    /**
1275     * Set destination index in the SVB write message payload (M0.5). Used
1276     * in gen6 for transform feedback.
1277     *
1278     * - dst is the header to save the destination indices for SVB WRITE.
1279     * - src is the register that holds the destination indices value.
1280     */
1281    GS_OPCODE_SVB_SET_DST_INDEX,
1282 
1283    /**
1284     * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
1285     * Used in gen6 for transform feedback.
1286     *
1287     * - dst will hold the register with the final Mx.0 value.
1288     *
1289     * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
1290     *
1291     * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
1292     *
1293     * - src2 is the value to hold in M0: number of SO vertices to write
1294     *   and number of SO primitives needed.
1295     */
1296    GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
1297 
1298    /**
1299     * Terminate the compute shader.
1300     */
1301    CS_OPCODE_CS_TERMINATE,
1302 
1303    /**
1304     * GLSL barrier()
1305     */
1306    SHADER_OPCODE_BARRIER,
1307 
1308    /**
1309     * Calculate the high 32-bits of a 32x32 multiply.
1310     */
1311    SHADER_OPCODE_MULH,
1312 
1313    /**
1314     * A MOV that uses VxH indirect addressing.
1315     *
1316     * Source 0: A register to start from (HW_REG).
1317     * Source 1: An indirect offset (in bytes, UD GRF).
1318     * Source 2: The length of the region that could be accessed (in bytes,
1319     *           UD immediate).
1320     */
1321    SHADER_OPCODE_MOV_INDIRECT,
1322 
1323    VEC4_OPCODE_URB_READ,
1324    TCS_OPCODE_GET_INSTANCE_ID,
1325    TCS_OPCODE_URB_WRITE,
1326    TCS_OPCODE_SET_INPUT_URB_OFFSETS,
1327    TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
1328    TCS_OPCODE_GET_PRIMITIVE_ID,
1329    TCS_OPCODE_CREATE_BARRIER_HEADER,
1330    TCS_OPCODE_SRC0_010_IS_ZERO,
1331    TCS_OPCODE_RELEASE_INPUT,
1332    TCS_OPCODE_THREAD_END,
1333 
1334    TES_OPCODE_GET_PRIMITIVE_ID,
1335    TES_OPCODE_CREATE_INPUT_READ_HEADER,
1336    TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
1337 };
1338 
1339 enum brw_urb_write_flags {
1340    BRW_URB_WRITE_NO_FLAGS = 0,
1341 
1342    /**
1343     * Causes a new URB entry to be allocated, and its address stored in the
1344     * destination register (gen < 7).
1345     */
1346    BRW_URB_WRITE_ALLOCATE = 0x1,
1347 
1348    /**
1349     * Causes the current URB entry to be deallocated (gen < 7).
1350     */
1351    BRW_URB_WRITE_UNUSED = 0x2,
1352 
1353    /**
1354     * Causes the thread to terminate.
1355     */
1356    BRW_URB_WRITE_EOT = 0x4,
1357 
1358    /**
1359     * Indicates that the given URB entry is complete, and may be sent further
1360     * down the 3D pipeline (gen < 7).
1361     */
1362    BRW_URB_WRITE_COMPLETE = 0x8,
1363 
1364    /**
1365     * Indicates that an additional offset (which may be different for the two
1366     * vec4 slots) is stored in the message header (gen == 7).
1367     */
1368    BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
1369 
1370    /**
1371     * Indicates that the channel masks in the URB_WRITE message header should
1372     * not be overridden to 0xff (gen == 7).
1373     */
1374    BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
1375 
1376    /**
1377     * Indicates that the data should be sent to the URB using the
1378     * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7).  This
1379     * causes offsets to be interpreted as multiples of an OWORD instead of an
1380     * HWORD, and only allows one OWORD to be written.
1381     */
1382    BRW_URB_WRITE_OWORD = 0x40,
1383 
1384    /**
1385     * Convenient combination of flags: end the thread while simultaneously
1386     * marking the given URB entry as complete.
1387     */
1388    BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
1389 
1390    /**
1391     * Convenient combination of flags: mark the given URB entry as complete
1392     * and simultaneously allocate a new one.
1393     */
1394    BRW_URB_WRITE_ALLOCATE_COMPLETE =
1395       BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
1396 };
1397 
1398 enum fb_write_logical_srcs {
1399    FB_WRITE_LOGICAL_SRC_COLOR0,      /* REQUIRED */
1400    FB_WRITE_LOGICAL_SRC_COLOR1,      /* for dual source blend messages */
1401    FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
1402    FB_WRITE_LOGICAL_SRC_SRC_DEPTH,   /* gl_FragDepth */
1403    FB_WRITE_LOGICAL_SRC_DST_DEPTH,   /* GEN4-5: passthrough from thread */
1404    FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
1405    FB_WRITE_LOGICAL_SRC_OMASK,       /* Sample Mask (gl_SampleMask) */
1406    FB_WRITE_LOGICAL_SRC_COMPONENTS,  /* REQUIRED */
1407    FB_WRITE_LOGICAL_NUM_SRCS
1408 };
1409 
1410 enum tex_logical_srcs {
1411    /** Texture coordinates */
1412    TEX_LOGICAL_SRC_COORDINATE,
1413    /** Shadow comparator */
1414    TEX_LOGICAL_SRC_SHADOW_C,
1415    /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
1416    TEX_LOGICAL_SRC_LOD,
1417    /** dPdy if the operation takes explicit derivatives */
1418    TEX_LOGICAL_SRC_LOD2,
1419    /** Sample index */
1420    TEX_LOGICAL_SRC_SAMPLE_INDEX,
1421    /** MCS data */
1422    TEX_LOGICAL_SRC_MCS,
1423    /** REQUIRED: Texture surface index */
1424    TEX_LOGICAL_SRC_SURFACE,
1425    /** Texture sampler index */
1426    TEX_LOGICAL_SRC_SAMPLER,
1427    /** Texel offset for gathers */
1428    TEX_LOGICAL_SRC_TG4_OFFSET,
1429    /** REQUIRED: Number of coordinate components (as UD immediate) */
1430    TEX_LOGICAL_SRC_COORD_COMPONENTS,
1431    /** REQUIRED: Number of derivative components (as UD immediate) */
1432    TEX_LOGICAL_SRC_GRAD_COMPONENTS,
1433 
1434    TEX_LOGICAL_NUM_SRCS,
1435 };
1436 
1437 #ifdef __cplusplus
1438 /**
1439  * Allow brw_urb_write_flags enums to be ORed together.
1440  */
1441 inline brw_urb_write_flags
1442 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
1443 {
1444    return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
1445                                            static_cast<int>(y));
1446 }
1447 #endif
1448 
1449 enum PACKED brw_predicate {
1450    BRW_PREDICATE_NONE                =  0,
1451    BRW_PREDICATE_NORMAL              =  1,
1452    BRW_PREDICATE_ALIGN1_ANYV         =  2,
1453    BRW_PREDICATE_ALIGN1_ALLV         =  3,
1454    BRW_PREDICATE_ALIGN1_ANY2H        =  4,
1455    BRW_PREDICATE_ALIGN1_ALL2H        =  5,
1456    BRW_PREDICATE_ALIGN1_ANY4H        =  6,
1457    BRW_PREDICATE_ALIGN1_ALL4H        =  7,
1458    BRW_PREDICATE_ALIGN1_ANY8H        =  8,
1459    BRW_PREDICATE_ALIGN1_ALL8H        =  9,
1460    BRW_PREDICATE_ALIGN1_ANY16H       = 10,
1461    BRW_PREDICATE_ALIGN1_ALL16H       = 11,
1462    BRW_PREDICATE_ALIGN1_ANY32H       = 12,
1463    BRW_PREDICATE_ALIGN1_ALL32H       = 13,
1464    BRW_PREDICATE_ALIGN16_REPLICATE_X =  2,
1465    BRW_PREDICATE_ALIGN16_REPLICATE_Y =  3,
1466    BRW_PREDICATE_ALIGN16_REPLICATE_Z =  4,
1467    BRW_PREDICATE_ALIGN16_REPLICATE_W =  5,
1468    BRW_PREDICATE_ALIGN16_ANY4H       =  6,
1469    BRW_PREDICATE_ALIGN16_ALL4H       =  7,
1470 };
1471 
1472 enum PACKED brw_reg_file {
1473    BRW_ARCHITECTURE_REGISTER_FILE = 0,
1474    BRW_GENERAL_REGISTER_FILE      = 1,
1475    BRW_MESSAGE_REGISTER_FILE      = 2,
1476    BRW_IMMEDIATE_VALUE            = 3,
1477 
1478    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
1479    FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
1480    MRF = BRW_MESSAGE_REGISTER_FILE,
1481    IMM = BRW_IMMEDIATE_VALUE,
1482 
1483    /* These are not hardware values */
1484    VGRF,
1485    ATTR,
1486    UNIFORM, /* prog_data->params[reg] */
1487    BAD_FILE,
1488 };
1489 
1490 #define BRW_HW_REG_TYPE_UD  0
1491 #define BRW_HW_REG_TYPE_D   1
1492 #define BRW_HW_REG_TYPE_UW  2
1493 #define BRW_HW_REG_TYPE_W   3
1494 #define BRW_HW_REG_TYPE_F   7
1495 #define GEN8_HW_REG_TYPE_UQ 8
1496 #define GEN8_HW_REG_TYPE_Q  9
1497 
1498 #define BRW_HW_REG_NON_IMM_TYPE_UB  4
1499 #define BRW_HW_REG_NON_IMM_TYPE_B   5
1500 #define GEN7_HW_REG_NON_IMM_TYPE_DF 6
1501 #define GEN8_HW_REG_NON_IMM_TYPE_HF 10
1502 
1503 #define BRW_HW_REG_IMM_TYPE_UV  4 /* Gen6+ packed unsigned immediate vector */
1504 #define BRW_HW_REG_IMM_TYPE_VF  5 /* packed float immediate vector */
1505 #define BRW_HW_REG_IMM_TYPE_V   6 /* packed int imm. vector; uword dest only */
1506 #define GEN8_HW_REG_IMM_TYPE_DF 10
1507 #define GEN8_HW_REG_IMM_TYPE_HF 11
1508 
1509 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
1510  * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
1511  * and unsigned doublewords, so a new field is also available in the da3src
1512  * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
1513  * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*.
1514  */
1515 #define BRW_3SRC_TYPE_F  0
1516 #define BRW_3SRC_TYPE_D  1
1517 #define BRW_3SRC_TYPE_UD 2
1518 #define BRW_3SRC_TYPE_DF 3
1519 
1520 #define BRW_ARF_NULL                  0x00
1521 #define BRW_ARF_ADDRESS               0x10
1522 #define BRW_ARF_ACCUMULATOR           0x20
1523 #define BRW_ARF_FLAG                  0x30
1524 #define BRW_ARF_MASK                  0x40
1525 #define BRW_ARF_MASK_STACK            0x50
1526 #define BRW_ARF_MASK_STACK_DEPTH      0x60
1527 #define BRW_ARF_STATE                 0x70
1528 #define BRW_ARF_CONTROL               0x80
1529 #define BRW_ARF_NOTIFICATION_COUNT    0x90
1530 #define BRW_ARF_IP                    0xA0
1531 #define BRW_ARF_TDR                   0xB0
1532 #define BRW_ARF_TIMESTAMP             0xC0
1533 
1534 #define BRW_MRF_COMPR4			(1 << 7)
1535 
1536 #define BRW_AMASK   0
1537 #define BRW_IMASK   1
1538 #define BRW_LMASK   2
1539 #define BRW_CMASK   3
1540 
1541 
1542 
1543 #define BRW_THREAD_NORMAL     0
1544 #define BRW_THREAD_ATOMIC     1
1545 #define BRW_THREAD_SWITCH     2
1546 
1547 enum PACKED brw_vertical_stride {
1548    BRW_VERTICAL_STRIDE_0               = 0,
1549    BRW_VERTICAL_STRIDE_1               = 1,
1550    BRW_VERTICAL_STRIDE_2               = 2,
1551    BRW_VERTICAL_STRIDE_4               = 3,
1552    BRW_VERTICAL_STRIDE_8               = 4,
1553    BRW_VERTICAL_STRIDE_16              = 5,
1554    BRW_VERTICAL_STRIDE_32              = 6,
1555    BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
1556 };
1557 
1558 enum PACKED brw_width {
1559    BRW_WIDTH_1  = 0,
1560    BRW_WIDTH_2  = 1,
1561    BRW_WIDTH_4  = 2,
1562    BRW_WIDTH_8  = 3,
1563    BRW_WIDTH_16 = 4,
1564 };
1565 
1566 #define BRW_STATELESS_BUFFER_BOUNDARY_1K      0
1567 #define BRW_STATELESS_BUFFER_BOUNDARY_2K      1
1568 #define BRW_STATELESS_BUFFER_BOUNDARY_4K      2
1569 #define BRW_STATELESS_BUFFER_BOUNDARY_8K      3
1570 #define BRW_STATELESS_BUFFER_BOUNDARY_16K     4
1571 #define BRW_STATELESS_BUFFER_BOUNDARY_32K     5
1572 #define BRW_STATELESS_BUFFER_BOUNDARY_64K     6
1573 #define BRW_STATELESS_BUFFER_BOUNDARY_128K    7
1574 #define BRW_STATELESS_BUFFER_BOUNDARY_256K    8
1575 #define BRW_STATELESS_BUFFER_BOUNDARY_512K    9
1576 #define BRW_STATELESS_BUFFER_BOUNDARY_1M      10
1577 #define BRW_STATELESS_BUFFER_BOUNDARY_2M      11
1578 
1579 #define BRW_POLYGON_FACING_FRONT      0
1580 #define BRW_POLYGON_FACING_BACK       1
1581 
1582 /**
1583  * Message target: Shared Function ID for where to SEND a message.
1584  *
1585  * These are enumerated in the ISA reference under "send - Send Message".
1586  * In particular, see the following tables:
1587  * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1588  * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1589  * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1590  */
1591 enum brw_message_target {
1592    BRW_SFID_NULL                     = 0,
1593    BRW_SFID_MATH                     = 1, /* Only valid on Gen4-5 */
1594    BRW_SFID_SAMPLER                  = 2,
1595    BRW_SFID_MESSAGE_GATEWAY          = 3,
1596    BRW_SFID_DATAPORT_READ            = 4,
1597    BRW_SFID_DATAPORT_WRITE           = 5,
1598    BRW_SFID_URB                      = 6,
1599    BRW_SFID_THREAD_SPAWNER           = 7,
1600    BRW_SFID_VME                      = 8,
1601 
1602    GEN6_SFID_DATAPORT_SAMPLER_CACHE  = 4,
1603    GEN6_SFID_DATAPORT_RENDER_CACHE   = 5,
1604    GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1605 
1606    GEN7_SFID_DATAPORT_DATA_CACHE     = 10,
1607    GEN7_SFID_PIXEL_INTERPOLATOR      = 11,
1608    HSW_SFID_DATAPORT_DATA_CACHE_1    = 12,
1609    HSW_SFID_CRE                      = 13,
1610 };
1611 
1612 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE     10
1613 
1614 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32     0
1615 #define BRW_SAMPLER_RETURN_FORMAT_UINT32      2
1616 #define BRW_SAMPLER_RETURN_FORMAT_SINT32      3
1617 
1618 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE              0
1619 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE             0
1620 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS        0
1621 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX             1
1622 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD        1
1623 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD         1
1624 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS  2
1625 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS    2
1626 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE    0
1627 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE     2
1628 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1629 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1630 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE  1
1631 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO           2
1632 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO            2
1633 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD                3
1634 #define BRW_SAMPLER_MESSAGE_SIMD8_LD                  3
1635 #define BRW_SAMPLER_MESSAGE_SIMD16_LD                 3
1636 
1637 #define GEN5_SAMPLER_MESSAGE_SAMPLE              0
1638 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS         1
1639 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD          2
1640 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE      3
1641 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS       4
1642 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1643 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE  6
1644 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD           7
1645 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4      8
1646 #define GEN5_SAMPLER_MESSAGE_LOD                 9
1647 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO      10
1648 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO   11
1649 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C    16
1650 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO   17
1651 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1652 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1653 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ           24
1654 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ         25
1655 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ        26
1656 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W     28
1657 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS       29
1658 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS       30
1659 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS       31
1660 
1661 /* for GEN5 only */
1662 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2                   0
1663 #define BRW_SAMPLER_SIMD_MODE_SIMD8                     1
1664 #define BRW_SAMPLER_SIMD_MODE_SIMD16                    2
1665 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64                 3
1666 
1667 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1668  * behavior by setting bit 22 of dword 2 in the message header. */
1669 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D                   0
1670 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2        (1 << 22)
1671 
1672 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW   0
1673 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH  1
1674 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS     2
1675 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS     3
1676 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS     4
1677 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n)              \
1678    ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW :    \
1679     (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS :      \
1680     (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS :     \
1681     (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS :     \
1682     (abort(), ~0))
1683 
1684 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD     0
1685 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS    2
1686 
1687 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS   2
1688 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS  3
1689 
1690 /* This one stays the same across generations. */
1691 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ          0
1692 /* GEN4 */
1693 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     1
1694 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          2
1695 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      3
1696 /* G45, GEN5 */
1697 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ	    1
1698 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1699 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ	    3
1700 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1701 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1702 /* GEN6 */
1703 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ	    1
1704 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1705 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1706 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ  5
1707 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1708 
1709 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE      0
1710 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE    1
1711 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE   2
1712 
1713 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE                0
1714 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED     1
1715 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01         2
1716 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23         3
1717 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01       4
1718 
1719 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE                0
1720 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE           1
1721 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE                2
1722 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE            3
1723 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE              4
1724 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE     5
1725 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE               7
1726 
1727 /* GEN6 */
1728 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE              7
1729 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE               8
1730 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE          9
1731 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE               10
1732 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE           11
1733 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE             12
1734 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE               13
1735 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE       14
1736 
1737 /* GEN7 */
1738 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ                           4
1739 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ                         5
1740 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP                            6
1741 #define GEN7_DATAPORT_RC_MEMORY_FENCE                               7
1742 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE                          10
1743 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1744 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE                        13
1745 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ                           0
1746 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ                 1
1747 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ                      2
1748 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ                       3
1749 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ                        4
1750 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ                       5
1751 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP                          6
1752 #define GEN7_DATAPORT_DC_MEMORY_FENCE                               7
1753 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE                          8
1754 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE                     10
1755 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE                      11
1756 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE                       12
1757 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE                      13
1758 
1759 #define GEN7_DATAPORT_SCRATCH_READ                            ((1 << 18) | \
1760                                                                (0 << 17))
1761 #define GEN7_DATAPORT_SCRATCH_WRITE                           ((1 << 18) | \
1762                                                                (1 << 17))
1763 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT                        12
1764 
1765 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET     0
1766 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE            1
1767 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID          2
1768 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET   3
1769 
1770 /* HSW */
1771 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ                      0
1772 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ            1
1773 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ                 2
1774 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ                  3
1775 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ                   4
1776 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE                          7
1777 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE                     8
1778 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE                10
1779 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE                 11
1780 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE                  12
1781 
1782 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ                  1
1783 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP                     2
1784 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2             3
1785 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ                      4
1786 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ                    5
1787 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP                       6
1788 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2               7
1789 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE                 9
1790 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE                     10
1791 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP                     11
1792 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2             12
1793 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE                   13
1794 
1795 /* GEN9 */
1796 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1797 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ                         13
1798 
1799 /* Dataport special binding table indices: */
1800 #define BRW_BTI_STATELESS                255
1801 #define GEN7_BTI_SLM                     254
1802 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1803  * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1804  * CHV and at least some pre-production steppings of SKL due to
1805  * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1806  * kernel to be non-coherent (matching the behavior of the same BTI on
1807  * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1808  */
1809 #define GEN8_BTI_STATELESS_IA_COHERENT   255
1810 #define GEN8_BTI_STATELESS_NON_COHERENT  253
1811 
1812 /* dataport atomic operations. */
1813 #define BRW_AOP_AND                   1
1814 #define BRW_AOP_OR                    2
1815 #define BRW_AOP_XOR                   3
1816 #define BRW_AOP_MOV                   4
1817 #define BRW_AOP_INC                   5
1818 #define BRW_AOP_DEC                   6
1819 #define BRW_AOP_ADD                   7
1820 #define BRW_AOP_SUB                   8
1821 #define BRW_AOP_REVSUB                9
1822 #define BRW_AOP_IMAX                  10
1823 #define BRW_AOP_IMIN                  11
1824 #define BRW_AOP_UMAX                  12
1825 #define BRW_AOP_UMIN                  13
1826 #define BRW_AOP_CMPWR                 14
1827 #define BRW_AOP_PREDEC                15
1828 
1829 #define BRW_MATH_FUNCTION_INV                              1
1830 #define BRW_MATH_FUNCTION_LOG                              2
1831 #define BRW_MATH_FUNCTION_EXP                              3
1832 #define BRW_MATH_FUNCTION_SQRT                             4
1833 #define BRW_MATH_FUNCTION_RSQ                              5
1834 #define BRW_MATH_FUNCTION_SIN                              6
1835 #define BRW_MATH_FUNCTION_COS                              7
1836 #define BRW_MATH_FUNCTION_SINCOS                           8 /* gen4, gen5 */
1837 #define BRW_MATH_FUNCTION_FDIV                             9 /* gen6+ */
1838 #define BRW_MATH_FUNCTION_POW                              10
1839 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER   11
1840 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT                 12
1841 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER                13
1842 #define GEN8_MATH_FUNCTION_INVM                            14
1843 #define GEN8_MATH_FUNCTION_RSQRTM                          15
1844 
1845 #define BRW_MATH_INTEGER_UNSIGNED     0
1846 #define BRW_MATH_INTEGER_SIGNED       1
1847 
1848 #define BRW_MATH_PRECISION_FULL        0
1849 #define BRW_MATH_PRECISION_PARTIAL     1
1850 
1851 #define BRW_MATH_SATURATE_NONE         0
1852 #define BRW_MATH_SATURATE_SATURATE     1
1853 
1854 #define BRW_MATH_DATA_VECTOR  0
1855 #define BRW_MATH_DATA_SCALAR  1
1856 
1857 #define BRW_URB_OPCODE_WRITE_HWORD  0
1858 #define BRW_URB_OPCODE_WRITE_OWORD  1
1859 #define BRW_URB_OPCODE_READ_HWORD   2
1860 #define BRW_URB_OPCODE_READ_OWORD   3
1861 #define GEN7_URB_OPCODE_ATOMIC_MOV  4
1862 #define GEN7_URB_OPCODE_ATOMIC_INC  5
1863 #define GEN8_URB_OPCODE_ATOMIC_ADD  6
1864 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1865 #define GEN8_URB_OPCODE_SIMD8_READ  8
1866 
1867 #define BRW_URB_SWIZZLE_NONE          0
1868 #define BRW_URB_SWIZZLE_INTERLEAVE    1
1869 #define BRW_URB_SWIZZLE_TRANSPOSE     2
1870 
1871 #define BRW_SCRATCH_SPACE_SIZE_1K     0
1872 #define BRW_SCRATCH_SPACE_SIZE_2K     1
1873 #define BRW_SCRATCH_SPACE_SIZE_4K     2
1874 #define BRW_SCRATCH_SPACE_SIZE_8K     3
1875 #define BRW_SCRATCH_SPACE_SIZE_16K    4
1876 #define BRW_SCRATCH_SPACE_SIZE_32K    5
1877 #define BRW_SCRATCH_SPACE_SIZE_64K    6
1878 #define BRW_SCRATCH_SPACE_SIZE_128K   7
1879 #define BRW_SCRATCH_SPACE_SIZE_256K   8
1880 #define BRW_SCRATCH_SPACE_SIZE_512K   9
1881 #define BRW_SCRATCH_SPACE_SIZE_1M     10
1882 #define BRW_SCRATCH_SPACE_SIZE_2M     11
1883 
1884 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY         0
1885 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY        1
1886 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG          2
1887 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP        3
1888 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG          4
1889 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1890 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE      6
1891 
1892 
1893 #define CMD_URB_FENCE                 0x6000
1894 #define CMD_CS_URB_STATE              0x6001
1895 #define CMD_CONST_BUFFER              0x6002
1896 
1897 #define CMD_STATE_BASE_ADDRESS        0x6101
1898 #define CMD_STATE_SIP                 0x6102
1899 #define CMD_PIPELINE_SELECT_965       0x6104
1900 #define CMD_PIPELINE_SELECT_GM45      0x6904
1901 
1902 #define _3DSTATE_PIPELINED_POINTERS		0x7800
1903 #define _3DSTATE_BINDING_TABLE_POINTERS		0x7801
1904 # define GEN6_BINDING_TABLE_MODIFY_VS	(1 << 8)
1905 # define GEN6_BINDING_TABLE_MODIFY_GS	(1 << 9)
1906 # define GEN6_BINDING_TABLE_MODIFY_PS	(1 << 12)
1907 
1908 #define _3DSTATE_BINDING_TABLE_POINTERS_VS	0x7826 /* GEN7+ */
1909 #define _3DSTATE_BINDING_TABLE_POINTERS_HS	0x7827 /* GEN7+ */
1910 #define _3DSTATE_BINDING_TABLE_POINTERS_DS	0x7828 /* GEN7+ */
1911 #define _3DSTATE_BINDING_TABLE_POINTERS_GS	0x7829 /* GEN7+ */
1912 #define _3DSTATE_BINDING_TABLE_POINTERS_PS	0x782A /* GEN7+ */
1913 
1914 #define _3DSTATE_BINDING_TABLE_POOL_ALLOC       0x7919 /* GEN7.5+ */
1915 #define BRW_HW_BINDING_TABLE_ENABLE             (1 << 11)
1916 #define GEN7_HW_BT_POOL_MOCS_SHIFT              7
1917 #define GEN7_HW_BT_POOL_MOCS_MASK               INTEL_MASK(10, 7)
1918 #define GEN8_HW_BT_POOL_MOCS_SHIFT              0
1919 #define GEN8_HW_BT_POOL_MOCS_MASK               INTEL_MASK(6, 0)
1920 /* Only required in HSW */
1921 #define HSW_BT_POOL_ALLOC_MUST_BE_ONE           (3 << 5)
1922 
1923 #define _3DSTATE_BINDING_TABLE_EDIT_VS          0x7843 /* GEN7.5 */
1924 #define _3DSTATE_BINDING_TABLE_EDIT_GS          0x7844 /* GEN7.5 */
1925 #define _3DSTATE_BINDING_TABLE_EDIT_HS          0x7845 /* GEN7.5 */
1926 #define _3DSTATE_BINDING_TABLE_EDIT_DS          0x7846 /* GEN7.5 */
1927 #define _3DSTATE_BINDING_TABLE_EDIT_PS          0x7847 /* GEN7.5 */
1928 #define BRW_BINDING_TABLE_INDEX_SHIFT           16
1929 #define BRW_BINDING_TABLE_INDEX_MASK            INTEL_MASK(23, 16)
1930 
1931 #define BRW_BINDING_TABLE_EDIT_TARGET_ALL       3
1932 #define BRW_BINDING_TABLE_EDIT_TARGET_CORE1     2
1933 #define BRW_BINDING_TABLE_EDIT_TARGET_CORE0     1
1934 /* In HSW, when editing binding table entries to surface state offsets,
1935  * the surface state offset is a 16-bit value aligned to 32 bytes. But
1936  * Surface State Pointer in dword 2 is [15:0]. Right shift surf_offset
1937  * by 5 bits so it won't disturb bit 16 (which is used as the binding
1938  * table index entry), otherwise it would hang the GPU.
1939  */
1940 #define HSW_SURFACE_STATE_EDIT(value)           (value >> 5)
1941 /* Same as Haswell, but surface state offsets now aligned to 64 bytes.*/
1942 #define GEN8_SURFACE_STATE_EDIT(value)          (value >> 6)
1943 
1944 #define _3DSTATE_SAMPLER_STATE_POINTERS		0x7802 /* GEN6+ */
1945 # define PS_SAMPLER_STATE_CHANGE				(1 << 12)
1946 # define GS_SAMPLER_STATE_CHANGE				(1 << 9)
1947 # define VS_SAMPLER_STATE_CHANGE				(1 << 8)
1948 /* DW1: VS */
1949 /* DW2: GS */
1950 /* DW3: PS */
1951 
1952 #define _3DSTATE_SAMPLER_STATE_POINTERS_VS	0x782B /* GEN7+ */
1953 #define _3DSTATE_SAMPLER_STATE_POINTERS_HS	0x782C /* GEN7+ */
1954 #define _3DSTATE_SAMPLER_STATE_POINTERS_DS	0x782D /* GEN7+ */
1955 #define _3DSTATE_SAMPLER_STATE_POINTERS_GS	0x782E /* GEN7+ */
1956 #define _3DSTATE_SAMPLER_STATE_POINTERS_PS	0x782F /* GEN7+ */
1957 
1958 #define _3DSTATE_VERTEX_BUFFERS       0x7808
1959 # define BRW_VB0_INDEX_SHIFT		27
1960 # define GEN6_VB0_INDEX_SHIFT		26
1961 # define BRW_VB0_ACCESS_VERTEXDATA	(0 << 26)
1962 # define BRW_VB0_ACCESS_INSTANCEDATA	(1 << 26)
1963 # define GEN6_VB0_ACCESS_VERTEXDATA	(0 << 20)
1964 # define GEN6_VB0_ACCESS_INSTANCEDATA	(1 << 20)
1965 # define GEN7_VB0_ADDRESS_MODIFYENABLE  (1 << 14)
1966 # define BRW_VB0_PITCH_SHIFT		0
1967 
1968 #define _3DSTATE_VERTEX_ELEMENTS      0x7809
1969 # define BRW_VE0_INDEX_SHIFT		27
1970 # define GEN6_VE0_INDEX_SHIFT		26
1971 # define BRW_VE0_FORMAT_SHIFT		16
1972 # define BRW_VE0_VALID			(1 << 26)
1973 # define GEN6_VE0_VALID			(1 << 25)
1974 # define GEN6_VE0_EDGE_FLAG_ENABLE	(1 << 15)
1975 # define BRW_VE0_SRC_OFFSET_SHIFT	0
1976 # define BRW_VE1_COMPONENT_NOSTORE	0
1977 # define BRW_VE1_COMPONENT_STORE_SRC	1
1978 # define BRW_VE1_COMPONENT_STORE_0	2
1979 # define BRW_VE1_COMPONENT_STORE_1_FLT	3
1980 # define BRW_VE1_COMPONENT_STORE_1_INT	4
1981 # define BRW_VE1_COMPONENT_STORE_VID	5
1982 # define BRW_VE1_COMPONENT_STORE_IID	6
1983 # define BRW_VE1_COMPONENT_STORE_PID	7
1984 # define BRW_VE1_COMPONENT_0_SHIFT	28
1985 # define BRW_VE1_COMPONENT_1_SHIFT	24
1986 # define BRW_VE1_COMPONENT_2_SHIFT	20
1987 # define BRW_VE1_COMPONENT_3_SHIFT	16
1988 # define BRW_VE1_DST_OFFSET_SHIFT	0
1989 
1990 #define CMD_INDEX_BUFFER              0x780a
1991 #define GEN4_3DSTATE_VF_STATISTICS		0x780b
1992 #define GM45_3DSTATE_VF_STATISTICS		0x680b
1993 #define _3DSTATE_CC_STATE_POINTERS		0x780e /* GEN6+ */
1994 #define _3DSTATE_BLEND_STATE_POINTERS		0x7824 /* GEN7+ */
1995 #define _3DSTATE_DEPTH_STENCIL_STATE_POINTERS	0x7825 /* GEN7+ */
1996 
1997 #define _3DSTATE_URB				0x7805 /* GEN6 */
1998 # define GEN6_URB_VS_SIZE_SHIFT				16
1999 # define GEN6_URB_VS_ENTRIES_SHIFT			0
2000 # define GEN6_URB_GS_ENTRIES_SHIFT			8
2001 # define GEN6_URB_GS_SIZE_SHIFT				0
2002 
2003 #define _3DSTATE_VF                             0x780c /* GEN7.5+ */
2004 #define HSW_CUT_INDEX_ENABLE                            (1 << 8)
2005 
2006 #define _3DSTATE_VF_INSTANCING                  0x7849 /* GEN8+ */
2007 # define GEN8_VF_INSTANCING_ENABLE                      (1 << 8)
2008 
2009 #define _3DSTATE_VF_SGVS                        0x784a /* GEN8+ */
2010 # define GEN8_SGVS_ENABLE_INSTANCE_ID                   (1 << 31)
2011 # define GEN8_SGVS_INSTANCE_ID_COMPONENT_SHIFT          29
2012 # define GEN8_SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT     16
2013 # define GEN8_SGVS_ENABLE_VERTEX_ID                     (1 << 15)
2014 # define GEN8_SGVS_VERTEX_ID_COMPONENT_SHIFT            13
2015 # define GEN8_SGVS_VERTEX_ID_ELEMENT_OFFSET_SHIFT       0
2016 
2017 #define _3DSTATE_VF_TOPOLOGY                    0x784b /* GEN8+ */
2018 
2019 #define _3DSTATE_WM_CHROMAKEY			0x784c /* GEN8+ */
2020 
2021 #define _3DSTATE_URB_VS                         0x7830 /* GEN7+ */
2022 #define _3DSTATE_URB_HS                         0x7831 /* GEN7+ */
2023 #define _3DSTATE_URB_DS                         0x7832 /* GEN7+ */
2024 #define _3DSTATE_URB_GS                         0x7833 /* GEN7+ */
2025 # define GEN7_URB_ENTRY_SIZE_SHIFT                      16
2026 # define GEN7_URB_STARTING_ADDRESS_SHIFT                25
2027 
2028 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
2029  * is 2^9, or 512.  It's counted in multiples of 64 bytes.
2030  *
2031  * Identical for VS, DS, and HS.
2032  */
2033 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES                (512*64)
2034 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES                (512*64)
2035 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES                (512*64)
2036 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES                (512*64)
2037 
2038 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
2039  * (128 bytes) URB rows and the maximum allowed value is 5 rows.
2040  */
2041 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES                (5*128)
2042 
2043 #define _3DSTATE_PUSH_CONSTANT_ALLOC_VS         0x7912 /* GEN7+ */
2044 #define _3DSTATE_PUSH_CONSTANT_ALLOC_HS         0x7913 /* GEN7+ */
2045 #define _3DSTATE_PUSH_CONSTANT_ALLOC_DS         0x7914 /* GEN7+ */
2046 #define _3DSTATE_PUSH_CONSTANT_ALLOC_GS         0x7915 /* GEN7+ */
2047 #define _3DSTATE_PUSH_CONSTANT_ALLOC_PS         0x7916 /* GEN7+ */
2048 # define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT         16
2049 
2050 #define _3DSTATE_VIEWPORT_STATE_POINTERS	0x780d /* GEN6+ */
2051 # define GEN6_CC_VIEWPORT_MODIFY			(1 << 12)
2052 # define GEN6_SF_VIEWPORT_MODIFY			(1 << 11)
2053 # define GEN6_CLIP_VIEWPORT_MODIFY			(1 << 10)
2054 # define GEN6_NUM_VIEWPORTS				16
2055 
2056 #define _3DSTATE_VIEWPORT_STATE_POINTERS_CC	0x7823 /* GEN7+ */
2057 #define _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL	0x7821 /* GEN7+ */
2058 
2059 #define _3DSTATE_SCISSOR_STATE_POINTERS		0x780f /* GEN6+ */
2060 
2061 #define _3DSTATE_VS				0x7810 /* GEN6+ */
2062 /* DW2 */
2063 # define GEN6_VS_SPF_MODE				(1 << 31)
2064 # define GEN6_VS_VECTOR_MASK_ENABLE			(1 << 30)
2065 # define GEN6_VS_SAMPLER_COUNT_SHIFT			27
2066 # define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
2067 # define GEN6_VS_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
2068 # define GEN6_VS_FLOATING_POINT_MODE_ALT		(1 << 16)
2069 # define HSW_VS_UAV_ACCESS_ENABLE                       (1 << 12)
2070 /* DW4 */
2071 # define GEN6_VS_DISPATCH_START_GRF_SHIFT		20
2072 # define GEN6_VS_URB_READ_LENGTH_SHIFT			11
2073 # define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT		4
2074 /* DW5 */
2075 # define GEN6_VS_MAX_THREADS_SHIFT			25
2076 # define HSW_VS_MAX_THREADS_SHIFT			23
2077 # define GEN6_VS_STATISTICS_ENABLE			(1 << 10)
2078 # define GEN6_VS_CACHE_DISABLE				(1 << 1)
2079 # define GEN6_VS_ENABLE					(1 << 0)
2080 /* Gen8+ DW7 */
2081 # define GEN8_VS_SIMD8_ENABLE                           (1 << 2)
2082 /* Gen8+ DW8 */
2083 # define GEN8_VS_URB_ENTRY_OUTPUT_OFFSET_SHIFT          21
2084 # define GEN8_VS_URB_OUTPUT_LENGTH_SHIFT                16
2085 # define GEN8_VS_USER_CLIP_DISTANCE_SHIFT               8
2086 
2087 #define _3DSTATE_GS		      		0x7811 /* GEN6+ */
2088 /* DW2 */
2089 # define GEN6_GS_SPF_MODE				(1 << 31)
2090 # define GEN6_GS_VECTOR_MASK_ENABLE			(1 << 30)
2091 # define GEN6_GS_SAMPLER_COUNT_SHIFT			27
2092 # define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
2093 # define GEN6_GS_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
2094 # define GEN6_GS_FLOATING_POINT_MODE_ALT		(1 << 16)
2095 # define HSW_GS_UAV_ACCESS_ENABLE       		(1 << 12)
2096 /* DW4 */
2097 # define GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT		23
2098 # define GEN7_GS_OUTPUT_TOPOLOGY_SHIFT			17
2099 # define GEN6_GS_URB_READ_LENGTH_SHIFT			11
2100 # define GEN7_GS_INCLUDE_VERTEX_HANDLES		        (1 << 10)
2101 # define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT		4
2102 # define GEN6_GS_DISPATCH_START_GRF_SHIFT		0
2103 /* DW5 */
2104 # define GEN6_GS_MAX_THREADS_SHIFT			25
2105 # define HSW_GS_MAX_THREADS_SHIFT			24
2106 # define IVB_GS_CONTROL_DATA_FORMAT_SHIFT		24
2107 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT		0
2108 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID		1
2109 # define GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT		20
2110 # define GEN7_GS_INSTANCE_CONTROL_SHIFT			15
2111 # define GEN7_GS_DISPATCH_MODE_SHIFT                    11
2112 # define GEN7_GS_DISPATCH_MODE_MASK                     INTEL_MASK(12, 11)
2113 # define GEN6_GS_STATISTICS_ENABLE			(1 << 10)
2114 # define GEN6_GS_SO_STATISTICS_ENABLE			(1 << 9)
2115 # define GEN6_GS_RENDERING_ENABLE			(1 << 8)
2116 # define GEN7_GS_INCLUDE_PRIMITIVE_ID			(1 << 4)
2117 # define GEN7_GS_REORDER_TRAILING			(1 << 2)
2118 # define GEN7_GS_ENABLE					(1 << 0)
2119 /* DW6 */
2120 # define HSW_GS_CONTROL_DATA_FORMAT_SHIFT		31
2121 # define GEN6_GS_REORDER				(1 << 30)
2122 # define GEN6_GS_DISCARD_ADJACENCY			(1 << 29)
2123 # define GEN6_GS_SVBI_PAYLOAD_ENABLE			(1 << 28)
2124 # define GEN6_GS_SVBI_POSTINCREMENT_ENABLE		(1 << 27)
2125 # define GEN6_GS_SVBI_POSTINCREMENT_VALUE_SHIFT		16
2126 # define GEN6_GS_SVBI_POSTINCREMENT_VALUE_MASK		INTEL_MASK(25, 16)
2127 # define GEN6_GS_ENABLE					(1 << 15)
2128 
2129 /* Gen8+ DW8 */
2130 # define GEN8_GS_STATIC_OUTPUT                          (1 << 30)
2131 # define GEN8_GS_STATIC_VERTEX_COUNT_SHIFT              16
2132 # define GEN8_GS_STATIC_VERTEX_COUNT_MASK               INTEL_MASK(26, 16)
2133 
2134 /* Gen8+ DW9 */
2135 # define GEN8_GS_URB_ENTRY_OUTPUT_OFFSET_SHIFT          21
2136 # define GEN8_GS_URB_OUTPUT_LENGTH_SHIFT                16
2137 # define GEN8_GS_USER_CLIP_DISTANCE_SHIFT               8
2138 
2139 # define BRW_GS_EDGE_INDICATOR_0			(1 << 8)
2140 # define BRW_GS_EDGE_INDICATOR_1			(1 << 9)
2141 
2142 /* GS Thread Payload
2143  */
2144 /* R0 */
2145 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT		27
2146 
2147 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62.  It's
2148  * counted in multiples of 16 bytes.
2149  */
2150 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES		(62*16)
2151 
2152 #define _3DSTATE_HS                             0x781B /* GEN7+ */
2153 /* DW1 */
2154 # define GEN7_HS_SAMPLER_COUNT_MASK                     INTEL_MASK(29, 27)
2155 # define GEN7_HS_SAMPLER_COUNT_SHIFT                    27
2156 # define GEN7_HS_BINDING_TABLE_ENTRY_COUNT_MASK         INTEL_MASK(25, 18)
2157 # define GEN7_HS_BINDING_TABLE_ENTRY_COUNT_SHIFT        18
2158 # define GEN7_HS_FLOATING_POINT_MODE_IEEE_754           (0 << 16)
2159 # define GEN7_HS_FLOATING_POINT_MODE_ALT                (1 << 16)
2160 # define GEN7_HS_MAX_THREADS_SHIFT                      0
2161 /* DW2 */
2162 # define GEN7_HS_ENABLE                                 (1 << 31)
2163 # define GEN7_HS_STATISTICS_ENABLE                      (1 << 29)
2164 # define GEN8_HS_MAX_THREADS_SHIFT                      8
2165 # define GEN7_HS_INSTANCE_COUNT_MASK                    INTEL_MASK(3, 0)
2166 # define GEN7_HS_INSTANCE_COUNT_SHIFT                   0
2167 /* DW5 */
2168 # define GEN7_HS_SINGLE_PROGRAM_FLOW                    (1 << 27)
2169 # define GEN7_HS_VECTOR_MASK_ENABLE                     (1 << 26)
2170 # define HSW_HS_ACCESSES_UAV                            (1 << 25)
2171 # define GEN7_HS_INCLUDE_VERTEX_HANDLES                 (1 << 24)
2172 # define GEN7_HS_DISPATCH_START_GRF_MASK                INTEL_MASK(23, 19)
2173 # define GEN7_HS_DISPATCH_START_GRF_SHIFT               19
2174 # define GEN7_HS_URB_READ_LENGTH_MASK                   INTEL_MASK(16, 11)
2175 # define GEN7_HS_URB_READ_LENGTH_SHIFT                  11
2176 # define GEN7_HS_URB_ENTRY_READ_OFFSET_MASK             INTEL_MASK(9, 4)
2177 # define GEN7_HS_URB_ENTRY_READ_OFFSET_SHIFT            4
2178 
2179 #define _3DSTATE_TE                             0x781C /* GEN7+ */
2180 /* DW1 */
2181 # define GEN7_TE_PARTITIONING_SHIFT                     12
2182 # define GEN7_TE_OUTPUT_TOPOLOGY_SHIFT                  8
2183 # define GEN7_TE_DOMAIN_SHIFT                           4
2184 //# define GEN7_TE_MODE_SW                                (1 << 1)
2185 # define GEN7_TE_ENABLE                                 (1 << 0)
2186 
2187 #define _3DSTATE_DS                             0x781D /* GEN7+ */
2188 /* DW2 */
2189 # define GEN7_DS_SINGLE_DOMAIN_POINT_DISPATCH           (1 << 31)
2190 # define GEN7_DS_VECTOR_MASK_ENABLE                     (1 << 30)
2191 # define GEN7_DS_SAMPLER_COUNT_MASK                     INTEL_MASK(29, 27)
2192 # define GEN7_DS_SAMPLER_COUNT_SHIFT                    27
2193 # define GEN7_DS_BINDING_TABLE_ENTRY_COUNT_MASK         INTEL_MASK(25, 18)
2194 # define GEN7_DS_BINDING_TABLE_ENTRY_COUNT_SHIFT        18
2195 # define GEN7_DS_FLOATING_POINT_MODE_IEEE_754           (0 << 16)
2196 # define GEN7_DS_FLOATING_POINT_MODE_ALT                (1 << 16)
2197 # define HSW_DS_ACCESSES_UAV                            (1 << 14)
2198 /* DW4 */
2199 # define GEN7_DS_DISPATCH_START_GRF_MASK                INTEL_MASK(24, 20)
2200 # define GEN7_DS_DISPATCH_START_GRF_SHIFT               20
2201 # define GEN7_DS_URB_READ_LENGTH_MASK                   INTEL_MASK(17, 11)
2202 # define GEN7_DS_URB_READ_LENGTH_SHIFT                  11
2203 # define GEN7_DS_URB_ENTRY_READ_OFFSET_MASK             INTEL_MASK(9, 4)
2204 # define GEN7_DS_URB_ENTRY_READ_OFFSET_SHIFT            4
2205 /* DW5 */
2206 # define GEN7_DS_MAX_THREADS_SHIFT                      25
2207 # define HSW_DS_MAX_THREADS_SHIFT                       21
2208 # define GEN7_DS_STATISTICS_ENABLE                      (1 << 10)
2209 # define GEN7_DS_SIMD8_DISPATCH_ENABLE                  (1 << 3)
2210 # define GEN7_DS_COMPUTE_W_COORDINATE_ENABLE            (1 << 2)
2211 # define GEN7_DS_CACHE_DISABLE                          (1 << 1)
2212 # define GEN7_DS_ENABLE                                 (1 << 0)
2213 /* Gen8+ DW8 */
2214 # define GEN8_DS_URB_ENTRY_OUTPUT_OFFSET_MASK           INTEL_MASK(26, 21)
2215 # define GEN8_DS_URB_ENTRY_OUTPUT_OFFSET_SHIFT          21
2216 # define GEN8_DS_URB_OUTPUT_LENGTH_MASK                 INTEL_MASK(20, 16)
2217 # define GEN8_DS_URB_OUTPUT_LENGTH_SHIFT                16
2218 # define GEN8_DS_USER_CLIP_DISTANCE_MASK                INTEL_MASK(15, 8)
2219 # define GEN8_DS_USER_CLIP_DISTANCE_SHIFT               8
2220 # define GEN8_DS_USER_CULL_DISTANCE_MASK                INTEL_MASK(7, 0)
2221 # define GEN8_DS_USER_CULL_DISTANCE_SHIFT               0
2222 
2223 
2224 #define _3DSTATE_CLIP				0x7812 /* GEN6+ */
2225 /* DW1 */
2226 # define GEN7_CLIP_WINDING_CW                           (0 << 20)
2227 # define GEN7_CLIP_WINDING_CCW                          (1 << 20)
2228 # define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_8          (0 << 19)
2229 # define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_4          (1 << 19)
2230 # define GEN7_CLIP_EARLY_CULL                           (1 << 18)
2231 # define GEN8_CLIP_FORCE_USER_CLIP_DISTANCE_BITMASK     (1 << 17)
2232 # define GEN7_CLIP_CULLMODE_BOTH                        (0 << 16)
2233 # define GEN7_CLIP_CULLMODE_NONE                        (1 << 16)
2234 # define GEN7_CLIP_CULLMODE_FRONT                       (2 << 16)
2235 # define GEN7_CLIP_CULLMODE_BACK                        (3 << 16)
2236 # define GEN6_CLIP_STATISTICS_ENABLE			(1 << 10)
2237 /**
2238  * Just does cheap culling based on the clip distance.  Bits must be
2239  * disjoint with USER_CLIP_CLIP_DISTANCE bits.
2240  */
2241 # define GEN6_USER_CLIP_CULL_DISTANCES_SHIFT		0
2242 /* DW2 */
2243 # define GEN6_CLIP_ENABLE				(1 << 31)
2244 # define GEN6_CLIP_API_OGL				(0 << 30)
2245 # define GEN6_CLIP_API_D3D				(1 << 30)
2246 # define GEN6_CLIP_XY_TEST				(1 << 28)
2247 # define GEN6_CLIP_Z_TEST				(1 << 27)
2248 # define GEN6_CLIP_GB_TEST				(1 << 26)
2249 /** 8-bit field of which user clip distances to clip aganist. */
2250 # define GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT		16
2251 # define GEN6_CLIP_MODE_NORMAL				(0 << 13)
2252 # define GEN6_CLIP_MODE_REJECT_ALL			(3 << 13)
2253 # define GEN6_CLIP_MODE_ACCEPT_ALL			(4 << 13)
2254 # define GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE		(1 << 9)
2255 # define GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE	(1 << 8)
2256 # define GEN6_CLIP_TRI_PROVOKE_SHIFT			4
2257 # define GEN6_CLIP_LINE_PROVOKE_SHIFT			2
2258 # define GEN6_CLIP_TRIFAN_PROVOKE_SHIFT			0
2259 /* DW3 */
2260 # define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT		17
2261 # define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT		6
2262 # define GEN6_CLIP_FORCE_ZERO_RTAINDEX			(1 << 5)
2263 # define GEN6_CLIP_MAX_VP_INDEX_MASK			INTEL_MASK(3, 0)
2264 
2265 #define _3DSTATE_SF				0x7813 /* GEN6+ */
2266 /* DW1 (for gen6) */
2267 # define GEN6_SF_NUM_OUTPUTS_SHIFT			22
2268 # define GEN6_SF_SWIZZLE_ENABLE				(1 << 21)
2269 # define GEN6_SF_POINT_SPRITE_UPPERLEFT			(0 << 20)
2270 # define GEN6_SF_POINT_SPRITE_LOWERLEFT			(1 << 20)
2271 # define GEN9_SF_LINE_WIDTH_SHIFT			12 /* U11.7 */
2272 # define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT		11
2273 # define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT		4
2274 /* DW2 */
2275 # define GEN6_SF_LEGACY_GLOBAL_DEPTH_BIAS		(1 << 11)
2276 # define GEN6_SF_STATISTICS_ENABLE			(1 << 10)
2277 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID		(1 << 9)
2278 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME		(1 << 8)
2279 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT		(1 << 7)
2280 # define GEN6_SF_FRONT_SOLID				(0 << 5)
2281 # define GEN6_SF_FRONT_WIREFRAME			(1 << 5)
2282 # define GEN6_SF_FRONT_POINT				(2 << 5)
2283 # define GEN6_SF_BACK_SOLID				(0 << 3)
2284 # define GEN6_SF_BACK_WIREFRAME				(1 << 3)
2285 # define GEN6_SF_BACK_POINT				(2 << 3)
2286 # define GEN6_SF_VIEWPORT_TRANSFORM_ENABLE		(1 << 1)
2287 # define GEN6_SF_WINDING_CCW				(1 << 0)
2288 /* DW3 */
2289 # define GEN6_SF_LINE_AA_ENABLE				(1 << 31)
2290 # define GEN6_SF_CULL_BOTH				(0 << 29)
2291 # define GEN6_SF_CULL_NONE				(1 << 29)
2292 # define GEN6_SF_CULL_FRONT				(2 << 29)
2293 # define GEN6_SF_CULL_BACK				(3 << 29)
2294 # define GEN6_SF_LINE_WIDTH_SHIFT			18 /* U3.7 */
2295 # define GEN6_SF_LINE_END_CAP_WIDTH_0_5			(0 << 16)
2296 # define GEN6_SF_LINE_END_CAP_WIDTH_1_0			(1 << 16)
2297 # define GEN6_SF_LINE_END_CAP_WIDTH_2_0			(2 << 16)
2298 # define GEN6_SF_LINE_END_CAP_WIDTH_4_0			(3 << 16)
2299 # define GEN6_SF_SCISSOR_ENABLE				(1 << 11)
2300 # define GEN6_SF_MSRAST_OFF_PIXEL			(0 << 8)
2301 # define GEN6_SF_MSRAST_OFF_PATTERN			(1 << 8)
2302 # define GEN6_SF_MSRAST_ON_PIXEL			(2 << 8)
2303 # define GEN6_SF_MSRAST_ON_PATTERN			(3 << 8)
2304 /* DW4 */
2305 # define GEN6_SF_TRI_PROVOKE_SHIFT			29
2306 # define GEN6_SF_LINE_PROVOKE_SHIFT			27
2307 # define GEN6_SF_TRIFAN_PROVOKE_SHIFT			25
2308 # define GEN6_SF_LINE_AA_MODE_MANHATTAN			(0 << 14)
2309 # define GEN6_SF_LINE_AA_MODE_TRUE			(1 << 14)
2310 # define GEN6_SF_VERTEX_SUBPIXEL_8BITS			(0 << 12)
2311 # define GEN6_SF_VERTEX_SUBPIXEL_4BITS			(1 << 12)
2312 # define GEN6_SF_USE_STATE_POINT_WIDTH			(1 << 11)
2313 # define GEN6_SF_POINT_WIDTH_SHIFT			0 /* U8.3 */
2314 /* DW5: depth offset constant */
2315 /* DW6: depth offset scale */
2316 /* DW7: depth offset clamp */
2317 /* DW8 */
2318 # define ATTRIBUTE_1_OVERRIDE_W				(1 << 31)
2319 # define ATTRIBUTE_1_OVERRIDE_Z				(1 << 30)
2320 # define ATTRIBUTE_1_OVERRIDE_Y				(1 << 29)
2321 # define ATTRIBUTE_1_OVERRIDE_X				(1 << 28)
2322 # define ATTRIBUTE_1_CONST_SOURCE_SHIFT			25
2323 # define ATTRIBUTE_1_SWIZZLE_SHIFT			22
2324 # define ATTRIBUTE_1_SOURCE_SHIFT			16
2325 # define ATTRIBUTE_0_OVERRIDE_W				(1 << 15)
2326 # define ATTRIBUTE_0_OVERRIDE_Z				(1 << 14)
2327 # define ATTRIBUTE_0_OVERRIDE_Y				(1 << 13)
2328 # define ATTRIBUTE_0_OVERRIDE_X				(1 << 12)
2329 # define ATTRIBUTE_0_CONST_SOURCE_SHIFT			9
2330 #  define ATTRIBUTE_CONST_0000				0
2331 #  define ATTRIBUTE_CONST_0001_FLOAT			1
2332 #  define ATTRIBUTE_CONST_1111_FLOAT			2
2333 #  define ATTRIBUTE_CONST_PRIM_ID			3
2334 # define ATTRIBUTE_0_SWIZZLE_SHIFT			6
2335 # define ATTRIBUTE_0_SOURCE_SHIFT			0
2336 
2337 # define ATTRIBUTE_SWIZZLE_INPUTATTR                    0
2338 # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING             1
2339 # define ATTRIBUTE_SWIZZLE_INPUTATTR_W                  2
2340 # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W           3
2341 # define ATTRIBUTE_SWIZZLE_SHIFT                        6
2342 
2343 /* DW16: Point sprite texture coordinate enables */
2344 /* DW17: Constant interpolation enables */
2345 /* DW18: attr 0-7 wrap shortest enables */
2346 /* DW19: attr 8-16 wrap shortest enables */
2347 
2348 /* On GEN7, many fields of 3DSTATE_SF were split out into a new command:
2349  * 3DSTATE_SBE.  The remaining fields live in different DWords, but retain
2350  * the same bit-offset.  The only new field:
2351  */
2352 /* GEN7/DW1: */
2353 # define GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT	12
2354 /* GEN7/DW2: */
2355 # define HSW_SF_LINE_STIPPLE_ENABLE			(1 << 14)
2356 
2357 # define GEN8_SF_SMOOTH_POINT_ENABLE                    (1 << 13)
2358 
2359 #define _3DSTATE_SBE				0x781F /* GEN7+ */
2360 /* DW1 */
2361 # define GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH           (1 << 29)
2362 # define GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET           (1 << 28)
2363 # define GEN7_SBE_SWIZZLE_CONTROL_MODE			(1 << 28)
2364 # define GEN7_SBE_NUM_OUTPUTS_SHIFT			22
2365 # define GEN7_SBE_SWIZZLE_ENABLE			(1 << 21)
2366 # define GEN7_SBE_POINT_SPRITE_LOWERLEFT		(1 << 20)
2367 # define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT		11
2368 # define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT		4
2369 # define GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT		5
2370 /* DW2-9: Attribute setup (same as DW8-15 of gen6 _3DSTATE_SF) */
2371 /* DW10: Point sprite texture coordinate enables */
2372 /* DW11: Constant interpolation enables */
2373 /* DW12: attr 0-7 wrap shortest enables */
2374 /* DW13: attr 8-16 wrap shortest enables */
2375 
2376 /* DW4-5: Attribute active components (gen9) */
2377 #define GEN9_SBE_ACTIVE_COMPONENT_NONE			0
2378 #define GEN9_SBE_ACTIVE_COMPONENT_XY			1
2379 #define GEN9_SBE_ACTIVE_COMPONENT_XYZ			2
2380 #define GEN9_SBE_ACTIVE_COMPONENT_XYZW			3
2381 
2382 #define _3DSTATE_SBE_SWIZ                       0x7851 /* GEN8+ */
2383 
2384 #define _3DSTATE_RASTER                         0x7850 /* GEN8+ */
2385 /* DW1 */
2386 # define GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE    (1 << 26)
2387 # define GEN9_RASTER_CONSERVATIVE_RASTERIZATION_ENABLE  (1 << 24)
2388 # define GEN8_RASTER_FRONT_WINDING_CCW                  (1 << 21)
2389 # define GEN8_RASTER_CULL_BOTH                          (0 << 16)
2390 # define GEN8_RASTER_CULL_NONE                          (1 << 16)
2391 # define GEN8_RASTER_CULL_FRONT                         (2 << 16)
2392 # define GEN8_RASTER_CULL_BACK                          (3 << 16)
2393 # define GEN8_RASTER_SMOOTH_POINT_ENABLE                (1 << 13)
2394 # define GEN8_RASTER_API_MULTISAMPLE_ENABLE             (1 << 12)
2395 # define GEN8_RASTER_LINE_AA_ENABLE                     (1 << 2)
2396 # define GEN8_RASTER_SCISSOR_ENABLE                     (1 << 1)
2397 # define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE        (1 << 0)
2398 # define GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE   (1 << 0)
2399 
2400 /* Gen8 BLEND_STATE */
2401 /* DW0 */
2402 #define GEN8_BLEND_ALPHA_TO_COVERAGE_ENABLE             (1 << 31)
2403 #define GEN8_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE       (1 << 30)
2404 #define GEN8_BLEND_ALPHA_TO_ONE_ENABLE                  (1 << 29)
2405 #define GEN8_BLEND_ALPHA_TO_COVERAGE_DITHER_ENABLE      (1 << 28)
2406 #define GEN8_BLEND_ALPHA_TEST_ENABLE                    (1 << 27)
2407 #define GEN8_BLEND_ALPHA_TEST_FUNCTION_MASK             INTEL_MASK(26, 24)
2408 #define GEN8_BLEND_ALPHA_TEST_FUNCTION_SHIFT            24
2409 #define GEN8_BLEND_COLOR_DITHER_ENABLE                  (1 << 23)
2410 #define GEN8_BLEND_X_DITHER_OFFSET_MASK                 INTEL_MASK(22, 21)
2411 #define GEN8_BLEND_X_DITHER_OFFSET_SHIFT                21
2412 #define GEN8_BLEND_Y_DITHER_OFFSET_MASK                 INTEL_MASK(20, 19)
2413 #define GEN8_BLEND_Y_DITHER_OFFSET_SHIFT                19
2414 /* DW1 + 2n */
2415 #define GEN8_BLEND_COLOR_BUFFER_BLEND_ENABLE            (1 << 31)
2416 #define GEN8_BLEND_SRC_BLEND_FACTOR_MASK                INTEL_MASK(30, 26)
2417 #define GEN8_BLEND_SRC_BLEND_FACTOR_SHIFT               26
2418 #define GEN8_BLEND_DST_BLEND_FACTOR_MASK                INTEL_MASK(25, 21)
2419 #define GEN8_BLEND_DST_BLEND_FACTOR_SHIFT               21
2420 #define GEN8_BLEND_COLOR_BLEND_FUNCTION_MASK            INTEL_MASK(20, 18)
2421 #define GEN8_BLEND_COLOR_BLEND_FUNCTION_SHIFT           18
2422 #define GEN8_BLEND_SRC_ALPHA_BLEND_FACTOR_MASK          INTEL_MASK(17, 13)
2423 #define GEN8_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT         13
2424 #define GEN8_BLEND_DST_ALPHA_BLEND_FACTOR_MASK          INTEL_MASK(12, 8)
2425 #define GEN8_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT         8
2426 #define GEN8_BLEND_ALPHA_BLEND_FUNCTION_MASK            INTEL_MASK(7, 5)
2427 #define GEN8_BLEND_ALPHA_BLEND_FUNCTION_SHIFT           5
2428 #define GEN8_BLEND_WRITE_DISABLE_ALPHA                  (1 << 3)
2429 #define GEN8_BLEND_WRITE_DISABLE_RED                    (1 << 2)
2430 #define GEN8_BLEND_WRITE_DISABLE_GREEN                  (1 << 1)
2431 #define GEN8_BLEND_WRITE_DISABLE_BLUE                   (1 << 0)
2432 /* DW1 + 2n + 1 */
2433 #define GEN8_BLEND_LOGIC_OP_ENABLE                      (1 << 31)
2434 #define GEN8_BLEND_LOGIC_OP_FUNCTION_MASK               INTEL_MASK(30, 27)
2435 #define GEN8_BLEND_LOGIC_OP_FUNCTION_SHIFT              27
2436 #define GEN8_BLEND_PRE_BLEND_SRC_ONLY_CLAMP_ENABLE      (1 << 4)
2437 #define GEN8_BLEND_COLOR_CLAMP_RANGE_RTFORMAT           (2 << 2)
2438 #define GEN8_BLEND_PRE_BLEND_COLOR_CLAMP_ENABLE         (1 << 1)
2439 #define GEN8_BLEND_POST_BLEND_COLOR_CLAMP_ENABLE        (1 << 0)
2440 
2441 #define _3DSTATE_WM_HZ_OP                       0x7852 /* GEN8+ */
2442 /* DW1 */
2443 # define GEN8_WM_HZ_STENCIL_CLEAR                       (1 << 31)
2444 # define GEN8_WM_HZ_DEPTH_CLEAR                         (1 << 30)
2445 # define GEN8_WM_HZ_DEPTH_RESOLVE                       (1 << 28)
2446 # define GEN8_WM_HZ_HIZ_RESOLVE                         (1 << 27)
2447 # define GEN8_WM_HZ_PIXEL_OFFSET_ENABLE                 (1 << 26)
2448 # define GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR            (1 << 25)
2449 # define GEN8_WM_HZ_STENCIL_CLEAR_VALUE_MASK            INTEL_MASK(23, 16)
2450 # define GEN8_WM_HZ_STENCIL_CLEAR_VALUE_SHIFT           16
2451 # define GEN8_WM_HZ_NUM_SAMPLES_MASK                    INTEL_MASK(15, 13)
2452 # define GEN8_WM_HZ_NUM_SAMPLES_SHIFT                   13
2453 /* DW2 */
2454 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MIN_MASK          INTEL_MASK(31, 16)
2455 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MIN_SHIFT         16
2456 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MIN_MASK          INTEL_MASK(15, 0)
2457 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MIN_SHIFT         0
2458 /* DW3 */
2459 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX_MASK          INTEL_MASK(31, 16)
2460 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX_SHIFT         16
2461 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX_MASK          INTEL_MASK(15, 0)
2462 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX_SHIFT         0
2463 /* DW4 */
2464 # define GEN8_WM_HZ_SAMPLE_MASK_MASK                    INTEL_MASK(15, 0)
2465 # define GEN8_WM_HZ_SAMPLE_MASK_SHIFT                   0
2466 
2467 
2468 #define _3DSTATE_PS_BLEND                       0x784D /* GEN8+ */
2469 /* DW1 */
2470 # define GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE         (1 << 31)
2471 # define GEN8_PS_BLEND_HAS_WRITEABLE_RT                 (1 << 30)
2472 # define GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE        (1 << 29)
2473 # define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_MASK      INTEL_MASK(28, 24)
2474 # define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT     24
2475 # define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_MASK      INTEL_MASK(23, 19)
2476 # define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT     19
2477 # define GEN8_PS_BLEND_SRC_BLEND_FACTOR_MASK            INTEL_MASK(18, 14)
2478 # define GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT           14
2479 # define GEN8_PS_BLEND_DST_BLEND_FACTOR_MASK            INTEL_MASK(13, 9)
2480 # define GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT           9
2481 # define GEN8_PS_BLEND_ALPHA_TEST_ENABLE                (1 << 8)
2482 # define GEN8_PS_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE   (1 << 7)
2483 
2484 #define _3DSTATE_WM_DEPTH_STENCIL               0x784E /* GEN8+ */
2485 /* DW1 */
2486 # define GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT               29
2487 # define GEN8_WM_DS_Z_FAIL_OP_SHIFT                     26
2488 # define GEN8_WM_DS_Z_PASS_OP_SHIFT                     23
2489 # define GEN8_WM_DS_BF_STENCIL_FUNC_SHIFT               20
2490 # define GEN8_WM_DS_BF_STENCIL_FAIL_OP_SHIFT            17
2491 # define GEN8_WM_DS_BF_Z_FAIL_OP_SHIFT                  14
2492 # define GEN8_WM_DS_BF_Z_PASS_OP_SHIFT                  11
2493 # define GEN8_WM_DS_STENCIL_FUNC_SHIFT                  8
2494 # define GEN8_WM_DS_DEPTH_FUNC_SHIFT                    5
2495 # define GEN8_WM_DS_DOUBLE_SIDED_STENCIL_ENABLE         (1 << 4)
2496 # define GEN8_WM_DS_STENCIL_TEST_ENABLE                 (1 << 3)
2497 # define GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE         (1 << 2)
2498 # define GEN8_WM_DS_DEPTH_TEST_ENABLE                   (1 << 1)
2499 # define GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE           (1 << 0)
2500 /* DW2 */
2501 # define GEN8_WM_DS_STENCIL_TEST_MASK_MASK              INTEL_MASK(31, 24)
2502 # define GEN8_WM_DS_STENCIL_TEST_MASK_SHIFT             24
2503 # define GEN8_WM_DS_STENCIL_WRITE_MASK_MASK             INTEL_MASK(23, 16)
2504 # define GEN8_WM_DS_STENCIL_WRITE_MASK_SHIFT            16
2505 # define GEN8_WM_DS_BF_STENCIL_TEST_MASK_MASK           INTEL_MASK(15, 8)
2506 # define GEN8_WM_DS_BF_STENCIL_TEST_MASK_SHIFT          8
2507 # define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_MASK          INTEL_MASK(7, 0)
2508 # define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_SHIFT         0
2509 /* DW3 */
2510 # define GEN9_WM_DS_STENCIL_REF_MASK                    INTEL_MASK(15, 8)
2511 # define GEN9_WM_DS_STENCIL_REF_SHIFT                   8
2512 # define GEN9_WM_DS_BF_STENCIL_REF_MASK                 INTEL_MASK(7, 0)
2513 # define GEN9_WM_DS_BF_STENCIL_REF_SHIFT                0
2514 
2515 enum brw_pixel_shader_computed_depth_mode {
2516    BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
2517    BRW_PSCDEPTH_ON    = 1, /* PS computes depth; no guarantee about value */
2518    BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
2519    BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
2520 };
2521 
2522 enum brw_pixel_shader_coverage_mask_mode {
2523    BRW_PSICMS_OFF     = 0, /* PS does not use input coverage masks. */
2524    BRW_PSICMS_NORMAL  = 1, /* Input Coverage masks based on outer conservatism
2525                             * and factors in SAMPLE_MASK.  If Pixel is
2526                             * conservatively covered, all samples are enabled.
2527                             */
2528 
2529    BRW_PSICMS_INNER   = 2, /* Input Coverage masks based on inner conservatism
2530                             * and factors in SAMPLE_MASK.  If Pixel is
2531                             * conservatively *FULLY* covered, all samples are
2532                             * enabled.
2533                             */
2534    BRW_PCICMS_DEPTH   = 3,
2535 };
2536 
2537 #define _3DSTATE_PS_EXTRA                       0x784F /* GEN8+ */
2538 /* DW1 */
2539 # define GEN8_PSX_PIXEL_SHADER_VALID                    (1 << 31)
2540 # define GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE              (1 << 30)
2541 # define GEN8_PSX_OMASK_TO_RENDER_TARGET                (1 << 29)
2542 # define GEN8_PSX_KILL_ENABLE                           (1 << 28)
2543 # define GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT             26
2544 # define GEN8_PSX_FORCE_COMPUTED_DEPTH                  (1 << 25)
2545 # define GEN8_PSX_USES_SOURCE_DEPTH                     (1 << 24)
2546 # define GEN8_PSX_USES_SOURCE_W                         (1 << 23)
2547 # define GEN8_PSX_ATTRIBUTE_ENABLE                      (1 << 8)
2548 # define GEN8_PSX_SHADER_DISABLES_ALPHA_TO_COVERAGE     (1 << 7)
2549 # define GEN8_PSX_SHADER_IS_PER_SAMPLE                  (1 << 6)
2550 # define GEN9_PSX_SHADER_COMPUTES_STENCIL               (1 << 5)
2551 # define GEN9_PSX_SHADER_PULLS_BARY                     (1 << 3)
2552 # define GEN8_PSX_SHADER_HAS_UAV                        (1 << 2)
2553 # define GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK       (1 << 1)
2554 # define GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT     0
2555 
2556 enum brw_barycentric_mode {
2557    BRW_BARYCENTRIC_PERSPECTIVE_PIXEL       = 0,
2558    BRW_BARYCENTRIC_PERSPECTIVE_CENTROID    = 1,
2559    BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE      = 2,
2560    BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL    = 3,
2561    BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
2562    BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
2563    BRW_BARYCENTRIC_MODE_COUNT              = 6
2564 };
2565 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
2566    ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
2567     (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
2568     (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
2569 
2570 #define _3DSTATE_WM				0x7814 /* GEN6+ */
2571 /* DW1: kernel pointer */
2572 /* DW2 */
2573 # define GEN6_WM_SPF_MODE				(1 << 31)
2574 # define GEN6_WM_VECTOR_MASK_ENABLE			(1 << 30)
2575 # define GEN6_WM_SAMPLER_COUNT_SHIFT			27
2576 # define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
2577 # define GEN6_WM_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
2578 # define GEN6_WM_FLOATING_POINT_MODE_ALT		(1 << 16)
2579 /* DW3: scratch space */
2580 /* DW4 */
2581 # define GEN6_WM_STATISTICS_ENABLE			(1 << 31)
2582 # define GEN6_WM_DEPTH_CLEAR				(1 << 30)
2583 # define GEN6_WM_DEPTH_RESOLVE				(1 << 28)
2584 # define GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE		(1 << 27)
2585 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_0		16
2586 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_1		8
2587 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_2		0
2588 /* DW5 */
2589 # define GEN6_WM_MAX_THREADS_SHIFT			25
2590 # define GEN6_WM_KILL_ENABLE				(1 << 22)
2591 # define GEN6_WM_COMPUTED_DEPTH				(1 << 21)
2592 # define GEN6_WM_USES_SOURCE_DEPTH			(1 << 20)
2593 # define GEN6_WM_DISPATCH_ENABLE			(1 << 19)
2594 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5		(0 << 16)
2595 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0		(1 << 16)
2596 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_2_0		(2 << 16)
2597 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_4_0		(3 << 16)
2598 # define GEN6_WM_LINE_AA_WIDTH_0_5			(0 << 14)
2599 # define GEN6_WM_LINE_AA_WIDTH_1_0			(1 << 14)
2600 # define GEN6_WM_LINE_AA_WIDTH_2_0			(2 << 14)
2601 # define GEN6_WM_LINE_AA_WIDTH_4_0			(3 << 14)
2602 # define GEN6_WM_POLYGON_STIPPLE_ENABLE			(1 << 13)
2603 # define GEN6_WM_LINE_STIPPLE_ENABLE			(1 << 11)
2604 # define GEN6_WM_OMASK_TO_RENDER_TARGET			(1 << 9)
2605 # define GEN6_WM_USES_SOURCE_W				(1 << 8)
2606 # define GEN6_WM_DUAL_SOURCE_BLEND_ENABLE		(1 << 7)
2607 # define GEN6_WM_32_DISPATCH_ENABLE			(1 << 2)
2608 # define GEN6_WM_16_DISPATCH_ENABLE			(1 << 1)
2609 # define GEN6_WM_8_DISPATCH_ENABLE			(1 << 0)
2610 /* DW6 */
2611 # define GEN6_WM_NUM_SF_OUTPUTS_SHIFT			20
2612 # define GEN6_WM_POSOFFSET_NONE				(0 << 18)
2613 # define GEN6_WM_POSOFFSET_CENTROID			(2 << 18)
2614 # define GEN6_WM_POSOFFSET_SAMPLE			(3 << 18)
2615 # define GEN6_WM_POSITION_ZW_PIXEL			(0 << 16)
2616 # define GEN6_WM_POSITION_ZW_CENTROID			(2 << 16)
2617 # define GEN6_WM_POSITION_ZW_SAMPLE			(3 << 16)
2618 # define GEN6_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC	(1 << 15)
2619 # define GEN6_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC	(1 << 14)
2620 # define GEN6_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC	(1 << 13)
2621 # define GEN6_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC		(1 << 12)
2622 # define GEN6_WM_PERSPECTIVE_CENTROID_BARYCENTRIC	(1 << 11)
2623 # define GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC		(1 << 10)
2624 # define GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT   10
2625 # define GEN6_WM_POINT_RASTRULE_UPPER_RIGHT		(1 << 9)
2626 # define GEN6_WM_MSRAST_OFF_PIXEL			(0 << 1)
2627 # define GEN6_WM_MSRAST_OFF_PATTERN			(1 << 1)
2628 # define GEN6_WM_MSRAST_ON_PIXEL			(2 << 1)
2629 # define GEN6_WM_MSRAST_ON_PATTERN			(3 << 1)
2630 # define GEN6_WM_MSDISPMODE_PERSAMPLE			(0 << 0)
2631 # define GEN6_WM_MSDISPMODE_PERPIXEL			(1 << 0)
2632 /* DW7: kernel 1 pointer */
2633 /* DW8: kernel 2 pointer */
2634 
2635 #define _3DSTATE_CONSTANT_VS		      0x7815 /* GEN6+ */
2636 #define _3DSTATE_CONSTANT_GS		      0x7816 /* GEN6+ */
2637 #define _3DSTATE_CONSTANT_PS		      0x7817 /* GEN6+ */
2638 # define GEN6_CONSTANT_BUFFER_3_ENABLE			(1 << 15)
2639 # define GEN6_CONSTANT_BUFFER_2_ENABLE			(1 << 14)
2640 # define GEN6_CONSTANT_BUFFER_1_ENABLE			(1 << 13)
2641 # define GEN6_CONSTANT_BUFFER_0_ENABLE			(1 << 12)
2642 
2643 #define _3DSTATE_CONSTANT_HS                  0x7819 /* GEN7+ */
2644 #define _3DSTATE_CONSTANT_DS                  0x781A /* GEN7+ */
2645 
2646 /* Resource streamer gather constants */
2647 #define _3DSTATE_GATHER_POOL_ALLOC            0x791A /* GEN7.5+ */
2648 #define HSW_GATHER_POOL_ALLOC_MUST_BE_ONE     (3 << 4) /* GEN7.5 only */
2649 
2650 #define _3DSTATE_GATHER_CONSTANT_VS           0x7834 /* GEN7.5+ */
2651 #define _3DSTATE_GATHER_CONSTANT_GS           0x7835
2652 #define _3DSTATE_GATHER_CONSTANT_HS           0x7836
2653 #define _3DSTATE_GATHER_CONSTANT_DS           0x7837
2654 #define _3DSTATE_GATHER_CONSTANT_PS           0x7838
2655 #define HSW_GATHER_CONSTANT_ENABLE            (1 << 11)
2656 #define HSW_GATHER_CONSTANT_BUFFER_VALID_SHIFT         16
2657 #define HSW_GATHER_CONSTANT_BUFFER_VALID_MASK          INTEL_MASK(31, 16)
2658 #define HSW_GATHER_CONSTANT_BINDING_TABLE_BLOCK_SHIFT  12
2659 #define HSW_GATHER_CONSTANT_BINDING_TABLE_BLOCK_MASK   INTEL_MASK(15, 12)
2660 #define HSW_GATHER_CONSTANT_CONST_BUFFER_OFFSET_SHIFT  8
2661 #define HSW_GATHER_CONSTANT_CONST_BUFFER_OFFSET_MASK   INTEL_MASK(15, 8)
2662 #define HSW_GATHER_CONSTANT_CHANNEL_MASK_SHIFT         4
2663 #define HSW_GATHER_CONSTANT_CHANNEL_MASK_MASK          INTEL_MASK(7, 4)
2664 
2665 #define _3DSTATE_STREAMOUT                    0x781e /* GEN7+ */
2666 /* DW1 */
2667 # define SO_FUNCTION_ENABLE				(1 << 31)
2668 # define SO_RENDERING_DISABLE				(1 << 30)
2669 /* This selects which incoming rendering stream goes down the pipeline.  The
2670  * rendering stream is 0 if not defined by special cases in the GS state.
2671  */
2672 # define SO_RENDER_STREAM_SELECT_SHIFT			27
2673 # define SO_RENDER_STREAM_SELECT_MASK			INTEL_MASK(28, 27)
2674 /* Controls reordering of TRISTRIP_* elements in stream output (not rendering).
2675  */
2676 # define SO_REORDER_TRAILING				(1 << 26)
2677 /* Controls SO_NUM_PRIMS_WRITTEN_* and SO_PRIM_STORAGE_* */
2678 # define SO_STATISTICS_ENABLE				(1 << 25)
2679 # define SO_BUFFER_ENABLE(n)				(1 << (8 + (n)))
2680 /* DW2 */
2681 # define SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT		29
2682 # define SO_STREAM_3_VERTEX_READ_OFFSET_MASK		INTEL_MASK(29, 29)
2683 # define SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT		24
2684 # define SO_STREAM_3_VERTEX_READ_LENGTH_MASK		INTEL_MASK(28, 24)
2685 # define SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT		21
2686 # define SO_STREAM_2_VERTEX_READ_OFFSET_MASK		INTEL_MASK(21, 21)
2687 # define SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT		16
2688 # define SO_STREAM_2_VERTEX_READ_LENGTH_MASK		INTEL_MASK(20, 16)
2689 # define SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT		13
2690 # define SO_STREAM_1_VERTEX_READ_OFFSET_MASK		INTEL_MASK(13, 13)
2691 # define SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT		8
2692 # define SO_STREAM_1_VERTEX_READ_LENGTH_MASK		INTEL_MASK(12, 8)
2693 # define SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT		5
2694 # define SO_STREAM_0_VERTEX_READ_OFFSET_MASK		INTEL_MASK(5, 5)
2695 # define SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT		0
2696 # define SO_STREAM_0_VERTEX_READ_LENGTH_MASK		INTEL_MASK(4, 0)
2697 
2698 /* 3DSTATE_WM for Gen7 */
2699 /* DW1 */
2700 # define GEN7_WM_STATISTICS_ENABLE			(1 << 31)
2701 # define GEN7_WM_DEPTH_CLEAR				(1 << 30)
2702 # define GEN7_WM_DISPATCH_ENABLE			(1 << 29)
2703 # define GEN7_WM_DEPTH_RESOLVE				(1 << 28)
2704 # define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE		(1 << 27)
2705 # define GEN7_WM_KILL_ENABLE				(1 << 25)
2706 # define GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT              23
2707 # define GEN7_WM_USES_SOURCE_DEPTH			(1 << 20)
2708 # define GEN7_WM_EARLY_DS_CONTROL_NORMAL                (0 << 21)
2709 # define GEN7_WM_EARLY_DS_CONTROL_PSEXEC                (1 << 21)
2710 # define GEN7_WM_EARLY_DS_CONTROL_PREPS                 (2 << 21)
2711 # define GEN7_WM_USES_SOURCE_W			        (1 << 19)
2712 # define GEN7_WM_POSITION_ZW_PIXEL			(0 << 17)
2713 # define GEN7_WM_POSITION_ZW_CENTROID			(2 << 17)
2714 # define GEN7_WM_POSITION_ZW_SAMPLE			(3 << 17)
2715 # define GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT   11
2716 # define GEN7_WM_USES_INPUT_COVERAGE_MASK	        (1 << 10)
2717 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5		(0 << 8)
2718 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0		(1 << 8)
2719 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0		(2 << 8)
2720 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0		(3 << 8)
2721 # define GEN7_WM_LINE_AA_WIDTH_0_5			(0 << 6)
2722 # define GEN7_WM_LINE_AA_WIDTH_1_0			(1 << 6)
2723 # define GEN7_WM_LINE_AA_WIDTH_2_0			(2 << 6)
2724 # define GEN7_WM_LINE_AA_WIDTH_4_0			(3 << 6)
2725 # define GEN7_WM_POLYGON_STIPPLE_ENABLE			(1 << 4)
2726 # define GEN7_WM_LINE_STIPPLE_ENABLE			(1 << 3)
2727 # define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT		(1 << 2)
2728 # define GEN7_WM_MSRAST_OFF_PIXEL			(0 << 0)
2729 # define GEN7_WM_MSRAST_OFF_PATTERN			(1 << 0)
2730 # define GEN7_WM_MSRAST_ON_PIXEL			(2 << 0)
2731 # define GEN7_WM_MSRAST_ON_PATTERN			(3 << 0)
2732 /* DW2 */
2733 # define GEN7_WM_MSDISPMODE_PERSAMPLE			(0 << 31)
2734 # define GEN7_WM_MSDISPMODE_PERPIXEL			(1 << 31)
2735 # define HSW_WM_UAV_ONLY                                (1 << 30)
2736 
2737 #define _3DSTATE_PS				0x7820 /* GEN7+ */
2738 /* DW1: kernel pointer */
2739 /* DW2 */
2740 # define GEN7_PS_SPF_MODE				(1 << 31)
2741 # define GEN7_PS_VECTOR_MASK_ENABLE			(1 << 30)
2742 # define GEN7_PS_SAMPLER_COUNT_SHIFT			27
2743 # define GEN7_PS_SAMPLER_COUNT_MASK                     INTEL_MASK(29, 27)
2744 # define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
2745 # define GEN7_PS_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
2746 # define GEN7_PS_FLOATING_POINT_MODE_ALT		(1 << 16)
2747 /* DW3: scratch space */
2748 /* DW4 */
2749 # define IVB_PS_MAX_THREADS_SHIFT			24
2750 # define HSW_PS_MAX_THREADS_SHIFT			23
2751 # define HSW_PS_SAMPLE_MASK_SHIFT		        12
2752 # define HSW_PS_SAMPLE_MASK_MASK			INTEL_MASK(19, 12)
2753 # define GEN7_PS_PUSH_CONSTANT_ENABLE		        (1 << 11)
2754 # define GEN7_PS_ATTRIBUTE_ENABLE		        (1 << 10)
2755 # define GEN7_PS_OMASK_TO_RENDER_TARGET			(1 << 9)
2756 # define GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE	(1 << 8)
2757 # define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE		(1 << 7)
2758 # define GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE		(1 << 6)
2759 # define GEN9_PS_RENDER_TARGET_RESOLVE_FULL             (3 << 6)
2760 # define HSW_PS_UAV_ACCESS_ENABLE			(1 << 5)
2761 # define GEN7_PS_POSOFFSET_NONE				(0 << 3)
2762 # define GEN7_PS_POSOFFSET_CENTROID			(2 << 3)
2763 # define GEN7_PS_POSOFFSET_SAMPLE			(3 << 3)
2764 # define GEN7_PS_32_DISPATCH_ENABLE			(1 << 2)
2765 # define GEN7_PS_16_DISPATCH_ENABLE			(1 << 1)
2766 # define GEN7_PS_8_DISPATCH_ENABLE			(1 << 0)
2767 /* DW5 */
2768 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_0		16
2769 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_1		8
2770 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_2		0
2771 /* DW6: kernel 1 pointer */
2772 /* DW7: kernel 2 pointer */
2773 
2774 #define _3DSTATE_SAMPLE_MASK			0x7818 /* GEN6+ */
2775 
2776 #define _3DSTATE_DRAWING_RECTANGLE		0x7900
2777 #define _3DSTATE_BLEND_CONSTANT_COLOR		0x7901
2778 #define _3DSTATE_CHROMA_KEY			0x7904
2779 #define _3DSTATE_DEPTH_BUFFER			0x7905 /* GEN4-6 */
2780 #define _3DSTATE_POLY_STIPPLE_OFFSET		0x7906
2781 #define _3DSTATE_POLY_STIPPLE_PATTERN		0x7907
2782 #define _3DSTATE_LINE_STIPPLE_PATTERN		0x7908
2783 #define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP	0x7909
2784 #define _3DSTATE_AA_LINE_PARAMETERS		0x790a /* G45+ */
2785 
2786 #define _3DSTATE_GS_SVB_INDEX			0x790b /* CTG+ */
2787 /* DW1 */
2788 # define SVB_INDEX_SHIFT				29
2789 # define SVB_LOAD_INTERNAL_VERTEX_COUNT			(1 << 0) /* SNB+ */
2790 /* DW2: SVB index */
2791 /* DW3: SVB maximum index */
2792 
2793 #define _3DSTATE_MULTISAMPLE			0x790d /* GEN6+ */
2794 #define GEN8_3DSTATE_MULTISAMPLE		0x780d /* GEN8+ */
2795 /* DW1 */
2796 # define MS_PIXEL_LOCATION_CENTER			(0 << 4)
2797 # define MS_PIXEL_LOCATION_UPPER_LEFT			(1 << 4)
2798 # define MS_NUMSAMPLES_1				(0 << 1)
2799 # define MS_NUMSAMPLES_2				(1 << 1)
2800 # define MS_NUMSAMPLES_4				(2 << 1)
2801 # define MS_NUMSAMPLES_8				(3 << 1)
2802 # define MS_NUMSAMPLES_16				(4 << 1)
2803 
2804 #define _3DSTATE_SAMPLE_PATTERN                 0x791c
2805 
2806 #define _3DSTATE_STENCIL_BUFFER			0x790e /* ILK, SNB */
2807 #define _3DSTATE_HIER_DEPTH_BUFFER		0x790f /* ILK, SNB */
2808 
2809 #define GEN7_3DSTATE_CLEAR_PARAMS		0x7804
2810 #define GEN7_3DSTATE_DEPTH_BUFFER		0x7805
2811 #define GEN7_3DSTATE_STENCIL_BUFFER		0x7806
2812 # define HSW_STENCIL_ENABLED                            (1 << 31)
2813 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER		0x7807
2814 
2815 #define _3DSTATE_CLEAR_PARAMS			0x7910 /* ILK, SNB */
2816 # define GEN5_DEPTH_CLEAR_VALID				(1 << 15)
2817 /* DW1: depth clear value */
2818 /* DW2 */
2819 # define GEN7_DEPTH_CLEAR_VALID				(1 << 0)
2820 
2821 #define _3DSTATE_SO_DECL_LIST			0x7917 /* GEN7+ */
2822 /* DW1 */
2823 # define SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT		12
2824 # define SO_STREAM_TO_BUFFER_SELECTS_3_MASK		INTEL_MASK(15, 12)
2825 # define SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT		8
2826 # define SO_STREAM_TO_BUFFER_SELECTS_2_MASK		INTEL_MASK(11, 8)
2827 # define SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT		4
2828 # define SO_STREAM_TO_BUFFER_SELECTS_1_MASK		INTEL_MASK(7, 4)
2829 # define SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT		0
2830 # define SO_STREAM_TO_BUFFER_SELECTS_0_MASK		INTEL_MASK(3, 0)
2831 /* DW2 */
2832 # define SO_NUM_ENTRIES_3_SHIFT				24
2833 # define SO_NUM_ENTRIES_3_MASK				INTEL_MASK(31, 24)
2834 # define SO_NUM_ENTRIES_2_SHIFT				16
2835 # define SO_NUM_ENTRIES_2_MASK				INTEL_MASK(23, 16)
2836 # define SO_NUM_ENTRIES_1_SHIFT				8
2837 # define SO_NUM_ENTRIES_1_MASK				INTEL_MASK(15, 8)
2838 # define SO_NUM_ENTRIES_0_SHIFT				0
2839 # define SO_NUM_ENTRIES_0_MASK				INTEL_MASK(7, 0)
2840 
2841 /* SO_DECL DW0 */
2842 # define SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT		12
2843 # define SO_DECL_OUTPUT_BUFFER_SLOT_MASK		INTEL_MASK(13, 12)
2844 # define SO_DECL_HOLE_FLAG				(1 << 11)
2845 # define SO_DECL_REGISTER_INDEX_SHIFT			4
2846 # define SO_DECL_REGISTER_INDEX_MASK			INTEL_MASK(9, 4)
2847 # define SO_DECL_COMPONENT_MASK_SHIFT			0
2848 # define SO_DECL_COMPONENT_MASK_MASK			INTEL_MASK(3, 0)
2849 
2850 #define _3DSTATE_SO_BUFFER                    0x7918 /* GEN7+ */
2851 /* DW1 */
2852 # define GEN8_SO_BUFFER_ENABLE                          (1 << 31)
2853 # define SO_BUFFER_INDEX_SHIFT				29
2854 # define SO_BUFFER_INDEX_MASK				INTEL_MASK(30, 29)
2855 # define GEN8_SO_BUFFER_OFFSET_WRITE_ENABLE             (1 << 21)
2856 # define GEN8_SO_BUFFER_OFFSET_ADDRESS_ENABLE           (1 << 20)
2857 # define SO_BUFFER_PITCH_SHIFT				0
2858 # define SO_BUFFER_PITCH_MASK				INTEL_MASK(11, 0)
2859 /* DW2: start address */
2860 /* DW3: end address. */
2861 
2862 #define CMD_MI_FLUSH                  0x0200
2863 
2864 # define BLT_X_SHIFT					0
2865 # define BLT_X_MASK					INTEL_MASK(15, 0)
2866 # define BLT_Y_SHIFT					16
2867 # define BLT_Y_MASK					INTEL_MASK(31, 16)
2868 
2869 #define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))
2870 /* DW0 */
2871 # define GEN5_MI_COUNTER_SET_0      (0 << 6)
2872 # define GEN5_MI_COUNTER_SET_1      (1 << 6)
2873 /* DW1 */
2874 # define MI_COUNTER_ADDRESS_GTT     (1 << 0)
2875 /* DW2: a user-defined report ID (written to the buffer but can be anything) */
2876 
2877 #define GEN6_MI_REPORT_PERF_COUNT ((0x28 << 23) | (3 - 2))
2878 
2879 /* Bitfields for the URB_WRITE message, DW2 of message header: */
2880 #define URB_WRITE_PRIM_END		0x1
2881 #define URB_WRITE_PRIM_START		0x2
2882 #define URB_WRITE_PRIM_TYPE_SHIFT	2
2883 
2884 
2885 /* Maximum number of entries that can be addressed using a binding table
2886  * pointer of type SURFTYPE_BUFFER
2887  */
2888 #define BRW_MAX_NUM_BUFFER_ENTRIES	(1 << 27)
2889 
2890 /* Memory Object Control State:
2891  * Specifying zero for L3 means "uncached in L3", at least on Haswell
2892  * and Baytrail, since there are no PTE flags for setting L3 cacheability.
2893  * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
2894  * may still respect that.
2895  */
2896 #define GEN7_MOCS_L3                    1
2897 
2898 /* Ivybridge only: cache in LLC.
2899  * Specifying zero here means to use the PTE values set by the kernel;
2900  * non-zero overrides the PTE values.
2901  */
2902 #define IVB_MOCS_LLC                    (1 << 1)
2903 
2904 /* Baytrail only: snoop in CPU cache */
2905 #define BYT_MOCS_SNOOP                  (1 << 1)
2906 
2907 /* Haswell only: LLC/eLLC controls (write-back or uncached).
2908  * Specifying zero here means to use the PTE values set by the kernel,
2909  * which is useful since it offers additional control (write-through
2910  * cacheing and age).  Non-zero overrides the PTE values.
2911  */
2912 #define HSW_MOCS_UC_LLC_UC_ELLC         (1 << 1)
2913 #define HSW_MOCS_WB_LLC_WB_ELLC         (2 << 1)
2914 #define HSW_MOCS_UC_LLC_WB_ELLC         (3 << 1)
2915 
2916 /* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
2917  * and let you force write-back (WB) or write-through (WT) caching, or leave
2918  * it up to the page table entry (PTE) specified by the kernel.
2919  */
2920 #define BDW_MOCS_WB  0x78
2921 #define BDW_MOCS_WT  0x58
2922 #define BDW_MOCS_PTE 0x18
2923 
2924 /* Skylake: MOCS is now an index into an array of 62 different caching
2925  * configurations programmed by the kernel.
2926  */
2927 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
2928 #define SKL_MOCS_WB  (2 << 1)
2929 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
2930 #define SKL_MOCS_PTE (1 << 1)
2931 
2932 #define MEDIA_VFE_STATE                         0x7000
2933 /* GEN7 DW2, GEN8+ DW3 */
2934 # define MEDIA_VFE_STATE_MAX_THREADS_SHIFT      16
2935 # define MEDIA_VFE_STATE_MAX_THREADS_MASK       INTEL_MASK(31, 16)
2936 # define MEDIA_VFE_STATE_URB_ENTRIES_SHIFT      8
2937 # define MEDIA_VFE_STATE_URB_ENTRIES_MASK       INTEL_MASK(15, 8)
2938 # define MEDIA_VFE_STATE_RESET_GTW_TIMER_SHIFT  7
2939 # define MEDIA_VFE_STATE_RESET_GTW_TIMER_MASK   INTEL_MASK(7, 7)
2940 # define MEDIA_VFE_STATE_BYPASS_GTW_SHIFT       6
2941 # define MEDIA_VFE_STATE_BYPASS_GTW_MASK        INTEL_MASK(6, 6)
2942 # define GEN7_MEDIA_VFE_STATE_GPGPU_MODE_SHIFT  2
2943 # define GEN7_MEDIA_VFE_STATE_GPGPU_MODE_MASK   INTEL_MASK(2, 2)
2944 /* GEN7 DW4, GEN8+ DW5 */
2945 # define MEDIA_VFE_STATE_URB_ALLOC_SHIFT        16
2946 # define MEDIA_VFE_STATE_URB_ALLOC_MASK         INTEL_MASK(31, 16)
2947 # define MEDIA_VFE_STATE_CURBE_ALLOC_SHIFT      0
2948 # define MEDIA_VFE_STATE_CURBE_ALLOC_MASK       INTEL_MASK(15, 0)
2949 
2950 #define MEDIA_CURBE_LOAD                        0x7001
2951 #define MEDIA_INTERFACE_DESCRIPTOR_LOAD         0x7002
2952 /* GEN7 DW4, GEN8+ DW5 */
2953 # define MEDIA_CURBE_READ_LENGTH_SHIFT          16
2954 # define MEDIA_CURBE_READ_LENGTH_MASK           INTEL_MASK(31, 16)
2955 # define MEDIA_CURBE_READ_OFFSET_SHIFT          0
2956 # define MEDIA_CURBE_READ_OFFSET_MASK           INTEL_MASK(15, 0)
2957 /* GEN7 DW5, GEN8+ DW6 */
2958 # define MEDIA_BARRIER_ENABLE_SHIFT             21
2959 # define MEDIA_BARRIER_ENABLE_MASK              INTEL_MASK(21, 21)
2960 # define MEDIA_SHARED_LOCAL_MEMORY_SIZE_SHIFT   16
2961 # define MEDIA_SHARED_LOCAL_MEMORY_SIZE_MASK    INTEL_MASK(20, 16)
2962 # define MEDIA_GPGPU_THREAD_COUNT_SHIFT         0
2963 # define MEDIA_GPGPU_THREAD_COUNT_MASK          INTEL_MASK(7, 0)
2964 # define GEN8_MEDIA_GPGPU_THREAD_COUNT_SHIFT    0
2965 # define GEN8_MEDIA_GPGPU_THREAD_COUNT_MASK     INTEL_MASK(9, 0)
2966 /* GEN7 DW6, GEN8+ DW7 */
2967 # define CROSS_THREAD_READ_LENGTH_SHIFT         0
2968 # define CROSS_THREAD_READ_LENGTH_MASK          INTEL_MASK(7, 0)
2969 #define MEDIA_STATE_FLUSH                       0x7004
2970 #define GPGPU_WALKER                            0x7105
2971 /* GEN7 DW0 */
2972 # define GEN7_GPGPU_INDIRECT_PARAMETER_ENABLE   (1 << 10)
2973 # define GEN7_GPGPU_PREDICATE_ENABLE            (1 << 8)
2974 /* GEN8+ DW2 */
2975 # define GPGPU_WALKER_INDIRECT_LENGTH_SHIFT     0
2976 # define GPGPU_WALKER_INDIRECT_LENGTH_MASK      INTEL_MASK(15, 0)
2977 /* GEN7 DW2, GEN8+ DW4 */
2978 # define GPGPU_WALKER_SIMD_SIZE_SHIFT           30
2979 # define GPGPU_WALKER_SIMD_SIZE_MASK            INTEL_MASK(31, 30)
2980 # define GPGPU_WALKER_THREAD_DEPTH_MAX_SHIFT    16
2981 # define GPGPU_WALKER_THREAD_DEPTH_MAX_MASK     INTEL_MASK(21, 16)
2982 # define GPGPU_WALKER_THREAD_HEIGHT_MAX_SHIFT   8
2983 # define GPGPU_WALKER_THREAD_HEIGHT_MAX_MASK    INTEL_MASK(31, 8)
2984 # define GPGPU_WALKER_THREAD_WIDTH_MAX_SHIFT    0
2985 # define GPGPU_WALKER_THREAD_WIDTH_MAX_MASK     INTEL_MASK(5, 0)
2986 
2987 #define CMD_MI				(0x0 << 29)
2988 #define CMD_2D				(0x2 << 29)
2989 #define CMD_3D				(0x3 << 29)
2990 
2991 #define MI_NOOP				(CMD_MI | 0)
2992 
2993 #define MI_BATCH_BUFFER_END		(CMD_MI | 0xA << 23)
2994 
2995 #define MI_FLUSH			(CMD_MI | (4 << 23))
2996 #define FLUSH_MAP_CACHE				(1 << 0)
2997 #define INHIBIT_FLUSH_RENDER_CACHE		(1 << 2)
2998 
2999 #define MI_STORE_DATA_IMM		(CMD_MI | (0x20 << 23))
3000 #define MI_LOAD_REGISTER_IMM		(CMD_MI | (0x22 << 23))
3001 #define MI_LOAD_REGISTER_REG		(CMD_MI | (0x2A << 23))
3002 
3003 #define MI_FLUSH_DW			(CMD_MI | (0x26 << 23) | 2)
3004 
3005 #define MI_STORE_REGISTER_MEM		(CMD_MI | (0x24 << 23))
3006 # define MI_STORE_REGISTER_MEM_USE_GGTT		(1 << 22)
3007 # define MI_STORE_REGISTER_MEM_PREDICATE	(1 << 21)
3008 
3009 /* Load a value from memory into a register.  Only available on Gen7+. */
3010 #define GEN7_MI_LOAD_REGISTER_MEM	(CMD_MI | (0x29 << 23))
3011 # define MI_LOAD_REGISTER_MEM_USE_GGTT		(1 << 22)
3012 /* Haswell RS control */
3013 #define MI_RS_CONTROL                   (CMD_MI | (0x6 << 23))
3014 #define MI_RS_STORE_DATA_IMM            (CMD_MI | (0x2b << 23))
3015 
3016 /* Manipulate the predicate bit based on some register values. Only on Gen7+ */
3017 #define GEN7_MI_PREDICATE		(CMD_MI | (0xC << 23))
3018 # define MI_PREDICATE_LOADOP_KEEP		(0 << 6)
3019 # define MI_PREDICATE_LOADOP_LOAD		(2 << 6)
3020 # define MI_PREDICATE_LOADOP_LOADINV		(3 << 6)
3021 # define MI_PREDICATE_COMBINEOP_SET		(0 << 3)
3022 # define MI_PREDICATE_COMBINEOP_AND		(1 << 3)
3023 # define MI_PREDICATE_COMBINEOP_OR		(2 << 3)
3024 # define MI_PREDICATE_COMBINEOP_XOR		(3 << 3)
3025 # define MI_PREDICATE_COMPAREOP_TRUE		(0 << 0)
3026 # define MI_PREDICATE_COMPAREOP_FALSE		(1 << 0)
3027 # define MI_PREDICATE_COMPAREOP_SRCS_EQUAL	(2 << 0)
3028 # define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL	(3 << 0)
3029 
3030 #define HSW_MI_MATH			(CMD_MI | (0x1a << 23))
3031 
3032 #define MI_MATH_ALU2(opcode, operand1, operand2) \
3033    ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) | \
3034      ((MI_MATH_OPERAND_##operand2) << 0) )
3035 
3036 #define MI_MATH_ALU1(opcode, operand1) \
3037    ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) )
3038 
3039 #define MI_MATH_ALU0(opcode) \
3040    ( ((MI_MATH_OPCODE_##opcode) << 20) )
3041 
3042 #define MI_MATH_OPCODE_NOOP      0x000
3043 #define MI_MATH_OPCODE_LOAD      0x080
3044 #define MI_MATH_OPCODE_LOADINV   0x480
3045 #define MI_MATH_OPCODE_LOAD0     0x081
3046 #define MI_MATH_OPCODE_LOAD1     0x481
3047 #define MI_MATH_OPCODE_ADD       0x100
3048 #define MI_MATH_OPCODE_SUB       0x101
3049 #define MI_MATH_OPCODE_AND       0x102
3050 #define MI_MATH_OPCODE_OR        0x103
3051 #define MI_MATH_OPCODE_XOR       0x104
3052 #define MI_MATH_OPCODE_STORE     0x180
3053 #define MI_MATH_OPCODE_STOREINV  0x580
3054 
3055 #define MI_MATH_OPERAND_R0   0x00
3056 #define MI_MATH_OPERAND_R1   0x01
3057 #define MI_MATH_OPERAND_R2   0x02
3058 #define MI_MATH_OPERAND_R3   0x03
3059 #define MI_MATH_OPERAND_R4   0x04
3060 #define MI_MATH_OPERAND_SRCA 0x20
3061 #define MI_MATH_OPERAND_SRCB 0x21
3062 #define MI_MATH_OPERAND_ACCU 0x31
3063 #define MI_MATH_OPERAND_ZF   0x32
3064 #define MI_MATH_OPERAND_CF   0x33
3065 
3066 /** @{
3067  *
3068  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
3069  * additional flushing control.
3070  */
3071 #define _3DSTATE_PIPE_CONTROL		(CMD_3D | (3 << 27) | (2 << 24))
3072 #define PIPE_CONTROL_CS_STALL		(1 << 20)
3073 #define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET	(1 << 19)
3074 #define PIPE_CONTROL_TLB_INVALIDATE	(1 << 18)
3075 #define PIPE_CONTROL_SYNC_GFDT		(1 << 17)
3076 #define PIPE_CONTROL_MEDIA_STATE_CLEAR	(1 << 16)
3077 #define PIPE_CONTROL_NO_WRITE		(0 << 14)
3078 #define PIPE_CONTROL_WRITE_IMMEDIATE	(1 << 14)
3079 #define PIPE_CONTROL_WRITE_DEPTH_COUNT	(2 << 14)
3080 #define PIPE_CONTROL_WRITE_TIMESTAMP	(3 << 14)
3081 #define PIPE_CONTROL_DEPTH_STALL	(1 << 13)
3082 #define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
3083 #define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11)
3084 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE	(1 << 10) /* GM45+ only */
3085 #define PIPE_CONTROL_ISP_DIS		(1 << 9)
3086 #define PIPE_CONTROL_INTERRUPT_ENABLE	(1 << 8)
3087 #define PIPE_CONTROL_FLUSH_ENABLE	(1 << 7) /* Gen7+ only */
3088 /* GT */
3089 #define PIPE_CONTROL_DATA_CACHE_FLUSH   	(1 << 5)
3090 #define PIPE_CONTROL_VF_CACHE_INVALIDATE	(1 << 4)
3091 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE	(1 << 3)
3092 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE	(1 << 2)
3093 #define PIPE_CONTROL_STALL_AT_SCOREBOARD	(1 << 1)
3094 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1 << 0)
3095 #define PIPE_CONTROL_PPGTT_WRITE	(0 << 2)
3096 #define PIPE_CONTROL_GLOBAL_GTT_WRITE	(1 << 2)
3097 
3098 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
3099    (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \
3100     PIPE_CONTROL_RENDER_TARGET_FLUSH)
3101 
3102 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
3103    (PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
3104     PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
3105     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
3106 
3107 /** @} */
3108 
3109 #define XY_SETUP_BLT_CMD		(CMD_2D | (0x01 << 22))
3110 
3111 #define XY_COLOR_BLT_CMD		(CMD_2D | (0x50 << 22))
3112 
3113 #define XY_SRC_COPY_BLT_CMD             (CMD_2D | (0x53 << 22))
3114 
3115 #define XY_FAST_COPY_BLT_CMD             (CMD_2D | (0x42 << 22))
3116 
3117 #define XY_TEXT_IMMEDIATE_BLIT_CMD	(CMD_2D | (0x31 << 22))
3118 # define XY_TEXT_BYTE_PACKED		(1 << 16)
3119 
3120 /* BR00 */
3121 #define XY_BLT_WRITE_ALPHA	(1 << 21)
3122 #define XY_BLT_WRITE_RGB	(1 << 20)
3123 #define XY_SRC_TILED		(1 << 15)
3124 #define XY_DST_TILED		(1 << 11)
3125 
3126 /* BR00 */
3127 #define XY_FAST_SRC_TILED_64K        (3 << 20)
3128 #define XY_FAST_SRC_TILED_Y          (2 << 20)
3129 #define XY_FAST_SRC_TILED_X          (1 << 20)
3130 
3131 #define XY_FAST_DST_TILED_64K        (3 << 13)
3132 #define XY_FAST_DST_TILED_Y          (2 << 13)
3133 #define XY_FAST_DST_TILED_X          (1 << 13)
3134 
3135 /* BR13 */
3136 #define BR13_8			(0x0 << 24)
3137 #define BR13_565		(0x1 << 24)
3138 #define BR13_8888		(0x3 << 24)
3139 #define BR13_16161616		(0x4 << 24)
3140 #define BR13_32323232		(0x5 << 24)
3141 
3142 #define XY_FAST_SRC_TRMODE_YF        (1 << 31)
3143 #define XY_FAST_DST_TRMODE_YF        (1 << 30)
3144 
3145 /* Pipeline Statistics Counter Registers */
3146 #define IA_VERTICES_COUNT               0x2310
3147 #define IA_PRIMITIVES_COUNT             0x2318
3148 #define VS_INVOCATION_COUNT             0x2320
3149 #define HS_INVOCATION_COUNT             0x2300
3150 #define DS_INVOCATION_COUNT             0x2308
3151 #define GS_INVOCATION_COUNT             0x2328
3152 #define GS_PRIMITIVES_COUNT             0x2330
3153 #define CL_INVOCATION_COUNT             0x2338
3154 #define CL_PRIMITIVES_COUNT             0x2340
3155 #define PS_INVOCATION_COUNT             0x2348
3156 #define CS_INVOCATION_COUNT             0x2290
3157 #define PS_DEPTH_COUNT                  0x2350
3158 
3159 #define GEN6_SO_PRIM_STORAGE_NEEDED     0x2280
3160 #define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
3161 
3162 #define GEN6_SO_NUM_PRIMS_WRITTEN       0x2288
3163 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)    (0x5200 + (n) * 8)
3164 
3165 #define GEN7_SO_WRITE_OFFSET(n)         (0x5280 + (n) * 4)
3166 
3167 #define TIMESTAMP                       0x2358
3168 
3169 #define BCS_SWCTRL                      0x22200
3170 # define BCS_SWCTRL_SRC_Y               (1 << 0)
3171 # define BCS_SWCTRL_DST_Y               (1 << 1)
3172 
3173 #define OACONTROL                       0x2360
3174 # define OACONTROL_COUNTER_SELECT_SHIFT  2
3175 # define OACONTROL_ENABLE_COUNTERS       (1 << 0)
3176 
3177 /* Auto-Draw / Indirect Registers */
3178 #define GEN7_3DPRIM_END_OFFSET          0x2420
3179 #define GEN7_3DPRIM_START_VERTEX        0x2430
3180 #define GEN7_3DPRIM_VERTEX_COUNT        0x2434
3181 #define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
3182 #define GEN7_3DPRIM_START_INSTANCE      0x243C
3183 #define GEN7_3DPRIM_BASE_VERTEX         0x2440
3184 
3185 /* Auto-Compute / Indirect Registers */
3186 #define GEN7_GPGPU_DISPATCHDIMX         0x2500
3187 #define GEN7_GPGPU_DISPATCHDIMY         0x2504
3188 #define GEN7_GPGPU_DISPATCHDIMZ         0x2508
3189 
3190 #define GEN7_CACHE_MODE_1               0x7004
3191 # define GEN8_HIZ_NP_PMA_FIX_ENABLE        (1 << 11)
3192 # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
3193 # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
3194 # define GEN8_HIZ_PMA_MASK_BITS \
3195    REG_MASK(GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE)
3196 
3197 /* Predicate registers */
3198 #define MI_PREDICATE_SRC0               0x2400
3199 #define MI_PREDICATE_SRC1               0x2408
3200 #define MI_PREDICATE_DATA               0x2410
3201 #define MI_PREDICATE_RESULT             0x2418
3202 #define MI_PREDICATE_RESULT_1           0x241C
3203 #define MI_PREDICATE_RESULT_2           0x2214
3204 
3205 #define HSW_CS_GPR(n) (0x2600 + (n) * 8)
3206 
3207 /* L3 cache control registers. */
3208 #define GEN7_L3SQCREG1                     0xb010
3209 /* L3SQ general and high priority credit initialization. */
3210 # define IVB_L3SQCREG1_SQGHPCI_DEFAULT     0x00730000
3211 # define VLV_L3SQCREG1_SQGHPCI_DEFAULT     0x00d30000
3212 # define HSW_L3SQCREG1_SQGHPCI_DEFAULT     0x00610000
3213 # define GEN7_L3SQCREG1_CONV_DC_UC         (1 << 24)
3214 # define GEN7_L3SQCREG1_CONV_IS_UC         (1 << 25)
3215 # define GEN7_L3SQCREG1_CONV_C_UC          (1 << 26)
3216 # define GEN7_L3SQCREG1_CONV_T_UC          (1 << 27)
3217 
3218 #define GEN7_L3CNTLREG2                    0xb020
3219 # define GEN7_L3CNTLREG2_SLM_ENABLE        (1 << 0)
3220 # define GEN7_L3CNTLREG2_URB_ALLOC_SHIFT   1
3221 # define GEN7_L3CNTLREG2_URB_ALLOC_MASK    INTEL_MASK(6, 1)
3222 # define GEN7_L3CNTLREG2_URB_LOW_BW        (1 << 7)
3223 # define GEN7_L3CNTLREG2_ALL_ALLOC_SHIFT   8
3224 # define GEN7_L3CNTLREG2_ALL_ALLOC_MASK    INTEL_MASK(13, 8)
3225 # define GEN7_L3CNTLREG2_RO_ALLOC_SHIFT    14
3226 # define GEN7_L3CNTLREG2_RO_ALLOC_MASK     INTEL_MASK(19, 14)
3227 # define GEN7_L3CNTLREG2_RO_LOW_BW         (1 << 20)
3228 # define GEN7_L3CNTLREG2_DC_ALLOC_SHIFT    21
3229 # define GEN7_L3CNTLREG2_DC_ALLOC_MASK     INTEL_MASK(26, 21)
3230 # define GEN7_L3CNTLREG2_DC_LOW_BW         (1 << 27)
3231 
3232 #define GEN7_L3CNTLREG3                    0xb024
3233 # define GEN7_L3CNTLREG3_IS_ALLOC_SHIFT    1
3234 # define GEN7_L3CNTLREG3_IS_ALLOC_MASK     INTEL_MASK(6, 1)
3235 # define GEN7_L3CNTLREG3_IS_LOW_BW         (1 << 7)
3236 # define GEN7_L3CNTLREG3_C_ALLOC_SHIFT     8
3237 # define GEN7_L3CNTLREG3_C_ALLOC_MASK      INTEL_MASK(13, 8)
3238 # define GEN7_L3CNTLREG3_C_LOW_BW          (1 << 14)
3239 # define GEN7_L3CNTLREG3_T_ALLOC_SHIFT     15
3240 # define GEN7_L3CNTLREG3_T_ALLOC_MASK      INTEL_MASK(20, 15)
3241 # define GEN7_L3CNTLREG3_T_LOW_BW          (1 << 21)
3242 
3243 #define HSW_SCRATCH1                       0xb038
3244 #define HSW_SCRATCH1_L3_ATOMIC_DISABLE     (1 << 27)
3245 
3246 #define HSW_ROW_CHICKEN3                   0xe49c
3247 #define HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE (1 << 6)
3248 
3249 #define GEN8_L3CNTLREG                     0x7034
3250 # define GEN8_L3CNTLREG_SLM_ENABLE         (1 << 0)
3251 # define GEN8_L3CNTLREG_URB_ALLOC_SHIFT    1
3252 # define GEN8_L3CNTLREG_URB_ALLOC_MASK     INTEL_MASK(7, 1)
3253 # define GEN8_L3CNTLREG_RO_ALLOC_SHIFT     11
3254 # define GEN8_L3CNTLREG_RO_ALLOC_MASK      INTEL_MASK(17, 11)
3255 # define GEN8_L3CNTLREG_DC_ALLOC_SHIFT     18
3256 # define GEN8_L3CNTLREG_DC_ALLOC_MASK      INTEL_MASK(24, 18)
3257 # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT    25
3258 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK     INTEL_MASK(31, 25)
3259 
3260 #endif
3261