Searched refs:BaseRegA (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 105 unsigned BaseRegA = 0, BaseRegB = 0; in areMemAccessesTriviallyDisjoint() local
108 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
110 if (BaseRegA == BaseRegB) { in areMemAccessesTriviallyDisjoint()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 660 unsigned BaseRegA = 0, BaseRegB = 0; in areMemAccessesTriviallyDisjoint() local
676 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
678 if (BaseRegA == BaseRegB) { in areMemAccessesTriviallyDisjoint()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1641 unsigned BaseRegA = getBaseAndOffset(&MIa, OffsetA, SizeA); in areMemAccessesTriviallyDisjoint() local
1642 if (!BaseRegA || !SizeA) in areMemAccessesTriviallyDisjoint()
1650 if (BaseRegA != BaseRegB) in areMemAccessesTriviallyDisjoint()
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