Searched refs:CIK_UCONFIG_REG_OFFSET (Results 1 – 6 of 6) sorted by relevance
98 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()101 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()114 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()117 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
186 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()189 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()202 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()205 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
72 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) { in si_pm4_set_reg()74 reg -= CIK_UCONFIG_REG_OFFSET; in si_pm4_set_reg()
33 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro
181 ac_parse_set_reg_packet(f, ib, count, CIK_UCONFIG_REG_OFFSET); in ac_parse_packet3()
34 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro