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Searched refs:CMP1 (Results 1 – 7 of 7) sorted by relevance

/external/llvm/test/Transforms/InstCombine/
Dand-fcmp.ll8 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord double %b, 0.000000e+00
9 ; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP]], [[CMP1]]
21 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord <2 x double> %b, zeroinitializer
22 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i1> [[CMP]], [[CMP1]]
1323 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp oeq double %a, %b
1324 ; CHECK-NEXT: ret i1 [[CMP1]]
1334 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ogt double %a, %b
1335 ; CHECK-NEXT: ret i1 [[CMP1]]
1345 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp oge double %a, %b
1346 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
Ddemorgan-zext.ll77 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 %y, 0
78 ; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP0]], [[CMP1]]
/external/llvm/test/Transforms/InstSimplify/
DAndOrXor.ll316 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 %i, 1
317 ; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16
333 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i16> %j, <i16 1, i16 1>
334 ; CHECK-NEXT: [[CONV1:%.*]] = zext <2 x i1> [[CMP1]] to <2 x i3>
/external/llvm/test/CodeGen/AMDGPU/
Dxor.ll44 ; SI-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 1.0, {{v[0-9]+}}
45 ; SI: s_xor_b64 [[XOR:vcc]], [[CMP0]], [[CMP1]]
Dllvm.amdgcn.div.fmas.ll113 ; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
114 ; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp13225 SDValue CMP1 = N1->getOperand(1); in CMPEQCombine() local
13229 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) in CMPEQCombine()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp27862 SDValue CMP1 = N1->getOperand(1); in combineCompareEqual() local
27866 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) in combineCompareEqual()