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Searched refs:CONV (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dcvt_f32_ubyte.ll8 ; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
9 ; SI: buffer_store_dword [[CONV]],
148 ; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]]
149 ; SI: buffer_store_dword [[CONV]],
192 ; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]]
193 ; SI: buffer_store_dword [[CONV]]
205 ; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]]
206 ; SI: buffer_store_dword [[CONV]]
219 ; SI: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]]
220 ; SI: buffer_store_dword [[CONV]]
[all …]
/external/mesa3d/src/mesa/main/
Dformat_utils.c801 #define SWIZZLE_CONVERT_LOOP(DST_TYPE, DST_CHANS, SRC_TYPE, SRC_CHANS, CONV) \ argument
807 tmp[j] = CONV; \
843 #define SWIZZLE_CONVERT(DST_TYPE, SRC_TYPE, CONV) \ argument
858 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 1, CONV); \
861 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 2, CONV); \
864 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 3, CONV); \
867 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 4, CONV); \
874 SWIZZLE_CONVERT_LOOP(DST_TYPE, 2, SRC_TYPE, 1, CONV); \
877 SWIZZLE_CONVERT_LOOP(DST_TYPE, 2, SRC_TYPE, 2, CONV); \
880 SWIZZLE_CONVERT_LOOP(DST_TYPE, 2, SRC_TYPE, 3, CONV); \
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/external/llvm/test/Transforms/InstSimplify/
Dshift-128-kb.ll9 ; CHECK: [[CONV:%.*]] = zext i32 %IntegerBitWidth to i64
10 ; CHECK-NEXT: [[SUB:%.*]] = sub i64 128, [[CONV]]
/external/llvm/test/CodeGen/X86/
Di386-shrink-wrapping.ll59 ; CHECK-NEXT: movsbl ([[F]]), [[CONV:%[a-z]+]]
60 ; CHECK-NEXT: movl $6, [[CONV:%[a-z]+]]
64 ; CHECK-NEXT: cmovnel {{%[a-z]+}}, [[CONV]]
/external/llvm/test/Transforms/InstCombine/
Ddiv-shift.ll7 ; CHECK-NEXT: [[CONV:%.*]] = zext i16 %x to i32
9 ; CHECK-NEXT: [[D:%.*]] = lshr i32 [[CONV]], [[TMP0]]
Ddiv.ll466 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 %x to i32
467 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], 128
477 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 %x to i32
478 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], -129
490 ; CHECK-NEXT: [[CONV:%.*]] = sext i16 %x to i32
491 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], 65535
D2004-11-27-SetCCForCastLargerAndConstant.ll33 ; CHECK-NEXT: [[CONV:%.*]] = sext i16 %a to i32
34 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[CONV]], or (i32 zext (i1 icmp ne (i32*** bitcast ([1 x…
Dicmp.ll1819 ; CHECK-NEXT: [[CONV:%.*]] = zext i8 %a to i32
1821 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[CONV]], [[CONV3]]
1901 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float %x to i32
1902 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[CONV]], %i
1913 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float %x to i32
1914 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], %i
1925 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float %x to i32
1926 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CONV]], %i
1937 ; CHECK-NEXT: [[CONV:%.*]] = fptosi float %x to i32
1938 ; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], %i
Dcast.ll1202 ; CHECK-NEXT: [[CONV:%.*]] = sext i16 %a to i32
1205 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[SH_PROM]]
/external/clang/test/CodeGenObjC/
Darm64-int32-ivar.m15 // CHECK: [[CONV:%.*]] = sext i32 [[IVAR]] to i64
Dproperty-type-mismatch.m15 // CHECK: [[CONV:%.*]] = fptosi float [[I]] to i32
/external/python/cpython2/Lib/compiler/
Dpyassem.py251 CONV = "CONV" variable
312 assert self.stage == CONV
417 self.stage = CONV
505 assert self.stage == CONV
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp1500 #define CONV(X) \ in CCMaskForCondCode() macro
1509 CONV(EQ); in CCMaskForCondCode()
1510 CONV(NE); in CCMaskForCondCode()
1511 CONV(GT); in CCMaskForCondCode()
1512 CONV(GE); in CCMaskForCondCode()
1513 CONV(LT); in CCMaskForCondCode()
1514 CONV(LE); in CCMaskForCondCode()
1519 #undef CONV in CCMaskForCondCode()
/external/libmtp/src/
Dptp-pack.c2020 #define XX( TYPE, CONV )\ in ptp_unpack_CANON_changes() argument
2026 dpd->FORM.Enum.SupportedValue[j].TYPE = CONV(xdata); \ in ptp_unpack_CANON_changes()
2027 ptp_debug (params, "event %d: suppval[%d] of %x is 0x%x.", i, j, proptype, CONV(xdata)); \ in ptp_unpack_CANON_changes()