Home
last modified time | relevance | path

Searched refs:COPY_TO_REGCLASS (Results 1 – 25 of 48) sorted by relevance

12

/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPU64InstrInfo.td57 CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
58 (COPY_TO_REGCLASS R64C:$rB, VECREG))), 0xb)>;
70 def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQr64compare.Fragment, R32C))>;
71 def v2i64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQv2i64compare.Fragment, R32C))>;
74 def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
76 def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
94 CodeFrag<(CLGTv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
95 (COPY_TO_REGCLASS R64C:$rB, VECREG))>;
98 CodeFrag<(CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
99 (COPY_TO_REGCLASS R64C:$rB, VECREG))>;
[all …]
DSPUISelDAGToDAG.cpp766 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, in Select()
850 Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT, in Select()
923 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, in SelectSHLi64()
968 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSHLi64()
990 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, in SelectSRLi64()
1037 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRLi64()
1059 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1067 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1115 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1143 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, in SelectI64Constant()
[all …]
DSPUInstrInfo.td1428 (COPY_TO_REGCLASS R8C:$rA, VECREG)>;
1431 (COPY_TO_REGCLASS R16C:$rA, VECREG)>;
1434 (COPY_TO_REGCLASS R32C:$rA, VECREG)>;
1437 (COPY_TO_REGCLASS R64C:$rA, VECREG)>;
1440 (COPY_TO_REGCLASS R32FP:$rA, VECREG)>;
1443 (COPY_TO_REGCLASS R64FP:$rA, VECREG)>;
1446 (COPY_TO_REGCLASS (v16i8 VECREG:$rA), R8C)>;
1449 (COPY_TO_REGCLASS (v8i16 VECREG:$rA), R16C)>;
1452 (COPY_TO_REGCLASS (v4i32 VECREG:$rA), R32C)>;
1455 (COPY_TO_REGCLASS (v2i64 VECREG:$rA), R64C)>;
[all …]
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td607 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
616 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
1337 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1344 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1548 (COPY_TO_REGCLASS (VPCMPGTDZrr
1553 (COPY_TO_REGCLASS (VPCMPEQDZrr
1807 (COPY_TO_REGCLASS (VCMPPSZrri
1812 (COPY_TO_REGCLASS (VPCMPDZrri
1817 (COPY_TO_REGCLASS (VPCMPUDZrri
2032 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
[all …]
DX86InstrSSE.td334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
588 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
590 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
592 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
597 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
[all …]
DX86InstrCompiler.td1447 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1454 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1489 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1496 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1528 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1532 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1550 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1554 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1558 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1564 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
[all …]
DX86InstrFPStack.td714 def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
716 def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
718 def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
724 def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
726 def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
728 def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
DX86InstrFMA.td243 (COPY_TO_REGCLASS(!cast<Instruction>(NAME#"SSr213r_Int")
247 (COPY_TO_REGCLASS(!cast<Instruction>(NAME#"SDr213r_Int")
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td883 (COPY_TO_REGCLASS $A, VSRC)>;
885 (COPY_TO_REGCLASS $A, VSRC)>;
887 (COPY_TO_REGCLASS $A, VSRC)>;
889 (COPY_TO_REGCLASS $A, VSRC)>;
892 (COPY_TO_REGCLASS $A, VRRC)>;
894 (COPY_TO_REGCLASS $A, VRRC)>;
896 (COPY_TO_REGCLASS $A, VRRC)>;
898 (COPY_TO_REGCLASS $A, VRRC)>;
901 (COPY_TO_REGCLASS $A, VSRC)>;
903 (COPY_TO_REGCLASS $A, VSRC)>;
[all …]
DPPCInstrQPX.td880 (QVFCPSGN (COPY_TO_REGCLASS $frA, QFRC), $frB)>;
882 (QVFCPSGNs (COPY_TO_REGCLASS $frA, QSRC), $frB)>;
1107 (COPY_TO_REGCLASS $src, QFRC)>;
1110 (COPY_TO_REGCLASS $src, QSRC)>;
1115 (COPY_TO_REGCLASS $src, QFRC)>;
DPPCVSXSwapRemoval.cpp427 case PPC::COPY_TO_REGCLASS: in gatherVectorInstructions()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetOpcodes.h66 COPY_TO_REGCLASS = 10, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrCompiler.td1224 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1231 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1259 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1266 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1298 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1302 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1320 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1324 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1330 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1335 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
[all …]
DX86InstrFPStack.td633 def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
635 def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
637 def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
643 def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
645 def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
647 def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
/external/llvm/test/CodeGen/PowerPC/
Dfast-isel-fpconv.ll4 ; of COPY_TO_REGCLASS in the FastISel pass. Verify that this is fixed.
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3555 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3613 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3621 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3636 (COPY_TO_REGCLASS
3638 (COPY_TO_REGCLASS
3639 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3756 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3761 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3766 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3771 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
[all …]
DMipsDSPInstrInfo.td1315 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1323 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1325 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1327 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1329 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1374 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1382 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelDAGToDAG.cpp169 DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, in FixRegisterClasses()
DBlackfinInstrInfo.td470 (STORE16pi (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$val, D)),
474 (STORE16pi (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$val, D)),
479 (i16 (COPY_TO_REGCLASS D16L:$val, D16L)),
530 (i16 (COPY_TO_REGCLASS D16L:$src, D16L)),
862 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$src, D)), lo16)>;
/external/llvm/include/llvm/Target/
DTargetOpcodes.def64 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
70 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS, 10)
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td742 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
745 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
748 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
751 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
821 (COPY_TO_REGCLASS
825 (COPY_TO_REGCLASS
831 (COPY_TO_REGCLASS
835 (COPY_TO_REGCLASS
1263 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1281 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
[all …]
DARMInstrNEON.td5866 (COPY_TO_REGCLASS
5870 (COPY_TO_REGCLASS
5874 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5877 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5936 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5939 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
6591 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
6593 (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
6600 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6607 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td564 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
566 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
3940 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3943 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3947 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3950 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
5511 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5512 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5513 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5514 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td22 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td4430 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4433 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4488 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4491 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4919 (v2f32 (COPY_TO_REGCLASS (Inst
4921 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4927 (v2f32 (COPY_TO_REGCLASS (Inst
4929 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4932 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4938 (v2f32 (COPY_TO_REGCLASS (Inst
[all …]

12