Searched refs:CTX_PP_CNTL (Results 1 – 10 of 10) sorted by relevance
341 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_MULTI_PASS_ENABLE | in r200UpdateFSRouting()351 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[0] == 8 ? in r200UpdateFSRouting()355 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_MULTI_PASS_ENABLE; in r200UpdateFSRouting()356 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[1] == 8 ? in r200UpdateFSRouting()388 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()407 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()469 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()496 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()
908 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_BLEND_ENABLE_MASK | R200_MULTI_PASS_ENABLE); in r200UpdateAllTexEnv()909 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= rmesa->state.envneeded << R200_TEX_BLEND_0_ENABLE_SHIFT; in r200UpdateAllTexEnv()952 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_0_ENABLE << unit); in disable_tex_obj_state()1423 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << unit; in r200_validate_texture()1521 if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_ENABLE_MASK) == R200_TEX_0_ENABLE && in r200UpdateTextureState()1526 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_1_ENABLE; in r200UpdateTextureState()1532 if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE) && in r200UpdateTextureState()1547 if (!(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE)) in r200UpdateTextureState()
765 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL]; in r200UpdateSpecular()814 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) { in r200UpdateSpecular()816 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p; in r200UpdateSpecular()1685 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ALPHA_TEST_ENABLE; in r200Enable()1687 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ALPHA_TEST_ENABLE; in r200Enable()1745 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_FOG_ENABLE; in r200Enable()1748 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_FOG_ENABLE; in r200Enable()1796 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_LINE; in r200Enable()1798 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ANTI_ALIAS_LINE; in r200Enable()1873 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_POLY; in r200Enable()[all …]
106 #define CTX_PP_CNTL 9 macro
506 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); in ctx_emit_cs()960 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE in r200InitState()
568 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL]; in radeonUpdateSpecular()631 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) { in radeonUpdateSpecular()633 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p; in radeonUpdateSpecular()1468 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ALPHA_TEST_ENABLE; in radeonEnable()1470 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ALPHA_TEST_ENABLE; in radeonEnable()1554 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_FOG_ENABLE; in radeonEnable()1557 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_FOG_ENABLE; in radeonEnable()1603 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ANTI_ALIAS_LINE; in radeonEnable()1605 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ANTI_ALIAS_LINE; in radeonEnable()1612 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_PATTERN_ENABLE; in radeonEnable()[all …]
103 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE); in radeonEmitScissor()114 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE); in radeonEmitScissor()
97 #define CTX_PP_CNTL 9 macro
1004 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= in radeon_validate_texture()1066 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~((RADEON_TEX_ENABLE_MASK) | (RADEON_TEX_BLEND_ENABLE_MASK)); in radeonUpdateTextureState()
389 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); in ctx_emit_cs()703 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | in radeonInitState()