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Searched refs:CTX_RB3D_CNTL (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_state_init.c334 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); in ctx_emit_cs()
336 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; in ctx_emit_cs()
340 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; in ctx_emit_cs()
344 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; in ctx_emit_cs()
348 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; in ctx_emit_cs()
390 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); in ctx_emit_cs()
706 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | in radeonInitState()
711 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; in radeonInitState()
714 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; in radeonInitState()
724 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; in radeonInitState()
[all …]
Dradeon_state.c146 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE; in radeonBlendEquationSeparate()
148 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE; in radeonBlendEquationSeparate()
1477 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ALPHA_BLEND_ENABLE; in radeonEnable()
1479 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ALPHA_BLEND_ENABLE; in radeonEnable()
1483 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE; in radeonEnable()
1485 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE; in radeonEnable()
1534 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_Z_ENABLE; in radeonEnable()
1536 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_Z_ENABLE; in radeonEnable()
1543 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; in radeonEnable()
1544 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->radeon.state.color.roundEnable; in radeonEnable()
[all …]
Dradeon_context.h98 #define CTX_RB3D_CNTL 10 macro
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_state.c208 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & in r200_set_blend_state()
221 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE; in r200_set_blend_state()
226 … rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE; in r200_set_blend_state()
229 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl; in r200_set_blend_state()
685 GLuint flag = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & ~R200_PLANE_MASK_ENABLE; in r200ColorMask()
700 if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) { in r200ColorMask()
702 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag; in r200ColorMask()
1725 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_Z_ENABLE; in r200Enable()
1727 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_Z_ENABLE; in r200Enable()
1734 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; in r200Enable()
[all …]
Dr200_state_init.c450 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); in ctx_emit_cs()
452 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; in ctx_emit_cs()
456 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; in ctx_emit_cs()
460 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; in ctx_emit_cs()
464 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; in ctx_emit_cs()
507 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); in ctx_emit_cs()
965 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; in r200InitState()
968 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE; in r200InitState()
978 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; in r200InitState()
980 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; in r200InitState()
Dr200_context.h107 #define CTX_RB3D_CNTL 10 macro