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Searched refs:CurOp (Results 1 – 11 of 11) sorted by relevance

/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp708 unsigned CurOp = X86II::getOperandBias(Desc); in EmitVEXOpcodePrefix() local
727 CurOp += X86::AddrNumOperands; in EmitVEXOpcodePrefix()
730 EVEX_aaa = getX86RegEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
733 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
738 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
753 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
758 EVEX_aaa = getX86RegEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
761 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
779 VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf; in EmitVEXOpcodePrefix()
790 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
[all …]
DX86BaseInfo.h632 unsigned CurOp = 0; in getOperandBias() local
634 ++CurOp; in getOperandBias()
639 CurOp += 2; in getOperandBias()
644 CurOp += 2; in getOperandBias()
647 ++CurOp; in getOperandBias()
648 return CurOp; in getOperandBias()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86CodeEmitter.cpp718 unsigned CurOp = 0; in emitInstruction() local
720 ++CurOp; in emitInstruction()
769 CurOp = NumOps; in emitInstruction()
774 if (CurOp == NumOps) in emitInstruction()
777 const MachineOperand &MO = MI.getOperand(CurOp++); in emitInstruction()
779 DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n"); in emitInstruction()
821 X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg())); in emitInstruction()
823 if (CurOp == NumOps) in emitInstruction()
826 const MachineOperand &MO1 = MI.getOperand(CurOp++); in emitInstruction()
855 emitRegModRMByte(MI.getOperand(CurOp).getReg(), in emitInstruction()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp496 unsigned CurOp = 0; in EmitVEXOpcodePrefix() local
510 CurOp = X86::AddrNumOperands; in EmitVEXOpcodePrefix()
512 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
514 const MCOperand &MO = MI.getOperand(CurOp); in EmitVEXOpcodePrefix()
560 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) in EmitVEXOpcodePrefix()
562 CurOp++; in EmitVEXOpcodePrefix()
565 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
566 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) in EmitVEXOpcodePrefix()
851 unsigned CurOp = 0; in EncodeInstruction() local
853 ++CurOp; in EncodeInstruction()
[all …]
/external/llvm/utils/TableGen/
DDAGISelMatcherGen.cpp530 unsigned CurOp = NextRecordedOperandNo; in EmitMatcherCode() local
532 NamedComplexPatternOperands[N->getChild(i)->getName()] = CurOp + 1; in EmitMatcherCode()
533 CurOp += N->getChild(i)->getNumMIResults(CGP); in EmitMatcherCode()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGISel.cpp1943 unsigned CurOp = InlineAsm::Op_FirstOperand; in SelectInlineAsmMemoryOperands() local
1944 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue(); in SelectInlineAsmMemoryOperands()
1946 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1; in SelectInlineAsmMemoryOperands()
1947 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue(); in SelectInlineAsmMemoryOperands()
DSelectionDAGBuilder.cpp6876 unsigned CurOp = InlineAsm::Op_FirstOperand; in visitInlineAsm() local
6880 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); in visitInlineAsm()
6884 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; in visitInlineAsm()
6888 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); in visitInlineAsm()
6902 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); in visitInlineAsm()
6936 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); in visitInlineAsm()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp6092 unsigned CurOp = InlineAsm::Op_FirstOperand; in visitInlineAsm() local
6096 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); in visitInlineAsm()
6100 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; in visitInlineAsm()
6104 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); in visitInlineAsm()
6118 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); in visitInlineAsm()
6144 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); in visitInlineAsm()
/external/llvm/docs/
DWritingAnLLVMBackend.rst1850 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
1852 if (CurOp != NumOps) {
1853 const MachineOperand &MO1 = MI.getOperand(CurOp++);
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8964 SDValue CurOp = PreOp.getOperand(0); in tryMatchAcrossLaneShuffleForReduction() local
8969 CurOp = PreOp.getOperand(1); in tryMatchAcrossLaneShuffleForReduction()
8978 if (CurOp.getOpcode() != Op && (CurStep != (NumExpectedSteps - 1))) in tryMatchAcrossLaneShuffleForReduction()
8986 if (Shuffle.getOperand(0) != CurOp) in tryMatchAcrossLaneShuffleForReduction()
9006 PreOp = CurOp; in tryMatchAcrossLaneShuffleForReduction()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp23746 unsigned CurOp = 0; in emitEHSjLjSetJmp() local
23748 DstReg = MI.getOperand(CurOp++).getReg(); in emitEHSjLjSetJmp()
23754 MemOpndSlot = CurOp; in emitEHSjLjSetJmp()